CN103426924A - Groove-type power MOSFET and manufacturing method thereof - Google Patents

Groove-type power MOSFET and manufacturing method thereof Download PDF

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CN103426924A
CN103426924A CN 201210147143 CN201210147143A CN103426924A CN 103426924 A CN103426924 A CN 103426924A CN 201210147143 CN201210147143 CN 201210147143 CN 201210147143 A CN201210147143 A CN 201210147143A CN 103426924 A CN103426924 A CN 103426924A
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drift region
trench
power mosfet
doping concentration
drift
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CN 201210147143
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Chinese (zh)
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周宏伟
阮孟波
吴宗宪
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无锡华润上华半导体有限公司
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    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7813Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843Source or drain regions of field-effect devices
    • H01L29/0847Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • H01L29/0852Source or drain regions of field-effect devices of field-effect transistors with insulated gate of DMOS transistors
    • H01L29/0873Drain regions
    • H01L29/0878Impurity concentration or distribution
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66477Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66712Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/66734Vertical DMOS transistors, i.e. VDMOS transistors with a step of recessing the gate electrode, e.g. to form a trench gate electrode

Abstract

The invention provides a groove-type power MOSFET and a manufacturing method thereof, and belongs to the technical field of a groove-type power MOSFET. The manufacturing method includes the steps that a semi-conductor substrate is provided, a first drift region grows and forms on the substrate, the first drift region is constructed and etched to form a second groove, a semi-conductor layer is formed in the second groove in an epitaxial growth mode so that a second drift region filling the bottom of the second groove partially can be formed, the doping concentration of the second drift region is higher than that of the first drift region, and a grid groove structure is formed in the second groove above the second drift region. The process of the manufacturing method is simple and reliable, and the on resistance of the groove-type power MOSFET formed in the method is small.

Description

沟槽型功率MOSFET及其制备方法 A trench type power MOSFET and method of preparation

技术领域 FIELD

[0001] 本发明属于沟槽型功率MOSFET (金属-氧化物-半导体场效应晶体管)技术领域,涉及一种栅沟槽结构正下方的漂移层通过单独的外延生长过程形成来降低该区域的电阻率的沟槽型功率MOSFET及其制备方法。 [0001] The present invention pertains to a trench type power MOSFET is reduced by an epitaxial growth process for forming a separate resistance technical field relates to a trench gate structure directly below the region of the drift layer (Metal - Semiconductor Field Effect Transistor - oxide) a trench type power MOSFET and a preparation method rate.

背景技术 Background technique

[0002] 沟槽型功率MOSFET是一种常见的功率型器件,其是大电流开关主流器件之一,广泛应用于高压大电流情况下,例如,应用于同步整流中。 [0002] The trench power MOSFET is a common type power device, which is one of the main current switching device is widely used in high current at high voltage, e.g., applied to the synchronous rectification. 而沟槽型功率MOSFET的导通电阻是其非常重要的参数之一,例如,在同步整流应用中,导通电阻越小,能量转换效率越高。 And trench type power MOSFET on-resistance is one of very important parameters, e.g., the synchronous rectifier applications, on-resistance, the higher the energy conversion efficiency. 因此,本领域不断追求减小沟槽型功率MOSFET的导通电阻。 Accordingly, the art constantly striving to reduce the trench type power MOSFET on-resistance.

[0003] 沟槽型功率MOSFET中一般包括漂移(drift)区,其电阻的大小对沟槽型功率MOSFET的整个导通电阻影响非常大。 [0003] The trench power MOSFET typically includes a drift (Drift) region, which affect the on-resistance of the magnitude of the resistance of a trench power MOSFET global pilot is very large. 因此,减小漂移区在器件导通时的电阻有利于减小沟槽型功率MOSFET的导通电阻。 Thus, reducing the resistance of the drift region when the device is turned facilitates reducing a trench power MOSFET on-resistance.

[0004]美国专利号为 US7202525B2、名称为“Trench MOSFET with Trench TipImplants”的专利中,也提出了减小漂移区的电阻的方法,即漂移层中的沟槽末端(TrenchTip)结构通过离子注入形成,并通过离子注入掺杂降低其电阻率。 [0004] U.S. Patent No. US7202525B2, entitled "Trench MOSFET with Trench TipImplants" patent also proposes a method of reducing the resistance of the drift region, i.e., the end of the trench in the drift layer (TrenchTip) structure is formed by ion implantation and doped by ion implantation to reduce its resistivity. 但是,该专利的制备方法及其结构中,沟槽末端(Trench Tip)是通过离子注入掺杂构图形成,而受离子注入工艺方法特征的限制,离子注入的深度有限,并且特别是在注入半径和质量较大的掺杂原子时,难以形成高掺杂浓度的沟槽末端。 However, this patent preparation and their configuration, the end of the trench (Trench Tip) is formed by ion implantation doping composition, but by an ion implantation process for limiting characteristics, limited depth of ion implantation, and in particular the injection radius and the larger the mass of dopant atoms, it is difficult to form a high doping concentration of the channel end. 因此,这种结构在降低漂移区的导通电阻方面有限。 Therefore, this structure is limited in reducing the on-resistance of the drift region.

发明内容 SUMMARY

[0005] 本发明的目的在于,降低沟槽型功率MOSFET的导通电阻。 Objective [0005] The present invention is to reduce the ON resistance of the trench type power MOSFET.

[0006] 为实现以上目的或者其他目的,本发明提供以下技术方案。 [0006] In order to achieve the above object or other objects, the present invention provides the following technical solutions.

[0007] 按照本发明的一方面,提供一种沟槽型功率M0SFET,至少包括栅沟槽和漂移层,所述漂移层包括所述栅沟槽结构正下方的第二漂移区以及所述第二漂移区之外的第一漂移区,所述第二漂移区通过单独的外延生长过程形成以使所述第二漂移区的掺杂浓度高于所述第一漂移区的掺杂浓度。 [0007] According to an aspect of the present invention, there is provided a trench-type power M0SFET, comprising at least the gate trench and the drift layer, the drift layer comprises a drift region of the second trench gate structure directly below the first and a first drift region outside the two drift region, the drift region is formed so that the second doping concentration of the second drift region is higher than the first doping concentration of the drift region by a single epitaxial growth process.

[0008] 按照本发明一实施例的沟槽型功率M0SFET,其中,所述第二漂移区的掺杂浓度的范围掺杂浓度范围为IX IO15离子/cm3至IX IO18离子/cm3。 [0008] The trench power M0SFET according to an embodiment of the present invention, wherein the second doping concentration range of the drift region doping concentration ranging IX IO15 ions / cm3 to IX IO18 ions / cm3.

[0009] 较佳地,所述第二漂移区的厚度范围为3微米至20微米。 [0009] Preferably, the thickness of the second drift region is 3 to 20 microns.

[0010] 按照本发明一实施例的沟槽型功率M0SFET,其中,所述第二漂移区的导电类型与所述第一漂移区的导电类型相同。 [0010] The groove type power M0SFET an embodiment of the present invention, wherein the second conductive type drift region and the drift region of the first conductivity type is the same.

[0011] 按照本发明的又一方面,提供一种沟槽型功率MOSFET的制备方法,其包括以下步骤: [0011] According to still another aspect of the present invention, there is provided a method of preparing a trench power MOSFET comprising the steps of:

提供半导体衬底; Providing a semiconductor substrate;

在所述衬底上生长形成第一漂移区; 对所述第一漂移区构图刻蚀形成第二沟槽; Growing on said substrate forming a first drift region; the first drift region patterned etched to form a second trench;

在所述第二沟槽中外延生长半导体层以形成部分地填充所述第二沟槽底部的第二漂移区,并且,所述第二漂移区的掺杂浓度高于所述第一漂移区的掺杂浓度;以及在所述第二漂移区上方、所述第二沟槽内形成栅沟槽结构。 In the second trench epitaxially growing a semiconductor layer to form a second drift region of the bottom of the second trench is filled partially, and the second doping concentration of the drift region is higher than the first drift region doping concentration; and above the second drift region, the second trench forming a gate trench structure.

[0012] 按照本发明一实施例的制备方法,其中,形成所述第二漂移区的步骤,包括步骤: 在所述第二沟槽中外延生长填充所述第二沟槽的半导体层;以及 [0012] The production method according to an embodiment of the present invention, wherein the step of the second drift region, comprising the step of forming: a second trench in the epitaxial growth of the second trench is filled semiconductor layer;

对所述第二沟槽中的半导体层进行回刻蚀以形成所述第二漂移区。 Said second semiconductor layer in the trench etched back to form the second drift region.

[0013] 按照本发明又一实施例的制备方法,其中,所述第二漂移区的掺杂浓度范围为IX IO15 离子/cm3 至IX IO18 离子/cm3。 Example of preparation [0013] According to a further embodiment of the present invention, wherein the second doping concentration of said drift region of ions IX IO15 / cm3 to IX IO18 ions / cm3.

[0014] 在之前所述任一实施例的制备方法中,优选地,所述第二漂移区的掺杂浓度在平行于所述半导体衬底表面的方向上、基于所述第二沟槽的中央轴线呈正态分布。 [0014] In the production method according to any one of the previous embodiment, the doping concentration preferably, the second drift region in a direction parallel to the surface of the semiconductor substrate, based on the second trench a central axis normal distribution.

[0015] 在之前所述任一实施例的制备方法中,优选地,所述第二漂移区的厚度范围为3微米至20微米;所述第二漂移区的厚度小于所述第一漂移区的厚度。 [0015] In a preparation method according to any previous embodiment, the preferred thickness range, the second drift region is 3 to 20 microns; thickness of the second drift region is less than the first drift region thickness of.

[0016] 其中,所述第二漂移区的导电类型与所述第一漂移区的导电类型相同。 [0016] wherein the second conductive type drift region and the drift region of the first conductivity type is the same.

[0017] 在之前所述任一实施例的制备方法中,优选地,所述第一漂移区的掺杂浓度范围为IX IO14 离子/cm3 至IX IO17 原子/cm3。 [0017] In a preparation method according to any previous embodiment, preferably, the doping concentration of said first drift region for ion IX IO14 / cm3 to IX IO17 atoms / cm3.

[0018] 在之前所述任一实施例的制备方法中,优选地,所述第一漂移区的厚度范围为3微米至40微米。 [0018] In one embodiment of the production method according to any previous embodiment, preferably a thickness of the first drift region is 3 to 40 micrometers.

[0019] 在之前所述任一实施例的制备方法中,优选地,所述第一漂移区通过在所述半导体衬底上外延生长形成。 [0019] The production method according to any previous embodiment, preferably, the first drift region formed by epitaxial growth in one embodiment passed over the semiconductor substrate.

[0020] 本发明的技术效果是,栅沟槽结构下方的第二漂移区通过单独的外延生长工艺形成,其可以形成高掺杂浓度、低电阻率的区域,并且,其厚度、掺杂浓度不容易受工艺限制,因此,能有效地降低该沟槽型功率MOSFET的导通电阻。 [0020] Technical effects of the invention, the second drift region below the trench gate structure formed by a single epitaxial growth process, highly doped, low resistivity region which can be formed, and a thickness, doping concentration not easily limited by technology, therefore, can effectively reduce the oN resistance of the trench power MOSFET. 另外,其制备方法过程是基于成熟 Further, their preparation process is based on the mature

工艺,简单可靠。 Technology, simple and reliable.

附图说明 BRIEF DESCRIPTION

[0021] 从结合附图的以下详细说明中,将会使本发明的上述和其他目的及优点更加完全清楚,其中,相同或相似的要素采用相同的标号表示。 [0021] from the following detailed description in conjunction with the drawings, will make the above and other objects and advantages of the present invention will become more fully understood, in which the same or similar elements use the same reference numerals.

[0022] 图1是按照本发明一实施例提供的制备沟槽型功率MOSFET的方法流程示意图。 [0022] FIG. 1 is a schematic process flow according to the preparation of a trench type power MOSFET according to an embodiment of the present invention.

[0023] 图2至图9是对应于图1所示方法流程的结构变化示意图,其中,图9是按照本发明一实施例提供的沟槽型功率MOSFET的截面结构示意图。 [0023] FIGS. 2 to 9 are corresponding to the flow of the method shown in Figure 1 a schematic structural changes, wherein FIG. 9 is a schematic sectional structural diagram of a trench power MOSFET according to an embodiment of the present invention.

具体实施方式 detailed description

[0024] 下面介绍的是本发明的多个可能实施例中的一些,旨在提供对本发明的基本了解,并不旨在确认本发明的关键或决定性的要素或限定所要保护的范围。 [0024] The following is a description of a plurality of possible embodiments of the present invention, in some embodiments, are intended to provide a basic understanding of the invention and is not intended to identify key scope of the invention defined or critical elements or to be protected. 容易理解,根据本发明的技术方案,在不变更本发明的实质精神下,本领域的一般技术人员可以提出可相互替换的其他实现方式。 Readily appreciated that the solution according to the invention, in the true spirit of the present invention is not changed, those skilled in the art may make other alternative implementations mutually. 因此,以下具体实施方式以及附图仅是对本发明的技术方案的示例性说明,而不应当视为本发明的全部或者视为对本发明技术方案的限定或限制。 Accordingly, the following detailed description and drawings are merely illustrative of the technical solution of the present invention and should not be considered all or is deemed to define or limit the invention to the aspect of the present invention.

[0025] 在附图中,为了清楚起见,夸大了层和区域的厚度,并且,由于刻蚀引起的圆润等形状特征未在附图中示意出。 [0025] In the drawings, for clarity, are exaggerated, and the layer thickness of the region, and, since the characteristic rounded shape such etching is not caused in the drawings is schematically shown.

[0026] 在本文描述中,使用方向性术语(例如“上”、“下”、“背面”、“横向”等)以及类似术语来描述的各种结构实施例表示附图中示出的方向或者能被本领域技术人员理解的方向。 Example [0026] In the description herein, directional terms used (e.g., "upper", "lower", "back", "horizontal", etc.) and like terms to describe the various structures shown in the direction represented by reference direction or it can be appreciated by those skilled in the art. 这些方向性术语用于相对的描述和澄清,而不是要将任何实施例的定向限定到具体的方向或定向。 These directional terms used to describe and clarify the relative, rather than the orientation of any embodiment want to be limited to a particular direction or orientation.

[0027] 以下以沟槽型功率NM0SFET为例对本发明的沟槽型功率MOSFET的制备方法及其结构进行说明。 [0027] In the following an example of a trench-type power NM0SFET trench type power MOSFET of the present invention and its production method will be described.

[0028] 图1所示为按照本发明一实施例提供的制备沟槽型功率MOSFET的方法流程示意图。 [0028] Figure 1 is a schematic process flow according to the preparation of a trench type power MOSFET according to an embodiment of the present invention. 图2至图9所示为对应于图1所示方法流程的结构变化示意图,因此,通过图1所示的方法,最终地形成如图9所示的本发明实施例的沟槽型功率MOSFET 30。 2 to FIG. 9 is a schematic view corresponding to changes in flow of the method shown in Figure 1, therefore, by the method shown in FIG. 1, ultimately forming a trench type power MOSFET of the embodiment of the present invention is shown in FIG. 9 30. 以下图2至图9中,定义垂直于半导体衬底表面的方向为z坐标方向,其也即沟槽的深度方向,并且z坐标的正方向为指向沟槽开口的方向,z坐标的负方向为指向半导体衬底上用于形成漏电极的一面(即半导体衬底的背面)的方向;定义平行于半导体衬底表面的方向为X坐标方向。 In the following Figures 2 to 9, is defined in a direction perpendicular to the semiconductor substrate surface as a z-coordinate direction, i.e. its depth direction of the trench, and the positive direction of the z coordinate is the direction pointing trench opening, the negative direction of the z-coordinate is a point on a semiconductor substrate for forming the drain electrode side direction (i.e., the back surface of the semiconductor substrate); a direction parallel to the semiconductor substrate surface is defined as X-coordinate direction. 以下结合图2至图9对制备图9所示实施例沟槽型功率MOSFET的方法进行详细说明,并同时说明图9所示实施例的沟槽型功率MOSFET单元结构。 Below in conjunction with FIGS. 2 to 9 prepared in the method embodiment shown in FIG. 9 a trench type power MOSFET will be described in detail, and also described a trench type power MOSFET cell structure of the embodiment shown in FIG.

[0029] 首先,步骤S110,提供N型半导体衬底310。 [0029] First, step S110, the N-type semiconductor substrate 310 provided.

[0030] 参阅图2,半导体衬底310可以选择采用N型高掺杂的晶圆(wafer),也即N-单晶晶圆,半导体衬底310最终在该实施例中处于漂移层与漏电极之间,其可以用来形成漏端电极,因此,半导体衬底310的掺杂浓度在IX IO19离子/cm3至5 X IO19离子/cm3内选择,例如为2.5 X IO19 离子/cm3。 [0030] Referring to Figure 2, the semiconductor substrate 310 can select a highly doped N-type wafer (the wafer), i.e. N- monocrystalline wafer, a semiconductor substrate 310 in this embodiment, eventually in the drift layer and the drain between the electrode, which can be used to form the drain terminal electrode, the doping concentration of the semiconductor substrate 310 is selected in the IX IO19 ions / cm3 to 5 X IO19 ions / cm3, for example, 2.5 X IO19 ions / cm3.

[0031] 进一步,步骤S120,在该半导体衬底上外延生长N型半导体层320,并且在半导体层320上生长氧化层391和氮化硅层392。 [0031] Further, step S120, where the semiconductor substrate is epitaxially grown on the N-type semiconductor layer 320, and oxide layer 391 is grown and a nitride layer 392 on the semiconductor layer 320.

[0032] 参阅图3,在该实施例中,外延生长的半导体层320与半导体衬底310为相同导电类型,其为N型,但是,其掺杂浓度要低于半导体衬底310的掺杂浓度。 [0032] Referring to Figure 3, in this embodiment, the semiconductor layer 320 and the semiconductor substrate 310 is epitaxially grown the same conductivity type, which is N-type, however, lower than the dopant concentration of the doped semiconductor substrate 310 concentration. 半导体层320在最终的部分用来形成沟槽型功率MOSFET的漂移层(即第一漂移区320a),因此,其选择相对较低的掺杂浓度以保证沟槽型功率MOSFET的击穿(BV)电压性能要求。 The semiconductor layer 320 in the final portion of the drift layer for forming a trench power MOSFET (i.e., a first drift region 320a), therefore, a relatively low doping concentration which is selected to ensure a trench type power MOSFET breakdown (BV ) voltage performance requirements. 在该实施例中,半导体层320的掺杂浓度范围为IX IO14离子/cm3至IX IO17离子/cm3,例如选择为5.9X IO15离子/cm3。 In this embodiment, the doping concentration of the semiconductor layer 320 is a range IX IO14 ions / cm3 to IX IO17 ions / cm3, for example, selected to 5.9X IO15 ions / cm3. 由于其掺杂浓度较低,可以方便地(相对其后形成的第二漂移区340来说)通过外延工艺生长形成,但是,半导体层320具体生长方法不是限制性的,任何其他可以形成基本同样性能的半导体层的薄膜沉积方法都可以应用于本发明。 Because of its doping concentration is low, can be easily (opposite second drift region 340 is subsequently formed) is formed by an epitaxial growth process, however, the semiconductor layer 320 is not particularly limiting growth process, any other form substantially the same the method of depositing a thin film semiconductor layer properties can be applied to the present invention. 半导体层320的具体厚度范围为3微米至40微米,例如,6微米。 The specific thickness of the semiconductor layer 320 range from 3 to 40 microns, e.g., 6 microns. 在半导体层320生长后,在其上依次覆盖地生长氧化层391和氮化硅层392,氧化层391用作衬垫(PAD)氧化层,氮化硅层392用作沟槽刻蚀掩膜层。 After the semiconductor layer 320 grown thereon are sequentially grown to cover the oxide layer 391 and silicon nitride layer 392, oxide layer 391 is used as a pad oxide layer (the PAD), a silicon nitride layer 392 is used as a trench etch mask Floor. 需要理解的是,用作沟槽刻蚀掩膜层的具体材料种类并不限于本发明实施例的氮化娃层。 Is to be understood that the specific kind of material is used as a trench etching mask layer is not limited baby nitride layer embodiment of the present invention.

[0033] 进一步,步骤S130,对半导体层320构图刻蚀形成沟槽331。 [0033] Further, step S130, the trench 331 pairs forming patterned semiconductor layer 320 is etched.

[0034] 参阅图4,氧化层391和氮化硅层392上首先构图形成孔以暴露欲刻蚀的半导体层部分,该孔的形状欲形成的沟槽的形状决定,从而完成了沟槽331的构图。 [0034] Referring to Figure 4, the oxide layer 391 and silicon nitride layer 392 is first patterned to expose holes formed portion of the semiconductor layer to be etched, the shape of the groove determines the shape of the hole to be formed, thereby completing a trench 331 composition. 然后以氮化硅层392作掩膜层,向下刻蚀半导体层320形成沟槽331,余下的半导体层320将主要用于形成漂移层的第一漂移区320a。 Then a silicon nitride layer 392 as a mask layer, a semiconductor layer 320 is etched down groove 331 is formed, the remaining semiconductor layer 320 will be used to form a drift region of the first drift layer 320a. 沟槽331的具体深度不大于半导体层320的厚度,这样,防止刻蚀至半导体衬底310,通过控制刻蚀速率、时间等工艺条件,可以控制刻蚀形成的沟槽331的深度。 DETAILED depth of the groove 331 is not larger than the thickness of the semiconductor layer 320, so that, to prevent the semiconductor substrate 310 is etched, by controlling the etching rate, time and other conditions can be controlled etching depth of the groove 331 is formed.

[0035] 进一步,步骤S140,在沟槽331中外延生长高掺杂浓度的半导体层340。 [0035] Further, step S140, the trench 331 is epitaxially grown semiconductor layer 340 of high dopant concentration.

[0036] 参阅图5,通过另外一次或多次的外延生长工艺(区别于之前的外延生长半导体层320的工艺)来形成半导体层340,半导体层340用来形成沟槽型功率MOSFET的第二漂移区(340a),为降低第二漂移区的电阻以减小导通电阻,半导体层340的掺杂浓度高于半导体层320的掺杂浓度,在该实施例中,半导体层340的掺杂浓度范围为IX IO15离子/cm3至IX IO18离子/cm3,并且,其掺杂元素具体地为As (砷)、P (磷)或Sb (锑)。 [0036] Referring to Figure 5, through one or more further epitaxial growth process (process of epitaxially growing a semiconductor layer 320 is distinguished from previous) forming a semiconductor layer 340, a semiconductor layer 340 for forming a trench type power MOSFET of the second drift region (340a), to reduce the resistance of the second drift region to reduce on-resistance, the doping concentration of the semiconductor layer 340 is higher than the doping concentration of the semiconductor layer 320, in this embodiment, the doped semiconductor layer 340 ion concentration ranging IX IO15 / cm3 to IX IO18 ions / cm3, and that the doping element is particularly as (arsenic), P (phosphorus) or Sb (antimony). 另外,半导体层340的掺杂浓度在上述范围内很可能并不是以某一值均匀地分布,而是在一定范围值内变化地非均匀掺杂,例如,在X方向上,以沟槽331的中央轴线为中心,半导体层340的掺杂浓度呈正态分布(中央轴线位置附近掺杂浓度相对最高)。 In addition, the doping concentration of the semiconductor layer 340 is not likely to be uniformly distributed within the above range at a certain value, but varies non-uniformly doped to within a certain range value, for example, in the X-direction, to the trench 331 central axis as its center, the doping concentration of the semiconductor layer 340 of a normal distribution (a central axial position relative to dope the vicinity of the highest concentration).

[0037] 在外延生长半导体层340之后,可用化学机械平坦工艺(CMP)使晶圆表面平坦化并去除如图4中所示的氧化层391和氮化硅层392。 [0037] After the epitaxial growth of the semiconductor layer 340, using chemical mechanical planarization process (CMP) planarization of the wafer surface and removing the oxide layer as shown in FIG. 4 392 391 and silicon nitride layer.

[0038] 进一步,步骤S150,构图回刻蚀半导体层340以形成第二漂移区340a。 [0038] Further, step S150, the patterned semiconductor layer 340 is etched back to form a second drift region 340a.

[0039] 参阅图6,具体地,氧化硅层393用作该回刻蚀过程的刻蚀掩膜层,其厚度例如可以为1000至8000埃。 [0039] Referring to Figure 6, specifically, a silicon oxide layer 393 as the etching mask layer is etched back process, for example, a thickness of 1000-8000 Angstroms. 回刻蚀部分半导体层340后,剩余在沟槽331底部的部分半导体层340用作第二漂移区340a (也可以称为外延漂移区)。 After etching back the portion of the semiconductor layer 340, the remaining portion of the semiconductor layer at the bottom of the trench 331 as the second drift region 340 340a (epitaxial drift region may also be referred to). 回刻蚀的深度可以决定第二漂移区340a的厚度,在该实施例中,第二漂移区340a的厚度范围为3微米至20微米,例如,5微米,其厚度一般小于第一漂移区320a的厚度。 The depth of etch-back may determine the thickness of the second drift region 340a, in this embodiment, the thickness of the second drift region 340a is 3 to 20 microns, e.g., 5 microns, generally less than a thickness of the first drift region 320a thickness of.

[0040] 相对于现有技术的离子注入掺杂形成的第二漂移区,如背景技术中描述,其厚度条件必然受离子注入的深度限制,特别是对As、Ph、Sb等原子半径和质量都比较大的掺杂元素,其深度相对较小,对改善漂移层的导通电阻作用不明显。 [0040] with respect to the prior art ion implantation of the second doping region formed in the drift, as described in the background, which is bound by the conditions of the thickness of the ion implantation depth limit, especially atomic radius of As, Ph, Sb, etc., and the quality of larger than the doping element, the depth is relatively small, on-resistance effect on the improvement of the drift layer is not obvious. 采用以上工艺方法过程形成第二漂移区340a时,其厚度和掺杂浓度均不受离子注入工艺条件限制,容易形成高掺杂浓度、厚度较深的第二漂移区340a,因此,能非常有效地降低沟槽型功率MOSFET (30)的导通电阻。 With the above process of the second process for the drift zone 340a, the thickness and doping concentration are from ion implantation process conditions of the second drift region, easy to form high doping concentration, thickness 340a is formed deeper, therefore, can be very effective reducing trench power MOSFET (30) of the on-resistance.

[0041] 同时,在回刻蚀结束后,原来的沟槽331的底部被第二漂移区340a填充,第二漂移区340a上方部分的沟槽形成沟槽332,沟槽332内将用于形成沟槽型功率MOSFET (30)的栅沟槽结构。 [0041] Meanwhile, after the etching back, the bottom of the original trench 331 is filled with a second drift region 340a, the upper portion of the groove 340a of the second drift region 332 forming a trench, the trench 332 for forming trench power MOSFET (30) of the trench gate structure.

[0042] 进一步,步骤S160,去除掩膜氧化层393。 [0042] Further, step S160, the mask oxide layer 393 is removed. 参阅图7,掩膜氧化层393被刻蚀去除。 Referring to Figure 7, the mask oxide layer 393 is etched away.

[0043] 进一步,步骤S170,在第二漂移区340a上方的沟槽332内形成栅沟槽结构。 [0043] Further, step S170, the trench gate structure is formed within the trenches 332 340a above the second drift region.

[0044] 参阅图8,沟槽332内可以制备形成栅沟槽结构,栅沟槽结构包括栅介质层352和栅电极351,栅介质层352例如可以通过先湿氧氧化形成牺牲层、去除该牺牲层后再干氧氧化形成,栅电极351为高掺杂的多晶硅,电阻率低。 [0044] Refer to 8, the trench 332 may be prepared by forming a gate trench structure in FIG, trench gate structure includes a gate dielectric layer 352 and the gate electrode 351, gate dielectric layer 352 may be formed, for example, sacrificial oxide layer by wet oxidation to remove the the sacrificial layer is formed after the dry oxidation process, a polysilicon gate electrode 351, a highly doped low resistivity. 需要说明的是,栅沟槽结构的具体结构及其制备方法不受本发明实施例的限制。 It should be noted that the specific structure of the trench gate structure and preparation method of the present invention is not limited to the examples.

[0045] 同时,第一漂移区320a上方还形成了体层361、低电阻率的接触区362和源区370,体层361和接触区362的导电类型为P型,也即P型掺杂,其不同于漂移层的导电类型(N型);源区370的导电类型为N型,其掺杂浓度相对较高。 [0045] Meanwhile, the drift region 320a over the first layer 361 is also formed, low resistivity contact regions 362 and the source region 370, the conductive type layer 361 and contact region 362 is P-type, P-type doped i.e. , which is different from the conductivity type (N-type) drift layer; conductive type source region 370 are N-type, doping concentration is relatively high.

[0046] 进一步,步骤S180,继续形成源电极、漏电极,直至制备形成沟槽型功率MOSFET30。 [0046] Further, step S180, the continued forming a source electrode, a drain electrode, forming a trench type power until preparation MOSFET30. [0047] 参阅图9,继续形成介质层381、源(Source)电极382和半导体衬底310背面的漏电极383。 [0047] Referring to Figure 9, continues to form dielectric layer 381, the source (Source) electrodes 382 of the semiconductor substrate 310 and the back surface drain electrode 383.

[0048] 至此,如图9所示实施例的沟槽型功率MOSFET 30基本形成。 [0048] At this point, substantially as shown in Figure 9 is formed a trench type power MOSFET 30 according to an embodiment. 以上制备方法过程并不复杂,并且深沟槽的刻蚀、外延生长填充等工艺成熟,工艺上简单可靠。 The method of preparing the above process is not complicated, and deep trench etching, epitaxial growth such as filling mature technology, the process is simple and reliable.

[0049] 尽管以上实施例仅以沟槽型功率NM0SFET 30为例进行说明,但是本领域技术人员根据以上启示和教导,基于相似的方法步骤,可以制备形成沟槽型功率PM0SFET。 [0049] Although the above embodiment only a trench type power NM0SFET 30 as an example, those skilled in the art according to the teachings of the above teachings and, based on similar method step, can be prepared by forming a trench type power PM0SFET.

[0050] 参阅图9所示的沟槽型功率MOSFET 30,其栅沟槽结构下方的漂移层部分,也即第二漂移区340a,是通过单独的外延工艺生长形成,其可以相对形成高掺杂、低电阻率的区域,从而有效降低其导通电阻。 [0050] See trench type power MOSFET 30 shown in FIG. 9, the drift layer portion below the gate trench structure, i.e. the second drift region 340a, is formed by a single epitaxial growth process, which can be formed relatively highly doped heteroaryl, low resistivity region, thus effectively reducing the oN resistance. 通过对工作电压为68V的沟槽型功率NM0SFET仿真表明,该器件的单位面积导通电阻能降低13%以上(Vgs=IOV的情况下);并且,第二漂移区340a并不影响沟槽型功率NM0SFET的击穿电压和开启阈值电压等性能参数。 By a trench type power NM0SFET show simulation 68V operating voltage, on-resistance per unit area of ​​the device can be reduced more than 13% (Vgs = IOV of the case); and, a second drift region 340a does not affect the trench breakdown voltage and turn-on threshold voltage of the performance parameters such as power NM0SFET.

[0051] 以上例子主要说明了本发明的沟槽型功率MOSFET的制备方法及其所制备形成的沟槽型功率M0SFET。 [0051] The above examples illustrate the preparation of mainly a trench type power MOSFET of the present invention and prepared by trench type power M0SFET formed. 尽管只对其中一些本发明的实施方式进行了描述,但是本领域普通技术人员应当了解,本发明可以在不偏离其主旨与范围内以许多其他的形式实施。 Although only some embodiments of the present invention which have been described, those skilled in the art will appreciate, the present invention may be made without departing from the spirit and scope of the embodied in many other forms. 因此,所展示的例子与实施方式被视为示意性的而非限制性的,在不脱离如所附各权利要求所定义的本发明精神及范围的情况下,本发明可能涵盖各种的修改与替换。 Thus, with the illustrated example embodiment be considered as illustrative and not restrictive, without departing from the spirit and scope of the invention as defined in the annexed claims the present invention may cover various modifications and replacement.

Claims (13)

  1. 1.一种沟槽型功率MOSFET,至少包括栅沟槽和漂移层,其特征在于,所述漂移层包括所述栅沟槽结构正下方的第二漂移区以及所述第二漂移区之外的第一漂移区,所述第二漂移区通过单独的外延生长过程形成以使所述第二漂移区的掺杂浓度高于所述第一漂移区的掺杂浓度。 A trench power MOSFET, a trench comprising at least outside the gate and the drift layer, wherein the drift layer comprises a drift region of a second structure of the trench gate and just below the second drift region a first drift region, the drift region is formed so that the second doping concentration of the second drift region is higher than the first doping concentration of the drift region by a single epitaxial growth process.
  2. 2.如权利要求1所述的沟槽型功率MOSFET,其特征在于,所述第二漂移区的掺杂浓度的范围掺杂浓度范围为IX IO15离子/cm3至IX IO18离子/cm3。 2. The trench power MOSFET according to claim 1, wherein said second dopant concentration range of the drift region doping concentration ranging IX IO15 ions / cm3 to IX IO18 ions / cm3.
  3. 3.如权利要求1或2所述的沟槽型功率MOSFET,其特征在于,所述第二漂移区的厚度范围为3微米至20微米。 3. The trench power MOSFET of claim 1 or claim 2, wherein a thickness of the second drift region is 3 to 20 microns.
  4. 4.如权利要求1所述的沟槽型功率MOSFET,其特征在于,所述第二漂移区的导电类型与所述第一漂移区的导电类型相同。 4. The trench power MOSFET according to claim 1, wherein said same conductivity type second drift region of the first drift region.
  5. 5.—种沟槽型功率MOSFET的制备方法,其特征在于,包括以下步骤: 提供半导体衬底; 在所述衬底上生长形成第一漂移区; 对所述第一漂移区构图刻蚀形成第二沟槽; 在所述第二沟槽中外延生长半导体层以形成部分地填充所述第二沟槽底部的第二漂移区,并且,使所述第二漂移区的掺杂浓度高于所述第一漂移区的掺杂浓度;以及在所述第二漂移区上方、所述第二沟槽内形成栅沟槽结构。 5.- preparation methods trench power MOSFET, characterized by comprising the steps of: providing a semiconductor substrate; forming a first drift region grown on the substrate; forming a first patterning and etching the drift region a second trench; trench in said second epitaxial semiconductor layer is grown to form a second drift region of the bottom of the second trench is filled partially, and the doping concentration of the drift region is higher than a second a first doping concentration of the drift region; and above the second drift region, the second trench forming a gate trench structure.
  6. 6.如权利要求5所述的制备方法,其特征在于,形成所述第二漂移区的步骤,包括步骤: 在所述第二沟槽中外延生长填充所述第二沟槽的半导体层;以及对所述第二沟槽中的半导体层进行回刻蚀以形成所述第二漂移区。 6. The method as claimed in claim 5, wherein the step of forming the second drift region, comprising the steps of: epitaxially growing the second trench filling said second trench semiconductor layer; and etching back the second semiconductor layer in the trench to form the second drift region.
  7. 7.如权利要求5或6所述的制备方法,其特征在于,所述第二漂移区的掺杂浓度范围为IX IO15 离子/cm3 至IX IO18 离子/cm3。 5 or 7. The method as recited in claim 6, wherein the second doping concentration of said drift region of ions IX IO15 / cm3 to IX IO18 ions / cm3.
  8. 8.如权利要求7所述的制备方法,其特征在于,所述第二漂移区的掺杂浓度在平行于所述半导体衬底表面的方向上、基于所述第二沟槽的中央轴线呈正态分布。 8. The production method according to claim 7, wherein the second doping concentration of the drift region in a direction parallel to the surface of the semiconductor substrate, was based on a central axis of the second trench normal distribution.
  9. 9.如权利要求5或6所述的制备方法,其特征在于,所述第二漂移区的厚度范围为3微米至20微米。 9. The method as claimed in 5 or claim 6, wherein a thickness of the second drift region is 3 to 20 microns.
  10. 10.如权利要求5或6所述的制备方法,其特征在于,所述第二漂移区的导电类型与所述第一漂移区的导电类型相同。 10. The method as claimed in 5 or claim 6, wherein said same conductivity type second drift region of the first drift region.
  11. 11.如权利要求10所述的制备方法,其特征在于,所述第一漂移区的掺杂浓度范围为IX IO14 离子/cm3 至IX IO17 离子/cm3。 11. The method as recited in claim 10, wherein the first doping concentration of said drift region of ions IX IO14 / cm3 to IX IO17 ions / cm3.
  12. 12.如权利要求10所述的制备方法,其特征在于,所述第一漂移区的厚度范围为3微米至40微米。 12. The method as recited in claim 10, wherein a thickness of the first drift region is 3 to 40 micrometers.
  13. 13.如权利要求5或6所述的制备方法,其特征在于,所述第一漂移区通过在所述半导体衬底上外延生长形成。 13. The production method of claim 5 or claim 6, wherein said first drift region is formed by epitaxial growth on the semiconductor substrate.
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