CN103022125A - NLDMOS (N type Lateral Double Diffusion Metal-Oxide-Semiconductor) device in BCD (Bipolar, CMOS and DMOS) process and manufacturing method - Google Patents
NLDMOS (N type Lateral Double Diffusion Metal-Oxide-Semiconductor) device in BCD (Bipolar, CMOS and DMOS) process and manufacturing method Download PDFInfo
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- CN103022125A CN103022125A CN2011102835011A CN201110283501A CN103022125A CN 103022125 A CN103022125 A CN 103022125A CN 2011102835011 A CN2011102835011 A CN 2011102835011A CN 201110283501 A CN201110283501 A CN 201110283501A CN 103022125 A CN103022125 A CN 103022125A
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 13
- 239000004065 semiconductor Substances 0.000 title abstract description 5
- 238000009792 diffusion process Methods 0.000 title abstract description 3
- 238000003672 processing method Methods 0.000 title 1
- 238000000034 method Methods 0.000 claims abstract description 64
- 238000002347 injection Methods 0.000 claims abstract description 53
- 239000007924 injection Substances 0.000 claims abstract description 53
- 238000002513 implantation Methods 0.000 claims description 28
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 28
- 229920005591 polysilicon Polymers 0.000 claims description 28
- 238000005516 engineering process Methods 0.000 claims description 16
- 238000005530 etching Methods 0.000 claims description 15
- 238000005468 ion implantation Methods 0.000 claims description 13
- 239000002019 doping agent Substances 0.000 claims description 12
- 230000015572 biosynthetic process Effects 0.000 claims description 11
- 229910052796 boron Inorganic materials 0.000 claims description 8
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 6
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims description 6
- 239000007943 implant Substances 0.000 claims description 6
- 229910052698 phosphorus Inorganic materials 0.000 claims description 6
- 239000011574 phosphorus Substances 0.000 claims description 6
- 239000000126 substance Substances 0.000 claims description 6
- 238000001039 wet etching Methods 0.000 claims description 6
- 229910052785 arsenic Inorganic materials 0.000 claims description 3
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 claims description 3
- 238000000151 deposition Methods 0.000 claims description 3
- 229920002120 photoresistant polymer Polymers 0.000 claims description 3
- 229910044991 metal oxide Inorganic materials 0.000 description 3
- 150000004706 metal oxides Chemical class 0.000 description 3
- INQLNSVYIFCUML-QZTLEVGFSA-N [[(2r,3s,4r,5r)-5-(6-aminopurin-9-yl)-3,4-dihydroxyoxolan-2-yl]methoxy-hydroxyphosphoryl] [(2r,3s,4r,5r)-5-(4-carbamoyl-1,3-thiazol-2-yl)-3,4-dihydroxyoxolan-2-yl]methyl hydrogen phosphate Chemical compound NC(=O)C1=CSC([C@H]2[C@@H]([C@H](O)[C@@H](COP(O)(=O)OP(O)(=O)OC[C@@H]3[C@H]([C@@H](O)[C@@H](O3)N3C4=NC=NC(N)=C4N=C3)O)O2)O)=N1 INQLNSVYIFCUML-QZTLEVGFSA-N 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000004088 simulation Methods 0.000 description 2
- 230000000295 complement effect Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
- H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
- H01L29/0852—Source or drain regions of field-effect devices of field-effect transistors with insulated gate of DMOS transistors
- H01L29/0873—Drain regions
- H01L29/0878—Impurity concentration or distribution
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66681—Lateral DMOS transistors, i.e. LDMOS transistors
- H01L29/66689—Lateral DMOS transistors, i.e. LDMOS transistors with a step of forming an insulating sidewall spacer
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
- H01L29/42368—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity the thickness being non-uniform
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Abstract
The invention discloses an NLDMOS (N type Lateral Double Diffusion Metal-Oxide-Semiconductor) device in a BCD (Bipolar, CMOS and DMOS) process. The drain terminal of the NLDMOS device comprises an N well, a first N type injection region and a second N type injection region, wherein the N well is formed in an N type epitaxial layer and covered by a side part of a field oxide, the first N type injection region is formed in the N type epitaxial layer, the process condition of the first N type injection region is as same as that of the N type injection region of a Zener diode in the BCD process, the second N type injection region is formed in the first N type injection region, and the process condition of second N type injection region is as same as that of an ion injection region of a source electrode of the NLDMOS device. The invention further discloses a manufacturing method of the NLDMOS device in the BCD process. According to the invention, the on resistance of the device can be reduced without changing the on resistance of the device.
Description
Technical field
The present invention relates to semiconductor integrated circuit and make the field, particularly relate to the NLDMOS device in a kind of BCD technique, the invention still further relates to the manufacture method of the NLDMOS device in a kind of BCD technique.
Background technology
The technique of BCD technique for making bipolar transistor (Bipolar Junction Transistor, BJT), CMOS (Complementary Metal Oxide Semiconductor) (CMOS), diffused metal oxide emiconductor (DMOS) at same chip.Adopt BCD technique just to make in N-type lateral double diffusion metal oxide semiconductor (NLDMOS) the device process, in order to reduce the conducting resistance of NLDMOS, and wanting the indices such as puncture voltage all to reach requirement.Usually need adjusting process, and the each several part size of optimised devices.In order to reduce conducting resistance, usually can add a N trap at drain terminal.
As shown in Figure 1, be the structural representation of existing NLDMOS device, existing NLDMOS device comprises: N trap 102, be formed in the N-type epitaxial loayer 101, and partly covered by a side of field oxide 103.
P type back of the body grid 104, be formed in the described N-type epitaxial loayer 101, and and the opposite side of described field oxide 103 segment distance of being separated by; Described P type back of the body grid 104 are described NLDMOS device drift region to described N-type epitaxial loayer 101 and described N trap 102 between the described N trap 102.
P type back of the body gate contact zone 109 forms in the described P type back of the body grid 104 of described gate oxide 105 opposite sides, and described back of the body gate contact zone 109 contacts with described P type back of the body grid 104 and described P type back of the body grid 104 are drawn.
Existing NLDMOS device as shown in Figure 1 after having increased by a described N trap 102, can reduce the conducting resistance of NLDMOS.But, even this N trap 102 is arranged, in the situation that guarantees puncture voltage, sometimes can not make the conducting resistance of NLDMOS drop to the value that needs.
Summary of the invention
Technical problem to be solved by this invention provides the NLDMOS device in a kind of BCD technique, can reduce the conducting resistance of device under the constant condition of the puncture voltage that guarantees device; The present invention also provides the manufacture method of the NLDMOS device in a kind of BCD technique.
For solving the problems of the technologies described above, the invention provides the NLDMOS device in a kind of BCD technique, the drain terminal of NLDMOS device comprises: the N trap, be formed in the N-type epitaxial loayer, partly covered by a side of field oxide; The first N-type injection region is formed in the described N-type, and is identical with the process conditions of the N-type injection region of Zener diode in the BCD technique; The second N-type injection region is formed in described the first N-type injection region, and is identical with the process conditions of the ion implanted region of the source electrode of described NLDMOS device.
Further improve and be, also the comprising of described NLDMOS device:
P type back of the body grid, be formed in the described N-type epitaxial loayer, and and the opposite side of the described field oxide segment distance of being separated by; Described P type back of the body grid are described NLDMOS device drift region to the described N-type epitaxial loayer between the described N trap, described N trap and described the first N-type injection region.
Gate oxide, a side of described gate oxide be connected that field oxide contact connects, the opposite side of described gate oxide is covered on the described P type back of the body grid.
Polysilicon gate is formed on the described gate oxide and extends on the described field oxide.
Source electrode forms in the described P type back of the body grid of described gate oxide opposite side.
P type back of the body gate contact zone forms in the described P type back of the body grid of described gate oxide opposite side, and described back of the body gate contact zone contacts with described P type back of the body grid and described P type back of the body grid are drawn.
Further improve is that described P type back of the body grid inject the P type injection region that forms by two steps and form.
For solving the problems of the technologies described above, the invention provides the manufacture method of the NLDMOS device in a kind of BCD technique, the drain terminal that forms the NLDMOS device comprises the steps:
Form the N trap after field oxide forms in the N-type epitaxial loayer, described N trap is partly covered by a side of described field oxide.
Adopt the ion implantation technology of the N-type injection region of the Zener diode in the BCD technique in described N-type, to form the first N-type injection region.
Adopt the ion implantation technology of source electrode in the first N-type injection region, to form the second N-type injection region.
Further improving is that the manufacture method of the NLDMOS device in the described BCD technique comprises the steps:
The ion implantation technology of the N-type injection region of the Zener diode in step 6, the employing BCD technique forms the first N-type injection region in described N-type.
Step 7, as carrying out the N-type ion implantation technology, hard mask forms simultaneously described source electrode and described the second N-type injection region take described polysilicon gate and its side wall; Form P type back of the body gate contact zone.
Further improve and be, the implanted dopant of the Implantation of described N trap is that phosphorus or arsenic, Implantation Energy are 0keV～2000keV, and dosage is 10
11Cm
-2～10
15Cm
-2, one or many injects.
Further improving is that the implanted dopant of the Implantation of described the first N-type injection region is that phosphorus, Implantation Energy are that 0keV～1000keV, implantation dosage are 10
12Cm
-2～10
16Cm
-2
Further improve and be, two step of the employing ion implantation technology of described P type back of the body grid forms, and the implant angle of first step Implantation is that 30 °～60 °, implanted dopant are that boron, energy are that 100keV～300keV, dosage are 10
12Cm
-2～10
14Cm
-2The implant angle of second step Implantation is that 0 °, implanted dopant are that boron, energy are that 100keV～300keV, dosage are 10
12Cm
-2～10
14Cm
-2
The present invention is by adding the first identical N-type injection region of N-type injection region of the Zener diode in process conditions and the BCD technique at drain terminal, can reduce the conducting resistance of NLDMOS device under the constant condition of the puncture voltage that guarantees the NLDMOS device.The Implantation of while owing to the N-type injection region of Zener diode just need to adopt in BCD technique originally, so can't increase the cost of making the NLDMOS device.
Description of drawings
The present invention is further detailed explanation below in conjunction with the drawings and specific embodiments:
Fig. 1 is the structural representation of existing NLDMOS device;
Fig. 2 is the structural representation of embodiment of the invention NLDMOS device;
Fig. 3 A-Fig. 3 C is the structural representation of NLDMOS device in each step of embodiment of the invention method;
Fig. 4 A-Fig. 4 B is the existing NLDMOS device of TCAD simulation and the transfer characteristic curve comparison diagram of embodiment of the invention NLDMOS device.
Embodiment
As shown in Figure 2, be the structural representation of embodiment of the invention NLDMOS device.NLDMOS device in the embodiment of the invention BCD technique comprises:
The first N-type injection region 10 is formed in the described N-type, and is identical with the process conditions of the N-type injection region of Zener diode in the BCD technique.
The second N-type injection region 11 is i.e. drain electrode also, is formed in described the first N-type injection region 10, and is identical with the process conditions of the ion implanted region of the source electrode 8 of described NLDMOS device.N trap 3 described above, described the first N-type injection region 10 and described the second N-type injection region 11 are the drain terminal of NLDMOS device.
P type back of the body grid 4, be formed in the described N-type epitaxial loayer 1, and and the opposite side of described field oxide 2 segment distance of being separated by; Described P type back of the body grid 4 are described NLDMOS device drift region to described N-type epitaxial loayer 1, described N trap 3 and described the first N-type injection region 10 between the described N trap 3.
Polysilicon gate 6 is formed on the described gate oxide 5 and extends on the described field oxide 2.Be formed with side wall 7 in the side of described polysilicon gate 6.
Described source electrode 8 is a N+ district, forms in the described P type back of the body grid 4 of described gate oxide 5 opposite sides.
P type back of the body gate contact zone 9 forms in the described P type back of the body grid 4 of described gate oxide 5 opposite sides, and described back of the body gate contact zone 9 contacts with described P type back of the body grid 4 and described P type back of the body grid 4 are drawn.Described P type back of the body grid 4 inject the P type injection region that forms by two steps and form.
Shown in Fig. 3 A to Fig. 3 C, it is the structural representation of NLDMOS device in each step of embodiment of the invention method.The manufacture method of the NLDMOS device in the embodiment of the invention BCD technique comprises the steps:
Step 6, as shown in Figure 1 adopts the ion implantation technology of the N-type injection region of the Zener diode in the BCD technique to form the first N-type injection region 10 in described N-type.The implanted dopant of the Implantation of described the first N-type injection region 10 is that phosphorus, Implantation Energy are that 0keV～1000keV, implantation dosage are 10
12m
-2～10
16Cm
-2
Step 7, as shown in Figure 1 forms described source electrode 8 and described the second N-type injection region 11 take described polysilicon gate 6 and its side wall 7 simultaneously as hard mask carries out the N-type ion implantation technology; Form P type back of the body gate contact zone 9.
Shown in Fig. 4 A and Fig. 4 B, be the existing NLDMOS device of TCAD simulation and the transfer characteristic curve comparison diagram of embodiment of the invention NLDMOS device; Wherein the ordinate of Fig. 4 A is drain current I
D, abscissa is gate voltage V
G, the ordinate of Fig. 4 B is drain current I
DLogarithm, abscissa be gate voltage V
GDrain current I
DUnit be the ampere/micron, gate voltage V
GLogarithm for the volt.Among Fig. 4 A and Fig. 4 B, have the measure-alike of NLDMOS device and embodiment of the invention NLDMOS device now, difference is that embodiment of the invention NLDMOS device adds the zener injection, and wherein dotted line represents that transfer characteristic curve, the solid line of embodiment of the invention NLDMOS device are the transfer characteristic curves of existing NLDMOS device.Can see the drain current I of embodiment of the invention NLDMOS device from Fig. 4 A and Fig. 4 B
DBe greater than the drain current I of existing NLDMOS device
D, energy and dosage that greatly how much concrete the and concrete size of device and zener is injected are relevant.As can be seen from Figure 4A, at V
GIn the time of=5 volts, it is the difference of 1.1E-5 ampere/micron and 1E-5 ampere/micron.So the embodiment of the invention can improve NLDMOS device drain electric current I
DThereby, can reduce the conducting resistance of device.
More than by specific embodiment the present invention is had been described in detail, but these are not to be construed as limiting the invention.In the situation that does not break away from the principle of the invention, those skilled in the art also can make many distortion and improvement, and these also should be considered as protection scope of the present invention.
Claims (8)
1. the NLDMOS device in the BCD technique, it is characterized in that: the drain terminal of NLDMOS device comprises:
The N trap is formed in the N-type epitaxial loayer, is partly covered by a side of field oxide;
The first N-type injection region is formed in the described N-type, and is identical with the process conditions of the N-type injection region of Zener diode in the BCD technique;
The second N-type injection region is formed in described the first N-type injection region, and is identical with the process conditions of the ion implanted region of the source electrode of described NLDMOS device.
2. the NLDMOS device in the BCD technique as claimed in claim 1 is characterized in that: also the comprising of described NLDMOS device:
P type back of the body grid, be formed in the described N-type epitaxial loayer, and and the opposite side of the described field oxide segment distance of being separated by; Described P type back of the body grid are described NLDMOS device drift region to the described N-type epitaxial loayer between the described N trap, described N trap and described the first N-type injection region;
Gate oxide, a side of described gate oxide be connected that field oxide contact connects, the opposite side of described gate oxide is covered on the described P type back of the body grid;
Polysilicon gate is formed on the described gate oxide and extends on the described field oxide;
Source electrode forms in the described P type back of the body grid of described gate oxide opposite side;
P type back of the body gate contact zone forms in the described P type back of the body grid of described gate oxide opposite side, and described back of the body gate contact zone contacts with described P type back of the body grid and described P type back of the body grid are drawn.
3. the NLDMOS device in the BCD technique as claimed in claim 1 is characterized in that: described P type back of the body grid inject the P type injection region that forms by two steps and form.
4. the manufacture method of the NLDMOS device in the BCD technique, it is characterized in that: the drain terminal that forms the NLDMOS device comprises the steps:
Form the N trap after field oxide forms in the N-type epitaxial loayer, described N trap is partly covered by a side of described field oxide;
Adopt the ion implantation technology of the N-type injection region of the Zener diode in the BCD technique in described N-type, to form the first N-type injection region;
Adopt the ion implantation technology of source electrode in the first N-type injection region, to form the second N-type injection region.
5. the manufacture method of the NLDMOS device in the BCD technique as claimed in claim 4 is characterized in that, comprises the steps:
Step 1, form described field oxide at described N-type epitaxial loayer;
Step 2, in the described N-type epitaxial loayer of described field oxide one side, carry out Implantation and form described N trap;
Step 3, formation gate oxide, and depositing polysilicon; Adopt chemical wet etching technique that described polysilicon is carried out etching first time, it is regional and the described etching polysilicon on the formation zone of described source electrode fallen that described first time, etching defined the formation of described source electrode;
Step 4, take described first time etching photoresist in described N-type epitaxial loayer, form P type back of the body grid as mask carries out Implantation, the opposite side of described P type back of the body grid and the described field oxide segment distance of being separated by;
Step 5, employing chemical wet etching technique are carried out etching formation second time polysilicon gate to described polysilicon, and described polysilicon gate extends on the described field oxide; Side at described polysilicon gate forms side wall;
The ion implantation technology of the N-type injection region of the Zener diode in step 6, the employing BCD technique forms the first N-type injection region in described N-type;
Step 7, as carrying out the N-type ion implantation technology, hard mask forms simultaneously described source electrode and described the second N-type injection region take described polysilicon gate and its side wall; Form P type back of the body gate contact zone.
6. such as the manufacture method of the NLDMOS device in claim 4 or the 5 described BCD techniques, it is characterized in that: the implanted dopant of the Implantation of described N trap is that phosphorus or arsenic, Implantation Energy are 0keV～2000keV, and dosage is 10
11Cm
-2～10
15Cm
-2, one or many injects.
7. such as the manufacture method of the NLDMOS device in claim 4 or the 5 described BCD techniques, it is characterized in that: the implanted dopant of the Implantation of described the first N-type injection region is that phosphorus, Implantation Energy are that 0keV～1000keV, implantation dosage are 10
12Cm
-2～10
16Cm
-2
8. the manufacture method of the NLDMOS device in the BCD technique as claimed in claim 5, it is characterized in that: two step of the employing ion implantation technology of described P type back of the body grid forms, and the implant angle of first step Implantation is that 30 °～60 °, implanted dopant are that boron, energy are that 100keV～300keV, dosage are 10
12Cm
-2～10
14Cm
-2The implant angle of second step Implantation is that 0 °, implanted dopant are that boron, energy are that 100keV～300keV, dosage are 10
12Cm
-2～10
14Cm
-2
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103337498A (en) * | 2013-05-31 | 2013-10-02 | 深圳市联德合微电子有限公司 | BCD semiconductor device and manufacturing method thereof |
| CN104377244A (en) * | 2013-08-15 | 2015-02-25 | 无锡华润上华半导体有限公司 | Device structure lowering LDMOS on resistance |
| CN104659090A (en) * | 2013-11-18 | 2015-05-27 | 上海华虹宏力半导体制造有限公司 | LDMOS (Lateral Double-diffused Metal Oxide Semiconductor Field Effect Transistor) device and manufacturing method |
| CN107546253A (en) * | 2016-06-27 | 2018-01-05 | 北大方正集团有限公司 | The preparation method and metal-oxide semiconductor (MOS) of metal-oxide semiconductor (MOS) |
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| US20070080398A1 (en) * | 2005-10-11 | 2007-04-12 | Chih-Hua Lee | Fabricating method of a high voltage metal oxide semiconductor device |
| TW200847428A (en) * | 2007-05-16 | 2008-12-01 | Macronix Int Co Ltd | Low on-resistance lateral-double diffused transistor and fabrication method of the same |
| CN101540339A (en) * | 2009-05-05 | 2009-09-23 | 浙江大学 | High-side NLDMOS structure |
| CN102087978A (en) * | 2009-12-08 | 2011-06-08 | 上海华虹Nec电子有限公司 | Injection method for DMOS back gate channel region in self-alignment BCD process |
| KR20110078879A (en) * | 2009-12-31 | 2011-07-07 | 주식회사 동부하이텍 | Method manufactruing of lateral double diffused metal oxide semiconductor |
| CN102130164A (en) * | 2010-01-18 | 2011-07-20 | 上海华虹Nec电子有限公司 | Buried layer of LDMOS (laterally diffused metal-oxide semiconductor) |
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2011
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| CN103337498A (en) * | 2013-05-31 | 2013-10-02 | 深圳市联德合微电子有限公司 | BCD semiconductor device and manufacturing method thereof |
| CN103337498B (en) * | 2013-05-31 | 2017-02-08 | 深圳市联德合微电子有限公司 | BCD semiconductor device and manufacturing method thereof |
| CN104377244A (en) * | 2013-08-15 | 2015-02-25 | 无锡华润上华半导体有限公司 | Device structure lowering LDMOS on resistance |
| US9716169B2 (en) | 2013-08-15 | 2017-07-25 | Csmc Technologies Fabi Co., Ltd. | Lateral double diffused metal oxide semiconductor field-effect transistor |
| CN104659090A (en) * | 2013-11-18 | 2015-05-27 | 上海华虹宏力半导体制造有限公司 | LDMOS (Lateral Double-diffused Metal Oxide Semiconductor Field Effect Transistor) device and manufacturing method |
| CN104659090B (en) * | 2013-11-18 | 2017-08-08 | 上海华虹宏力半导体制造有限公司 | LDMOS device and manufacture method |
| CN107546253A (en) * | 2016-06-27 | 2018-01-05 | 北大方正集团有限公司 | The preparation method and metal-oxide semiconductor (MOS) of metal-oxide semiconductor (MOS) |
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| CN103022125B (en) | 2015-10-14 |
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