CN107546253A - The preparation method and metal-oxide semiconductor (MOS) of metal-oxide semiconductor (MOS) - Google Patents

The preparation method and metal-oxide semiconductor (MOS) of metal-oxide semiconductor (MOS) Download PDF

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CN107546253A
CN107546253A CN201610482371.7A CN201610482371A CN107546253A CN 107546253 A CN107546253 A CN 107546253A CN 201610482371 A CN201610482371 A CN 201610482371A CN 107546253 A CN107546253 A CN 107546253A
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jing areas
region
jing
nxing
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杜蕾
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Peking University Founder Group Co Ltd
Shenzhen Founder Microelectronics Co Ltd
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Peking University Founder Group Co Ltd
Shenzhen Founder Microelectronics Co Ltd
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Abstract

The invention provides a kind of preparation method of metal-oxide semiconductor (MOS) and metal-oxide semiconductor (MOS), the preparation method of metal-oxide semiconductor (MOS) includes：NXing Jing areas and PXing Jing areas are sequentially formed in P type substrate；N-type ion implanting is carried out in the central area in NXing Jing areas, to form N-type drift region；Field oxide is formed in the borderline region of N-type drift region, to expose the central area of N-type drift region；Grid, the edge of the side edges cover field oxide of grid are formed in the handover region in NXing Jing areas and PXing Jing areas；The first N+ type doped regions are formed in the designated area in the PXing Jing areas of another lateral edges of grid, and the 2nd N+ type doped regions are formed in the central area of N-type drift region；P+ type doped region is formed in side PXing Jing areas of the first N+ types doped region away from grid, to form block contact.By technical solution of the present invention, while ensureing that PN junction resistance to pressure is high, conducting resistance and power consumption are reduced, improves device reliability.

Description

The preparation method and metal-oxide semiconductor (MOS) of metal-oxide semiconductor (MOS)
Technical field
The present invention relates to technical field of semiconductors, in particular to a kind of preparation method of metal-oxide semiconductor (MOS) With a kind of metal-oxide semiconductor (MOS).
Background technology
In the related art, conventional high-tension MOS (Metal Oxide Semiconductor, metal-oxide semiconductor (MOS)) The voltage endurance and on state characteristic of device are the characteristics of conflict, for example, when the ion concentration of the PN junction of MOS device is low, tool Standby higher voltage endurance, but conducting resistance is high, is unsuitable for the use demand of low-power consumption, still, if raising PN junction from Sub- concentration, then reduce voltage endurance, has a strong impact on the reliability of MOS device.
Therefore, how to design a kind of preparation scheme of new metal-oxide semiconductor (MOS), with simultaneously optimize voltage endurance and Conducting resistance turns into technical problem urgently to be resolved hurrily.
The content of the invention
The present invention is based at least one above-mentioned technical problem, it is proposed that a kind of system of new metal-oxide semiconductor (MOS) Standby scheme, by carrying out N-type ion implanting at the center in NXing Jing areas, to form N-type drift region, N-type drift region will not cover whole GeNXing Jing areas, while ensureing that PN junction resistance to pressure is high, conducting resistance and power consumption are reduced, improves device reliability.
In view of this, the present invention proposes a kind of preparation method of metal-oxide semiconductor (MOS), including：In P type substrate Sequentially form NXing Jing areas and PXing Jing areas；N-type ion implanting is carried out in the central area in NXing Jing areas, to form N-type drift region； Field oxide is formed in the borderline region of N-type drift region, to expose the central area of N-type drift region；In NXing Jing areas and p-type The handover region in hydrazine area forms grid, the edge of the side edges cover field oxide of grid；Close to another lateral edges of grid PXing Jing areas designated area in formed the first N+ type doped regions, and in the central area of N-type drift region formed the 2nd N+ Type doped region；P+ type doped region is formed in side PXing Jing areas of the first N+ types doped region away from grid, is connect with forming block Touch.
In the technical scheme, by carrying out N-type ion implanting at the center in NXing Jing areas, to form N-type drift region, N-type Drift region will not cover whole NXing Jing areas, while ensureing that PN junction resistance to pressure is high, reduce conducting resistance and power consumption, lifted Device reliability.
Wherein, the ion concentration in NXing Jing areas is relatively low corresponding to drain electrode, and main current path is MOS during MOS device conducting The surface texture layer of device, therefore, N-type drift region is formed in NXing Jing areas corresponding to drain electrode, and then reduce the table in NXing Jing areas The conducting resistance of layer, because N-type drift region will not cover whole NXing Jing areas, therefore, N-type drift region has no effect on NXing Jing areas Voltage endurance, while optimize the voltage endurance and conducting resistance of high-pressure MOS component, above-mentioned high-voltage metal oxide semiconductor (HVMOS) preparation technology is compatible with CMOS (Complementary Metal-Oxide-Semiconductor Transistor, complementary metal oxide semiconductor) standard technology, suitable for the batch production of small size semiconductor devices.
In the above-mentioned technical solutions, it is preferable that NXing Jing areas and PXing Jing areas are sequentially formed in P type substrate, is specifically included Following steps：First time N-type ion implanting is carried out in the designated area of P type substrate, to form NXing Jing areas；Above NXing Jing areas Form the first photoresist coating；First time p-type ion implanting is carried out to P type substrate using the first photoresist coating as mask, with shape Into PXing Jing areas.
In any of the above-described technical scheme, it is preferable that N-type ion implanting is carried out in the central area in NXing Jing areas, with shape Into N-type drift region, following steps are specifically included：Region beyond the central area in NXing Jing areas forms the second photoresist coating； Second of N-type ion implanting is carried out to the central area in NXing Jing areas using the second photoresist coating as mask, to form N-type drift Area.
In the technical scheme, by carrying out N-type ion implanting at the center in NXing Jing areas, to form N-type drift region, N-type Drift region will not cover whole NXing Jing areas, while ensureing that PN junction resistance to pressure is high, reduce conducting resistance and power consumption, lifted Device reliability.
In any of the above-described technical scheme, it is preferable that field oxide is formed in the borderline region of N-type drift region, with sudden and violent Expose the central area of N-type drift region, specifically include following steps：Using location oxidation of silicon process in the frontier district of N-type drift region Domain forms field oxide, to expose the central area of N-type drift region.
In the technical scheme, field oxide is formed by using borderline region of the location oxidation of silicon process in N-type drift region, To expose the central area of N-type drift region, form densification electrical isolation structure, namely realize MOS device grid, Isolation between source electrode and drain electrode.
In any of the above-described technical scheme, it is preferable that form grid, grid in the handover region in NXing Jing areas and PXing Jing areas The edge of the side edges cover field oxide of pole, specifically includes following steps：After field oxide is formed, using chemical gaseous phase Depositing technics forms polysilicon layer in P type substrate；Photoetching treatment is carried out to polysilicon layer, retains NXing Jing areas and PXing Jing areas The 3rd photoresist coating above handover region；Polysilicon layer is performed etching using the 3rd photoresist coating as mask, to be formed Grid.
In the technical scheme, by being performed etching using the 3rd photoresist coating as mask to polysilicon layer, to form grid Pole, it ensure that the structural reliability and high pressure resistant property of MOS device.
In any of the above-described technical scheme, it is preferable that the designated area close to the PXing Jing areas of another lateral edges of grid It is middle formation the first N+ type doped regions, and in the central area of N-type drift region formed the 2nd N+ type doped regions, specifically include with Lower step：Photoetching treatment is carried out to the P type substrate for forming grid, drifted about with forming the designated area for exposing PXing Jing areas and N-type 4th photoresist coating of the central area in area；The is carried out to the designated area in PXing Jing areas using the 4th photoresist coating as mask N-type ion implanting three times, to form the first N+ types doped region and the 2nd N+ type doped regions.
In the technical scheme, by forming the first N+ types doped region and the 2nd N+ type doped regions, wherein, the first N+ types are mixed Source contact of the miscellaneous area as MOS device, drain contact of the 2nd N+ types doped region as MOS device.
In any of the above-described technical scheme, it is preferable that the dosage of third time ion implanting is more than first time ion implanting Dosage, and the dosage of third time ion implanting is more than the dosage of second ion implanting.
In any of the above-described technical scheme, it is preferable that the energy of third time ion implanting is more than first time ion implanting Energy, and the energy of third time ion implanting is more than the energy of second ion implanting.
In any of the above-described technical scheme, it is preferable that in side PXing Jing area of the first N+ types doped region away from grid Middle formation P+ type doped region, to form block contact, specifically includes following steps：To forming the first N+ types doped region and the 2nd N+ types The P type substrate of doped region carries out photoetching treatment, to form covering grid, field oxide, the first N+ types doped region and the 2nd N+ types 5th photoresist coating of doped region；Second of p-type ion implanting is carried out to PXing Jing areas using the 5th photoresist coating as mask, To form P+ type doped region.
In the technical scheme, by forming P+ type doped region, the block contact of MOS device is formd, is further ensured The high pressure resistant property of MOS device.
According to a second aspect of the present invention, it is also proposed that a kind of metal-oxide semiconductor (MOS), using any one technology as described above The preparation method of metal-oxide semiconductor (MOS) described in scheme is prepared, and therefore, the field-effect transistor has and above-mentioned skill The preparation method identical technique effect of metal-oxide semiconductor (MOS) any one of art scheme, will not be repeated here.
By above technical scheme, by carrying out N-type ion implanting at the center in NXing Jing areas, to form N-type drift region, N Type drift region will not cover whole NXing Jing areas, while ensureing that PN junction resistance to pressure is high, reduce conducting resistance and power consumption, carry Device reliability is risen.
Brief description of the drawings
Fig. 1 shows the schematic flow diagram of the preparation method of metal-oxide semiconductor (MOS) according to an embodiment of the invention；
Fig. 2 to Figure 10 shows that the section of the preparation method of metal-oxide semiconductor (MOS) according to an embodiment of the invention shows It is intended to.
Numbering and structure title corresponding relation in Figure of description is as shown in the table：
Table 1
Numbering Structure title Numbering Structure title
102 P type substrate 104 NXing Jing areas
106 PXing Jing areas 108 N-type drift region
110 Field oxide 112 Grid
114 First N+ type doped regions 116 2nd N+ type doped regions
118 P+ type doped region PR Photo Resist, photoresist
Embodiment
It is below in conjunction with the accompanying drawings and specific real in order to be more clearly understood that the above objects, features and advantages of the present invention Mode is applied the present invention is further described in detail.It should be noted that in the case where not conflicting, the implementation of the application Feature in example and embodiment can be mutually combined.
Many details are elaborated in the following description to facilitate a thorough understanding of the present invention, still, the present invention may be used also Implemented in a manner of being different from third party described here using third party, therefore, protection scope of the present invention is not by following The limitation of disclosed specific embodiment.
Carried out with reference to preparation schemes of the Fig. 1 to Figure 10 to metal-oxide semiconductor (MOS) according to an embodiment of the invention Illustrate.
As shown in Figures 1 to 10, the preparation method of metal-oxide semiconductor (MOS) according to an embodiment of the invention, including： Step 202, NXing Jing areas 104 and PXing Jing areas 106 are sequentially formed in P type substrate 102；Step 204, in NXing Jing areas 104 Heart district domain carries out N-type ion implanting, to form N-type drift region 108；Step 206, formed in the borderline region of N-type drift region 108 Field oxide 110, to expose the central area of N-type drift region 108；Step 208, in NXing Jing areas 104 and PXing Jing areas 106 Handover region forms grid 112, the edge of the side edges cover field oxide 110 of grid 112；Step 210, close to grid The first N+ types doped region 114 is formed in the designated area in the PXing Jing areas 106 of 112 another lateral edges, and in N-type drift region The 2nd N+ types doped region 116 is formed in 108 central area；Step 212, in the domain of the first N+ types doped region 114 away from grid 112 Side PXing Jing areas 106 in form P+ type doped region 118, to form block contact.
In the technical scheme, by carrying out N-type ion implanting at the center in NXing Jing areas 104, to form N-type drift region 108, N-type drift region 108 will not cover whole NXing Jing areas 104, while ensureing that PN junction resistance to pressure is high, reduce electric conduction Resistance and power consumption, improve device reliability.
Wherein, the ion concentration in NXing Jing areas 104 is relatively low corresponding to drain electrode, and main current path is during MOS device conducting The surface texture layer of MOS device, therefore, N-type drift region 108 is formed in NXing Jing areas 104 corresponding to drain electrode, and then reduce N-type The conducting resistance on the top layer in hydrazine area 104, because N-type drift region 108 will not cover whole NXing Jing areas 104, therefore, N-type drift region 108 have no effect on the voltage endurance in NXing Jing areas 104, while optimize the voltage endurance and conducting resistance of high-pressure MOS component, on The preparation technology for stating high-voltage metal oxide semiconductor (HVMOS) is compatible with CMOS (Complementary Metal-Oxide- Semiconductor Transistor, complementary metal oxide semiconductor) standard technology, suitable for small size semiconductor devices Batch production.
In the above-mentioned technical solutions, it is preferable that NXing Jing areas 104 and PXing Jing areas 106 are sequentially formed in P type substrate 102, Specifically include following steps：First time N-type ion implanting is carried out in the designated area of P type substrate 102, to form NXing Jing areas 104；The first photoresist coating PR is formed above NXing Jing areas 104；It is mask to P type substrate 102 using the first photoresist coating PR First time p-type ion implanting is carried out, to form PXing Jing areas 106.
In any of the above-described technical scheme, it is preferable that N-type ion implanting is carried out in the central area in NXing Jing areas 104, To form N-type drift region 108, following steps are specifically included：Region beyond the central area in NXing Jing areas 104 forms second Photoresist coating PR；Second of N-type ion is carried out to the central area in NXing Jing areas 104 using the second photoresist coating PR as mask Injection, to form N-type drift region 108.
In the technical scheme, by carrying out N-type ion implanting at the center in NXing Jing areas 104, to form N-type drift region 108, N-type drift region 108 will not cover whole NXing Jing areas 104, while ensureing that PN junction resistance to pressure is high, reduce electric conduction Resistance and power consumption, improve device reliability.
In any of the above-described technical scheme, it is preferable that form field oxide in the borderline region of N-type drift region 108 110, to expose the central area of N-type drift region 108, specifically include following steps：Drifted about using location oxidation of silicon process in N-type The borderline region in area 108 forms field oxide 110, to expose the central area of N-type drift region 108.
In the technical scheme, field oxidation is formed in the borderline region of N-type drift region 108 by using location oxidation of silicon process Layer 110, to expose the central area of N-type drift region 108, the electrical isolation structure of densification is formd, namely realize MOS devices Isolation between the grid 112 of part, source electrode and drain electrode.
In any of the above-described technical scheme, it is preferable that the handover region in NXing Jing areas 104 and PXing Jing areas 106 is formed Grid 112, the edge of the side edges cover field oxide 110 of grid 112, specifically includes following steps：Forming field oxidation After layer 110, polysilicon layer is formed in P type substrate 102 using chemical vapor deposition method；Polysilicon layer is carried out at photoetching Reason, retain the 3rd photoresist coating PR above the handover region in NXing Jing areas 104 and PXing Jing areas 106；Applied with the 3rd photoresist Layer PR is that mask performs etching to polysilicon layer, to form grid 112.
In the technical scheme, by being performed etching using the 3rd photoresist coating PR as mask to polysilicon layer, to be formed Grid 112, it ensure that the structural reliability and high pressure resistant property of MOS device.
In any of the above-described technical scheme, it is preferable that the finger close to the PXing Jing areas 106 of another lateral edges of grid 112 Determine to form the first N+ types doped region 114 in region, and the doping of the 2nd N+ types is formed in the central area of N-type drift region 108 Area 116, specifically includes following steps：Photoetching treatment is carried out to the P type substrate 102 for forming grid 112, exposes p-type to be formed The designated area in hydrazine area 106 and the 4th photoresist coating PR of the central area of N-type drift region 108；With the 4th photoresist coating PR is that mask carries out third time N-type ion implanting to the designated area in PXing Jing areas 106, to form the He of the first N+ types doped region 114 2nd N+ types doped region 116.
In the technical scheme, by forming the first N+ types doped region 114 and the 2nd N+ types doped region 116, wherein, first N+ types 114 source contact as MOS device of doped region, the 2nd N+ types 116 drain contact as MOS device of doped region.
In any of the above-described technical scheme, it is preferable that the dosage of third time ion implanting is more than first time ion implanting Dosage, and the dosage of third time ion implanting is more than the dosage of second ion implanting.
In any of the above-described technical scheme, it is preferable that the energy of third time ion implanting is more than first time ion implanting Energy, and the energy of third time ion implanting is more than the energy of second ion implanting.
In any of the above-described technical scheme, it is preferable that in side P of the domain of the first N+ types doped region 114 away from grid 112 P+ type doped region 118 is formed in Xing Jing areas 106, to form block contact, specifically includes following steps：To forming the doping of the first N+ types The P type substrate 102 of the N+ types doped region 116 of area 114 and the 2nd carries out photoetching treatment, to form covering grid 112, field oxide 110th, the 5th photoresist coating PR of the first N+ types doped region 114 and the 2nd N+ types doped region 116；With the 5th photoresist coating PR Second of p-type ion implanting is carried out to PXing Jing areas 106 for mask, to form P+ type doped region 118.
In the technical scheme, by forming P+ type doped region 118, the block contact of MOS device is formd, is further protected The high pressure resistant property of MOS device is demonstrate,proved.
Technical scheme is described in detail above in association with accompanying drawing, it is contemplated that how to optimize simultaneously in correlation technique resistance to The technical problem of characteristic and conducting resistance is pressed, the present invention proposes a kind of preparation scheme of new metal-oxide semiconductor (MOS), leads to The center in GuoNXing Jing areas carries out N-type ion implanting, and to form N-type drift region, N-type drift region will not cover whole N-type hydrazine Area, while ensureing that PN junction resistance to pressure is high, conducting resistance and power consumption are reduced, improves device reliability.
The preferred embodiments of the present invention are the foregoing is only, are not intended to limit the invention, for the skill of this area For art personnel, the present invention can have various modifications and variations.Within the spirit and principles of the invention, that is made any repaiies Change, equivalent substitution, improvement etc., should be included in the scope of the protection.

Claims (10)

  1. A kind of 1. preparation method of metal-oxide semiconductor (MOS), it is characterised in that including：
    NXing Jing areas and PXing Jing areas are sequentially formed in P type substrate；
    N-type ion implanting is carried out in the central area in the NXing Jing areas, to form N-type drift region；
    Field oxide is formed in the borderline region of the N-type drift region, to expose the central area of the N-type drift region；
    Grid, field described in the side edges cover of the grid are formed in the handover region in the NXing Jing areas and the PXing Jing areas The edge of oxide layer；
    The first N+ type doped regions are formed in the designated area in the PXing Jing areas of another lateral edges of the grid, and in institute State the 2nd N+ type doped regions of formation in the central area of N-type drift region；
    P+ type doped region is formed in side PXing Jing areas of the first N+ types doped region away from the grid, to form block Contact.
  2. 2. the preparation method of metal-oxide semiconductor (MOS) according to claim 1, it is characterised in that in P type substrate according to Secondary formation NXing Jing areas and PXing Jing areas, specifically include following steps：
    First time N-type ion implanting is carried out in the designated area of the P type substrate, to form the NXing Jing areas；
    The first photoresist coating is formed above the NXing Jing areas；
    First time p-type ion implanting is carried out to the P type substrate using first photoresist coating as mask, to form the P Xing Jing areas.
  3. 3. the preparation method of metal-oxide semiconductor (MOS) according to claim 1, it is characterised in that in the NXing Jing areas Central area carry out N-type ion implanting, to form N-type drift region, specifically include following steps：
    Region beyond the central area in the NXing Jing areas forms the second photoresist coating；
    Second of N-type ion implanting is carried out to the central area in the NXing Jing areas using second photoresist coating as mask, with Form the N-type drift region.
  4. 4. the preparation method of metal-oxide semiconductor (MOS) according to claim 1, it is characterised in that drifted about in the N-type The borderline region in area forms field oxide, to expose the central area of the N-type drift region, specifically includes following steps：
    Field oxide is formed using borderline region of the location oxidation of silicon process in the N-type drift region, drifted about with exposing the N-type The central area in area.
  5. 5. the preparation method of metal-oxide semiconductor (MOS) according to claim 1, it is characterised in that in the NXing Jing areas With the handover region formation grid in the PXing Jing areas, the edge of field oxide described in the side edges cover of the grid, specifically Comprise the following steps：
    After the field oxide is formed, polysilicon layer is formed in the P type substrate using chemical vapor deposition method；
    Photoetching treatment is carried out to the polysilicon layer, retains the above the handover region in the NXing Jing areas and the PXing Jing areas Three photoresist coatings；
    The polysilicon layer is performed etching as mask using the 3rd photoresist coating, to form the grid.
  6. 6. the preparation method of metal-oxide semiconductor (MOS) according to any one of claim 1 to 5, it is characterised in that lean on The first N+ type doped regions are formed in the designated area in the PXing Jing areas of another lateral edges of the nearly grid, and are floated in the N-type Move and the 2nd N+ type doped regions are formed in the central area in area, specifically include following steps：
    Photoetching treatment is carried out to the P type substrate for forming the grid, to form the designated area and the institute that expose the PXing Jing areas State the 4th photoresist coating of the central area of N-type drift region；
    Third time N-type ion implanting is carried out to the designated area in the PXing Jing areas using the 4th photoresist coating as mask, with Form the first N+ types doped region and the 2nd N+ type doped regions.
  7. 7. the preparation method of metal-oxide semiconductor (MOS) according to claim 6, it is characterised in that the third time ion The dosage of injection is more than the dosage of the first time ion implanting, and the dosage of the third time ion implanting is more than described second The dosage of secondary ion injection.
  8. 8. the preparation method of metal-oxide semiconductor (MOS) according to claim 6, it is characterised in that the third time ion The energy of injection is more than the energy of the first time ion implanting, and the energy of the third time ion implanting is more than described second The energy of secondary ion injection.
  9. 9. the preparation method of the metal-oxide semiconductor (MOS) according to claim 7 or 8, it is characterised in that in the first N In the side PXing Jing areas of+type doped region away from the grid formed P+ type doped region, with formed block contact, specifically include with Lower step：
    Photoetching treatment is carried out to the P type substrate for forming the first N+ types doped region and the 2nd N+ type doped regions, to be formed Cover the 5th photoresist of the grid, the field oxide, the first N+ types doped region and the 2nd N+ type doped regions Coating；
    Second of p-type ion implanting is carried out to the PXing Jing areas using the 5th photoresist coating as mask, to form the P+ Type doped region.
  10. 10. a kind of metal-oxide semiconductor (MOS), it is characterised in that use metal oxygen as claimed in any one of claims 1-9 wherein The preparation method of compound semiconductor is prepared.
CN201610482371.7A 2016-06-27 2016-06-27 The preparation method and metal-oxide semiconductor (MOS) of metal-oxide semiconductor (MOS) Pending CN107546253A (en)

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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103022125A (en) * 2011-09-22 2013-04-03 上海华虹Nec电子有限公司 NLDMOS (N type Lateral Double Diffusion Metal-Oxide-Semiconductor) device in BCD (Bipolar, CMOS and DMOS) process and manufacturing method
US8482031B2 (en) * 2009-09-09 2013-07-09 Cambridge Semiconductor Limited Lateral insulated gate bipolar transistors (LIGBTS)
CN104900646A (en) * 2015-06-05 2015-09-09 杭州士兰微电子股份有限公司 Compound semiconductor device and manufacturing method thereof

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8482031B2 (en) * 2009-09-09 2013-07-09 Cambridge Semiconductor Limited Lateral insulated gate bipolar transistors (LIGBTS)
CN103022125A (en) * 2011-09-22 2013-04-03 上海华虹Nec电子有限公司 NLDMOS (N type Lateral Double Diffusion Metal-Oxide-Semiconductor) device in BCD (Bipolar, CMOS and DMOS) process and manufacturing method
CN104900646A (en) * 2015-06-05 2015-09-09 杭州士兰微电子股份有限公司 Compound semiconductor device and manufacturing method thereof

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