CN107665924A - A kind of mesolow groove type MOS device and preparation method thereof - Google Patents
A kind of mesolow groove type MOS device and preparation method thereof Download PDFInfo
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- 239000004065 semiconductor Substances 0.000 claims abstract description 12
- 230000001413 cellular effect Effects 0.000 claims description 59
- 210000000746 body region Anatomy 0.000 claims description 55
- 238000000034 method Methods 0.000 claims description 29
- 239000000758 substrate Substances 0.000 claims description 14
- 239000004020 conductor Substances 0.000 claims description 12
- 238000005516 engineering process Methods 0.000 claims description 11
- 238000002347 injection Methods 0.000 claims description 7
- 239000007924 injection Substances 0.000 claims description 7
- 238000005530 etching Methods 0.000 claims description 5
- 238000005468 ion implantation Methods 0.000 claims description 4
- 238000007254 oxidation reaction Methods 0.000 claims description 4
- 238000000137 annealing Methods 0.000 claims description 3
- 230000003647 oxidation Effects 0.000 claims description 3
- 230000026267 regulation of growth Effects 0.000 claims description 3
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- 239000002184 metal Substances 0.000 abstract description 3
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- 150000002500 ions Chemical class 0.000 description 6
- 238000001312 dry etching Methods 0.000 description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 4
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 239000007769 metal material Substances 0.000 description 3
- 229920005591 polysilicon Polymers 0.000 description 3
- 238000005240 physical vapour deposition Methods 0.000 description 2
- 239000003361 porogen Substances 0.000 description 2
- WHXSMMKQMYFTQS-UHFFFAOYSA-N Lithium Chemical compound [Li] WHXSMMKQMYFTQS-UHFFFAOYSA-N 0.000 description 1
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- 230000015572 biosynthetic process Effects 0.000 description 1
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- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 229910052744 lithium Inorganic materials 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7827—Vertical transistors
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- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
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- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823475—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type interconnection or wiring or contact manufacturing related aspects
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Abstract
The present invention relates to technical field of manufacturing semiconductors; a kind of more particularly to mesolow groove type MOS device and preparation method thereof; by using terminal knot of the groove structure as device, so saving workspace in traditional handicraft and protection ring mask plate this two pieces of mask blanks；And form the source region of device using contact hole mask plate, so save the source region mask plate in traditional handicraft, therefore trench mask plate is only needed, three mask blanks of contact hole mask plate and metal mask plate can prepare mesolow groove type MOS device, due to the reduction of the reticle number of plies, reduce the processing step of element manufacturing, so as to greatly reduce the production cost of mesolow groove type MOS device, and then improve the competitiveness of product.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors, more particularly to a kind of mesolow trench MOSFET device and its system
Preparation Method.
Background technology
Mesolow groove type MOS (MOSFET) device (Trench MOS) is due to high reliability, low on-resistance and big work(
The disposal ability of rate high current has important application in network service, computer and consumer field and industrial control field class；Example
Such as have extensively in lithium battery protection module, light-emitting diode display, LCD monitor, laptop and cellular phone power supplies management field
Using so the research to this device is very deep at present, and the design of this device and manufacturing process are very
It is ripe.
At present, in traditional Low-voltage trench type field-effect transistor manufacturing process, 6 layers of mask plate are normally applied to realize
The manufacture of device, respectively workspace, protection ring, groove, source region, the mask plate of contact hole and metal, this need it is higher into
This.With the increasingly raising of semiconductor devices integrated level, the manufacturing cost for reducing single chip is very important.
Chinese patent (publication number：CN101866923A a kind of three-layer light cover groove N-type MOS device and manufacturer) are disclosed
Method, after groove and conductive polycrystalline silicon complete, utilize the different openings chi between gate trench and gate contact trench
It is very little, by depositing the dielectric layer with good step covering power, there is gate trench notch and gate contact trench notch
Different-shape, then by dry etching processing procedure, then aid in lithographic process, it is possible to achieve retain medium in the region of needs
Layer.The dielectric layer remained can substitute photoresist mask, mask and p-type trap ion as the injection of N+ source ions
The mask of injection, it can also be used to self aligned source contact openings and self aligned gate contact hole.Therefore three-layer light cover is only needed
Can produces groove MOSFET device.So as to simple in manufacturing process, while cost is low, it is possible to achieve higher unit cell
Density, i.e. better performance.
Although above-mentioned give with three-layer light cover (i.e. mask blank) to realize the manufacture method of groove type MOS device,
But this manufacture method will be directed to the device that gate trench width is less than gate contact trench width, not have versatility.
Therefore, it is groove-shaped how to find the mesolow that a kind of general utilization mask blank as few as possible can be prepared
The method of MOS device turns into the direction that those skilled in the art are directed to research.
The content of the invention
For above-mentioned problem, the invention discloses a kind of mesolow groove type MOS device, including：
First conduction type heavy doping substrate, the first conduction type heavy doping substrate top are divided into cellular region and terminal
Area；
First conduction type lightly doped epitaxial layer, it is arranged at the first conduction type heavy doping substrate；
Second conductivity type body region doped layer, it is arranged on the first conduction type lightly doped epitaxial layer；
Groove structure, including the cellular region groove structure being arranged in the cellular region and be arranged in the termination environment
Termination environment groove structure, the cellular region groove structure and the termination environment groove structure run through the second conduction type body
Area's doped layer is arranged in the first conduction type lightly doped epitaxial layer；
Dielectric layer, it is arranged on second conductivity type body region doped layer and the groove structure；
Second conductivity type body region contact zone, it is arranged in the doped layer of second conductivity type body region；
First conduction type source region, it is arranged in the doped layer of second conductivity type body region, and is led positioned at described second
On electric type body region contact zone；
Contact hole, including cellular region contact hole and termination environment contact hole, the cellular region contact hole run through the dielectric layer
It is arranged in the contact zone of second conductivity type body region, the termination environment contact hole includes being arranged at institute through the dielectric layer
State the first contact hole in the groove structure of termination environment and the dielectric layer through the termination environment is arranged at second conduction
The second contact hole in type body region contact zone；
Electrode, the simultaneously upper surface of dielectric layer described in covering part is arranged in the contact hole.
Above-mentioned mesolow groove type MOS device, wherein, first conduction type is N-type, second conduction type
It is p-type for p-type or first conduction type, second conduction type is N-type.
Above-mentioned mesolow groove type MOS device, wherein, the groove structure includes：
Groove, through second conductivity type body region, doped layer is arranged at the first conduction type lightly doped epitaxial layer
In；
Gate oxide, it is arranged at bottom and its sidewall surfaces of the groove；
Conductive layer, it is arranged in the groove.
Above-mentioned mesolow groove type MOS device, wherein, the width of the groove is 0.2-1um.
Above-mentioned mesolow groove type MOS device, wherein, the thickness of the gate oxide is 200-600 angstroms.
Above-mentioned mesolow groove type MOS device, wherein, the thickness of second conductivity type body region doped layer is 0.5-
1um。
Above-mentioned mesolow groove type MOS device, wherein, the thickness of the dielectric layer is 0.2-1um.
The invention discloses a kind of preparation method of mesolow groove type MOS device, comprise the following steps：
Step S1, there is provided the first mask blank, the second mask blank, the 3rd mask blank and one have cellular region
With the semiconductor structure of termination environment, the semiconductor structure includes the first conduction type heavy doping substrate and led positioned at described first
First conduction type lightly doped epitaxial layer of electric type heavy doping substrate；
Step S2, the second conductivity type body region doped layer is formed on the first conduction type lightly doped epitaxial layer；
Step S3, trench etch process is carried out using first mask blank, is located at being formed in the cellular region
Cellular region groove and the termination environment groove positioned at the termination environment, and the cellular region groove and the termination environment groove pass through
Second conductivity type body region doped layer is worn to be arranged in the first conduction type lightly doped epitaxial layer；
Step S4, conductive layer is respectively formed in the cellular region groove and the termination environment groove；
Step S5, dielectric layer is formed on the conductive layer and second conductivity type body region doped layer；
Step S6, etch the dielectric layer using second mask blank and form contact hole, and be pointed to described connect
Second conductivity type body region doped layer of contact hole bottom carries out ion implantation technology, to form the first conduction type source region；
Step S7, and after the first conduction type source region described in etched portions, to positioned at the second of the contact hole bottom
Ion is injected in conductivity type body region doped layer and the conductive layer, to form the second conductivity type body region contact zone；
Step S8, after the positive and negative of the semiconductor structure is respectively formed conductive material, utilize the 3rd mask plate pair
The conductive material performs etching technique to form the electrode of the MOS device.
The preparation method of above-mentioned mesolow groove type MOS device, wherein, first conduction type is N-type, described
Two conduction types are p-type or first conduction type is p-type, and second conduction type is N-type.
The preparation method of above-mentioned mesolow groove type MOS device, wherein, the step S2 includes：
Step S21, the oxide layer of growth regulation one on the first conduction type lightly doped epitaxial layer；
Step S22, ion implanting and annealing process are carried out to first oxide layer to form second conduction type
Body area doped layer.
The preparation method of above-mentioned mesolow groove type MOS device, wherein, the step S3 includes：
Step S31, the second oxide layer is formed on the doped layer of second conductivity type body region；
Step S32, trench etch process is carried out using first mask blank, and described second is sequentially passed through to be formed
Oxide layer and PXing Ti areas doped layer are arranged at the cellular region groove of the first conduction type lightly doped epitaxial layer and described
Termination environment groove.
The preparation method of above-mentioned mesolow groove type MOS device, wherein, the step S4 includes：
Step S41, sacrificial oxide layer is formed in the cellular region groove and the bottom of the termination environment groove and its side wall；
Step S42, remove the sacrificial oxide layer and second oxide layer；
Step S43, gate oxide is formed with by the bottom and its side wall of the cellular region groove and the termination environment groove
Surface is covered, and doped layer exposed upper surface in second conductivity type body region is covered；
Step S44, conductive material is filled in the groove to form the conductive layer.
The preparation method of above-mentioned mesolow groove type MOS device, wherein, the step S7 includes：
Step S71, the first conduction type source region in the cellular region positioned at the contact hole bottom is etched with shape
Into cellular region contact hole, and the conductive layer etched in the termination environment positioned at the contact hole bottom is connect with forming first terminal area
Contact hole, while etch whole to form second positioned at the first conduction type source region of the contact hole bottom in the termination environment
Petiolarea contact hole.
Step S72, hole is carried out to second conductivity type body region doped region by the cellular region contact hole and injects work
Skill, and hole is carried out to the conductive layer and second conductivity type body region doped layer by the termination environment contact hole and injects work
Skill, to form the contact of the second conductivity type body region in the bottom periphery of the cellular region contact hole and the termination environment contact hole
Area.
The preparation method of above-mentioned mesolow groove type MOS device, wherein, the thickness of the gate oxide is 200-600
Angstrom.
The preparation method of above-mentioned mesolow groove type MOS device, wherein, the cellular region groove and the termination environment ditch
The width of groove is 0.2-1um.
The preparation method of above-mentioned mesolow groove type MOS device, wherein, second conductivity type body region doped layer
Thickness is 0.5-1um.
The preparation method of above-mentioned mesolow groove type MOS device, wherein, the thickness of the dielectric layer is 0.2-1um.
Foregoing invention has the following advantages that or beneficial effect：
The invention discloses a kind of mesolow groove type MOS device and preparation method thereof, by using groove structure conduct
The terminal knot of device, so saving workspace in traditional handicraft and protection ring mask plate this two pieces of mask blanks；And apply
Contact hole mask plate (i.e. the second mask blank) forms the source region of device, so save the source region mask in traditional handicraft
Plate, therefore trench mask plate (i.e. the first mask blank) is only needed, contact hole mask plate (i.e. the second mask blank) and gold
Category mask plate (i.e. the 3rd mask blank) three mask blanks can prepare mesolow groove type MOS device, due to photoetching
The reduction of plate number, reduce the processing step of element manufacturing, so as to greatly reduce the production of mesolow groove type MOS device
Cost, and then improve the competitiveness of product.
Brief description of the drawings
By reading the detailed description made with reference to the following drawings to non-limiting example, the present invention and its feature, outside
Shape and advantage will become more apparent.The identical mark instruction identical part in whole accompanying drawings.Not can according to than
Example draws accompanying drawing, it is preferred that emphasis is shows the purport of the present invention.
Fig. 1 is the structural representation of mesolow groove type MOS device in the embodiment of the present invention；
Fig. 2 is the method flow diagram that mesolow groove type MOS device is prepared in the embodiment of the present invention；
Fig. 3~16 are the method flow structural representations that mesolow groove type MOS device is prepared in the embodiment of the present invention.
Embodiment
The present invention is further illustrated with specific embodiment below in conjunction with the accompanying drawings, but not as the limit of the present invention
It is fixed.
Embodiment one
As shown in figure 1, the present embodiment is related to a kind of mesolow groove type MOS device, specifically, the mesolow is groove-shaped
MOS device is divided into the first conduction type heavy doping substrate 100 of cellular region and termination environment including top, is arranged at the first conductive-type
The first conduction type lightly doped epitaxial layer 101 on type heavy doping substrate 100, it is arranged at the first conduction type extension is lightly doped
The second conductivity type body region doped layer 102 including the groove of cellular region groove structure and termination environment groove structure on layer 101
Structure, and cellular region groove structure and termination environment groove structure are arranged at through the second conductivity type body region doped layer 102
In one conduction type lightly doped epitaxial layer 101, Jie for being arranged on the second conductivity type body region doped layer 102 and groove structure
Matter layer 105, the second conductivity type body region contact zone 106 being arranged in the second conductivity type body region doped layer 102, it is arranged at
In two conductivity type body region doped layers 102, and the first conduction type source on the second conductivity type body region contact zone 106
Area 107 including the contact hole of cellular region contact hole 1081 and termination environment contact hole, and cellular region contact hole 1081 runs through dielectric layer
105 are arranged in the second conductivity type body region contact zone 106, and termination environment contact hole includes being arranged at terminal through dielectric layer 105
The first contact hole 10821 in area's groove structure and the dielectric layer 105 through termination environment are arranged at the second conductivity type body region and connect
Touch the second contact hole 10822 in area 106 and be arranged at the electrode of in the contact hole and upper surface of covering part dielectric layer 105
109 (grid and source electrodes).
In a preferred embodiment of the invention, above-mentioned first conduction type is N-type, and the second conduction type is p-type
Or first conduction type be p-type, the second conduction type is N-type.
In a preferred embodiment of the invention, it is above-mentioned including cellular region groove structure and termination environment groove structure
Groove structure includes being arranged in the first conduction type lightly doped epitaxial layer 101 through the second conductivity type body region doped layer 102
Groove, be arranged at groove bottom and its sidewall surfaces gate oxide 103 and the conductive layer 104 that is arranged in groove,
In embodiments of the invention, the conductive layer 104 is that the conductive layer 104 can also be other conductive materials, not in polysilicon
It is limited to polysilicon.
On this basis, further, the width of above-mentioned groove be 0.2~1um (such as 0.2um, 0.5um, 0.6um or
1um etc.), in general, the depth of the groove positioned at cellular region is greater than positioned at the depth of the groove of termination environment.
On this basis, further, the thickness of above-mentioned gate oxide 103 be 200~600 angstroms (such as 200 angstroms, 300
Angstrom, 400 angstroms or 600 angstroms etc.).
In a preferred embodiment of the invention, the thickness of above-mentioned second conductivity type body region doped layer 102 for-
0.5-1um (0.5um, 0.7um, 0.8um, 1um etc.).
In a preferred embodiment of the invention, the thickness of above-mentioned dielectric layer 105 be 0.2~1um (such as 0.2um,
0.6um, 0.8um and 1um etc.).
In a preferred embodiment of the invention, above-mentioned electrode 109 includes grid and source electrode, and the electrode 109
Maximum gauge is preferably 0.8~2um (such as 0.8um, 1um, 1.4um or 2um etc.).
Embodiment two
As shown in Fig. 2 the present embodiment is related to a kind of preparation method of mesolow groove type MOS device, below with mesolow N
The method of the present invention is described in detail exemplified by the preparation method of type groove type MOS device；Specifically, this method includes
Step S1, there is provided the first mask blank (i.e. trench mask plate), the second mask blank (i.e. contact hole mask
Plate), the 3rd mask blank (i.e. metal mask plate) and a semiconductor structure 200 with cellular region and termination environment, this is partly led
N-type of the body structure 200 including N-type heavy doping substrate 2001 (N+) and on the first conduction type heavy doping substrate 2001 is light
Doped epitaxial layer 2002 (N-), structure as shown in Figure 3.
Step S2, PXing Ti areas doped layer 201, structure as shown in Figure 4 are formed on N-type lightly doped epitaxial layer 2002.
In a preferred embodiment of the invention, above-mentioned steps S2 is specifically included：
Step S21, the oxide layer of growth regulation one on N-type lightly doped epitaxial layer 2002, the thickness of first oxide layer is about
200 angstroms (180~220 angstroms).
Step S22, ion implanting and appropriate high-temperature annealing process are carried out to the first oxide layer to form the doping of PXing Ti areas
Layer 201, structure as shown in Figure 4.
In a preferred embodiment of the invention, the thickness of aforementioned p-type body area doped layer 201 is -0.5-1um
(0.5um, 0.7um, 0.8um, 1um etc.).
Step S3, trench etch process is carried out using the first mask blank, to form the cellular region being located in cellular region
Groove 2031 and the termination environment groove 2032 positioned at termination environment, and cellular region groove 2031 and termination environment groove 2032 run through P
Xing Ti areas doped layer 201 is arranged in N-type lightly doped epitaxial layer 2002, the structure as shown in Fig. 5~6.
In a preferred embodiment of the invention, above-mentioned steps S3 includes：
Step S31, formed by chemical vapour deposition technique on PXing Ti areas doped layer 201 thickness be about 200~
Second oxide layer 202 of 10000 angstroms (such as 2000 angstroms, 6000 angstroms, 8000 angstroms or 10000 angstroms etc.), structure as shown in Figure 5.
Step S32, trench etch process is carried out using the first mask blank, and the second oxide layer is sequentially passed through to be formed
202 and PXing Ti areas doped layer 201 is arranged at the cellular region groove 2031 and termination environment groove of N-type lightly doped epitaxial layer 2002
2032；Groove is defined using the first mask blank first, the width of groove is about 0.2-1um, passes through dry method afterwards
Etching forms the cellular region groove 2031 and termination environment groove 2032 of device, it is preferred that above-mentioned cellular region groove 2031 and terminal
The width of area's groove 2032 is 0.2~1um (such as 0.2um, 0.5um, 0.6um or 1um etc.), and the depth of termination environment groove 2032
Degree is greater than the depth positioned at cellular region groove 2031；Structure as shown in Figure 6.
Step S4, conductive layer 206 is respectively formed in cellular region groove 2031 and termination environment groove 2032, such as the institute of Fig. 7~10
The structure shown.
In a preferred embodiment of the invention, above-mentioned steps S4 includes：
Step S41, sacrificial oxide layer is formed in cellular region groove 2031 and the bottom of termination environment groove 2032 and its side wall
204, and the thickness of the sacrificial oxide layer 204 is 500~1250 angstroms (such as 500 angstroms, 600 angstroms, 900 angstroms or 1250 angstroms etc.), such as
Structure shown in Fig. 7.
Step S42, the oxide layer 202 of sacrificial oxide layer 204 and second is then removed using wet-etching technology, such as Fig. 8 institutes
The structure shown.
Step S43, the mode of high-temperature oxydation is used to grow gate oxide 205 with by cellular region groove 2031 and termination environment ditch
The bottom of groove 2032 and its sidewall surfaces are covered, and doped layer 201 exposed upper surface in PXing Ti areas is covered,
Structure as shown in Figure 9.
In a preferred embodiment of the invention, the thickness of above-mentioned gate oxide 205 be 200~600 angstroms (such as
200 angstroms, 300 angstroms, 400 angstroms or 600 angstroms etc.).
Step S44, to the upper surface of the above-mentioned steps S43 semiconductor structures formed by way of chemical vapor deposition
Conductive material is deposited, the thickness of the conductive material is 0.5-2 μm (such as 0.5 μm, 0.6 μm, 0.8 μm or 2 μm etc.), general to select
Polysilicon is as conductive material；Remove unnecessary conductive material using dry etching afterwards, and the dry etching is parked in gate oxidation
The upper surface of layer 205 is to form filling conductive layer 206 in the trench, structure as shown in Figure 10.
Step S5, by way of chemical vapor deposition in above-mentioned conductive layer 206 and aforementioned p-type body area doped layer 201 it
Upper formation dielectric layer 207, structure as shown in figure 11.
In a preferred embodiment of the invention, the thickness of above-mentioned dielectric layer 207 be 0.2~1um (such as 0.2um,
0.6um, 0.8um and 1um etc.).
Step S6, contact hole 208 is formed using the second mask blank etch media layer 207, and be pointed to contact hole 208
The PXing Ti areas doped layer 201 of bottom carries out ion implantation technology, to form N-type source region 209, the structure as shown in Figure 12~13.
In a preferred embodiment of the invention, above-mentioned steps S6 is specifically included：
The contact hole of device is defined first with the second mask blank, dielectric layer is etched away by dry etching afterwards
207 form contact hole 208, structure as shown in figure 12, and next PXing Ti areas doped layer 201 for being pointed to contact hole bottom is carried out
Ion implantation technology, to form N-type source region 209, structure as shown in fig. 13 that.
Step S7, and after etched portions N-type source region 209, to the He of PXing Ti areas doped layer 201 positioned at contact hole bottom
Ion is injected in conductive layer 206, to form PXing Ti areas contact zone；Structure as shown in Figure 14~15.
In a preferred embodiment of the invention, above-mentioned steps S7 is specifically included：
Step S71, the N-type source region 209 in cellular region positioned at contact hole bottom is etched to form cellular region contact hole 2101,
And the conductive layer 206 in termination environment positioned at contact hole bottom is etched to form first terminal area contact hole 21021, while etch end
N-type source region 209 in petiolarea positioned at contact hole bottom is to form second terminal area contact hole 21022, it is preferred that above-mentioned etching is adopted
With dry etch process, structure as shown in figure 14.
Step S72, carrying out hole injection technology to PXing Ti areas doped region by cellular region contact hole 2101, (ionic porogen injects
Technique), and it is right by termination environment contact hole (including first terminal area contact hole 21021 and second terminal area contact hole 21022)
Conductive layer 206 and PXing Ti areas doped layer 201 carry out hole injection technology (ionic porogen injection technology), with cellular region contact hole
2101 and termination environment contact hole (including first terminal area contact hole 21021 and second terminal area contact hole 21022) bottom week
Enclose to form PXing Ti areas contact zone 211 (Ohmic contact in Ji Ti areas), structure as shown in figure 15.
Step S8, it is respectively formed metal material in the positive and negative of semiconductor structure using the method for physical vapour deposition (PVD) and (also may be used
Think other conductive materials, however it is not limited to metal material) after, using the 3rd mask plate metal material is performed etching technique with
Form the electrode 212 (grid and source electrode) of MOS device, structure as shown in figure 16.
It is seen that the present embodiment is implemented for the method corresponding with the embodiment of above-mentioned mesolow groove type MOS device
Example, the present embodiment can work in coordination implementation with the embodiment of above-mentioned mesolow groove type MOS device.Above-mentioned mesolow is groove-shaped
The relevant technical details mentioned in the embodiment of MOS device are still effective in the present embodiment, in order to reduce repetition, here no longer
Repeat.Correspondingly, the relevant technical details mentioned in the present embodiment are also applicable in the reality of above-mentioned mesolow groove type MOS device
Apply in example.
It should be appreciated by those skilled in the art that those skilled in the art combine prior art and above-described embodiment can be with
Change case is realized, will not be described here.Such change case has no effect on the substantive content of the present invention, will not be described here.
Presently preferred embodiments of the present invention is described above.It is to be appreciated that the invention is not limited in above-mentioned
Particular implementation, wherein the equipment and structure be not described in detail to the greatest extent are construed as giving reality with the common mode in this area
Apply；Any those skilled in the art, without departing from the scope of the technical proposal of the invention, all using the disclosure above
Methods and technical content.
Claims (17)
- A kind of 1. mesolow groove type MOS device, it is characterised in that including：First conduction type heavy doping substrate, the first conduction type heavy doping substrate top are divided into cellular region and termination environment；First conduction type lightly doped epitaxial layer, it is arranged at the first conduction type heavy doping substrate；Second conductivity type body region doped layer, it is arranged on the first conduction type lightly doped epitaxial layer；Groove structure, including the cellular region groove structure being arranged in the cellular region and the terminal being arranged in the termination environment Area's groove structure, the cellular region groove structure and the termination environment groove structure are mixed through second conductivity type body region Diamicton is arranged in the first conduction type lightly doped epitaxial layer；Dielectric layer, it is arranged on second conductivity type body region doped layer and the groove structure；Second conductivity type body region contact zone, it is arranged in the doped layer of second conductivity type body region；First conduction type source region, it is arranged in the doped layer of second conductivity type body region, and is located at second conductive-type On Xing Ti areas contact zone；Contact hole, including cellular region contact hole and termination environment contact hole, the cellular region contact hole are set through the dielectric layer In the contact zone of second conductivity type body region, the termination environment contact hole includes being arranged at the end through the dielectric layer The first contact hole in petiolarea groove structure and the dielectric layer through the termination environment are arranged at second conduction type The second contact hole in body area contact zone；Electrode, the simultaneously upper surface of dielectric layer described in covering part is arranged in the contact hole.
- 2. mesolow groove type MOS device as claimed in claim 1, it is characterised in that first conduction type is N-type, Second conduction type is p-type or first conduction type is p-type, and second conduction type is N-type.
- 3. mesolow groove type MOS device as claimed in claim 1, it is characterised in that the groove structure includes：Groove, through second conductivity type body region, doped layer is arranged in the first conduction type lightly doped epitaxial layer；Gate oxide, it is arranged at bottom and its sidewall surfaces of the groove；Conductive layer, it is arranged in the groove.
- 4. mesolow groove type MOS device as claimed in claim 3, it is characterised in that the width of the groove is 0.2- 1um。
- 5. mesolow groove type MOS device as claimed in claim 3, it is characterised in that the thickness of the gate oxide is 200-600 angstroms.
- 6. mesolow groove type MOS device as claimed in claim 1, it is characterised in that mix second conductivity type body region The thickness of diamicton is 0.5-1um.
- 7. mesolow groove type MOS device as claimed in claim 1, it is characterised in that the thickness of the dielectric layer is 0.2- 1um。
- 8. a kind of preparation method of mesolow groove type MOS device, it is characterised in that comprise the following steps：Step S1, there is provided the first mask blank, the second mask blank, the 3rd mask blank and one have cellular region and end The semiconductor structure of petiolarea, the semiconductor structure include the first conduction type heavy doping substrate and positioned at first conductive-types First conduction type lightly doped epitaxial layer of type heavy doping substrate；Step S2, the second conductivity type body region doped layer is formed on the first conduction type lightly doped epitaxial layer；Step S3, trench etch process is carried out using first mask blank, to form the member being located in the cellular region Born of the same parents area groove and the termination environment groove positioned at the termination environment, and the cellular region groove and the termination environment groove run through institute The second conductivity type body region doped layer is stated to be arranged in the first conduction type lightly doped epitaxial layer；Step S4, conductive layer is respectively formed in the cellular region groove and the termination environment groove；Step S5, dielectric layer is formed on the conductive layer and second conductivity type body region doped layer；Step S6, etch the dielectric layer using second mask blank and form contact hole, and be pointed to the contact hole Second conductivity type body region doped layer of bottom carries out ion implantation technology, to form the first conduction type source region；Step S7, and after the first conduction type source region described in etched portions, to the second conduction positioned at the contact hole bottom Ion is injected in type body region doped layer and the conductive layer, to form the second conductivity type body region contact zone；Step S8, after the positive and negative of the semiconductor structure is respectively formed conductive material, utilize the 3rd mask blank pair The conductive material performs etching technique to form the electrode of the MOS device.
- 9. the preparation method of mesolow groove type MOS device as claimed in claim 8, it is characterised in that described first is conductive Type is N-type, and second conduction type is p-type or first conduction type is p-type, and second conduction type is N-type.
- 10. the preparation method of mesolow groove type MOS device as claimed in claim 8, it is characterised in that the step S2 bags Include：Step S21, the oxide layer of growth regulation one on the first conduction type lightly doped epitaxial layer；Step S22, ion implanting and annealing process are carried out to first oxide layer to form second conductivity type body region Doped layer.
- 11. the preparation method of mesolow groove type MOS device as claimed in claim 8, it is characterised in that the step S3 bags Include：Step S31, the second oxide layer is formed on the doped layer of second conductivity type body region；Step S32, trench etch process is carried out using first mask blank, second oxidation is sequentially passed through to be formed Ceng HePXing Ti areas doped layer is arranged at the cellular region groove of the first conduction type lightly doped epitaxial layer and the terminal Area's groove.
- 12. the preparation method of mesolow groove type MOS device as claimed in claim 11, it is characterised in that the step S4 Including：Step S41, sacrificial oxide layer is formed in the cellular region groove and the bottom of the termination environment groove and its side wall；Step S42, remove the sacrificial oxide layer and second oxide layer；Step S43, gate oxide is formed with by the bottom and its sidewall surfaces of the cellular region groove and the termination environment groove Covered, and doped layer exposed upper surface in second conductivity type body region is covered；Step S44, conductive material is filled in the groove to form the conductive layer.
- 13. the preparation method of mesolow groove type MOS device as claimed in claim 12, it is characterised in that the step S7 Including：Step S71, the first conduction type source region in the cellular region positioned at the contact hole bottom is etched to form member Born of the same parents area contact hole, and etch in the termination environment and contacted positioned at the conductive layer of the contact hole bottom with forming first terminal area Hole, while the first conduction type source region in the termination environment positioned at the contact hole bottom is etched to form second terminal Area's contact hole.Step S72, hole injection technology is carried out to second conductivity type body region doped region by the cellular region contact hole, and Hole injection technology is carried out to the conductive layer and second conductivity type body region doped layer by the termination environment contact hole, with The second conductivity type body region contact zone is formed in the bottom periphery of the cellular region contact hole and the termination environment contact hole.
- 14. the preparation method of mesolow groove type MOS device as claimed in claim 12, it is characterised in that the gate oxidation The thickness of layer is 200-600 angstroms.
- 15. the preparation method of mesolow groove type MOS device as claimed in claim 8, it is characterised in that the cellular region ditch The width of groove and the termination environment groove is 0.2-1um.
- 16. the preparation method of mesolow groove type MOS device as claimed in claim 8, it is characterised in that described second is conductive The thickness of type body region doped layer is 0.5-1um.
- 17. the preparation method of mesolow groove type MOS device as claimed in claim 8, it is characterised in that the dielectric layer Thickness is 0.2-1um.
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