TWI476924B - Double diffused metal oxide semiconductor device - Google Patents
Double diffused metal oxide semiconductor device Download PDFInfo
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- TWI476924B TWI476924B TW101116810A TW101116810A TWI476924B TW I476924 B TWI476924 B TW I476924B TW 101116810 A TW101116810 A TW 101116810A TW 101116810 A TW101116810 A TW 101116810A TW I476924 B TWI476924 B TW I476924B
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- 229910044991 metal oxide Inorganic materials 0.000 title claims description 4
- 150000004706 metal oxides Chemical class 0.000 title claims description 4
- 239000004065 semiconductor Substances 0.000 title claims description 4
- 210000000746 body region Anatomy 0.000 claims description 37
- 239000000758 substrate Substances 0.000 claims description 24
- 239000012535 impurity Substances 0.000 claims description 21
- 230000003647 oxidation Effects 0.000 claims description 10
- 238000007254 oxidation reaction Methods 0.000 claims description 10
- 238000000034 method Methods 0.000 description 12
- 238000001459 lithography Methods 0.000 description 5
- 238000002955 isolation Methods 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 4
- 230000015556 catabolic process Effects 0.000 description 3
- 229910052732 germanium Inorganic materials 0.000 description 3
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 3
- 238000005468 ion implantation Methods 0.000 description 3
- 150000002500 ions Chemical class 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- -1 but not limited to Chemical class 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 238000000609 electron-beam lithography Methods 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 238000005728 strengthening Methods 0.000 description 1
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
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- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
- H01L29/0692—Surface layout
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
- H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
- H01L29/0852—Source or drain regions of field-effect devices of field-effect transistors with insulated gate of DMOS transistors
- H01L29/0873—Drain regions
- H01L29/0878—Impurity concentration or distribution
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/107—Substrate region of field-effect devices
- H01L29/1075—Substrate region of field-effect devices of field-effect transistors
- H01L29/1079—Substrate region of field-effect devices of field-effect transistors with insulated gate
- H01L29/1083—Substrate region of field-effect devices of field-effect transistors with insulated gate with an inactive supplementary region, e.g. for preventing punch-through, improving capacity effect or leakage current
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7831—Field effect transistors with field effect produced by an insulated gate with multiple gate structure
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
- H01L29/42368—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity the thickness being non-uniform
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Description
本發明係有關一種雙擴散金屬氧化物半導體(double diffused metal oxide semiconductor,DMOS)元件，特別是指一種低導通電阻之DMOS元件。The present invention relates to a double diffused metal oxide semiconductor (DMOS) device, and more particularly to a low on-resistance DMOS device.
第1A-1C圖分別顯示先前技術之雙擴散金屬氧化物半導體(double diffused metal oxide semiconductor,DMOS)元件100之剖視圖、立體圖、與上視圖，如第1A-1C圖所示，P型基板11中具有隔絕區12，其圍繞一封閉區域(如第1C圖中，隔絕區12之粗黑框線所示意)，以定義DMOS元件100之功能區，隔絕區12與場氧化區12a例如為淺溝槽絕緣(shallow trench isolation,STI)結構或如圖所示之區域氧化(local oxidation of silicon,LOCOS)結構。DMOS元件100包含N型井區14、閘極13、汲極15、源極16、本體區17、本體極17a、以及場氧化區12a。其中，N型井區14、汲極15與源極16係由微影技術或以部分或全部之閘極13為遮罩，以定義各區域，並分別以離子植入技術，將N型雜質，以加速離子的形式，植入定義的區域內。其中，汲極15與源極16分別位於閘極13兩側下方；本體區17與本體極17a係由微影技術或以部分或全部之閘極13為遮罩，以定義各區域，並分別以離子植入技術，將P型雜質，以加速離子的形式，植入定義的區域內。而且DMOS元件中，閘極13有一部分位於場氧化區12a上。DMOS元件100為高壓元件，亦即其係設計用於供應較高的操作電壓，為了可以承受高壓，提高崩潰防護電壓， 往往犧牲導通電阻，限制了元件的應用範圍。特別是當DMOS元件100為一種超高壓元件時，也就是操作電壓大於500V，若不犧牲DMOS元件導通電阻，則必須犧牲崩潰防護電壓，或增加通道的寬度，但增加通道的寬度將提高製造成本，或是超過DMOS元件可容許的面積，才能達到所欲的導通電阻。受限於製造成本，且元件通道寬度亦有其限制，使得超高壓DMOS元件之導通電阻難以更進一步降低。1A-1C are cross-sectional, perspective, and top views, respectively, of a prior art double diffused metal oxide semiconductor (DMOS) device 100, as shown in FIGS. 1A-1C, in a P-type substrate 11 There is an isolation region 12 surrounding a closed region (as indicated by the thick black border of the isolation region 12 in FIG. 1C) to define a functional region of the DMOS device 100, and the isolation region 12 and the field oxide region 12a are, for example, shallow trenches. A shallow trench isolation (STI) structure or a local oxidation of silicon (LOCOS) structure as shown. The DMOS device 100 includes an N-type well region 14, a gate 13, a drain 15, a source 16, a body region 17, a body electrode 17a, and a field oxide region 12a. Wherein, the N-type well region 14, the drain electrode 15 and the source electrode 16 are masked by lithography techniques or with some or all of the gate electrodes 13 to define various regions, and the N-type impurities are respectively implanted by ion implantation techniques. , in the form of accelerated ions, implanted within defined areas. Wherein, the drain 15 and the source 16 are respectively located below the two sides of the gate 13; the body region 17 and the body pole 17a are masked by lithography or with some or all of the gates 13 to define regions and respectively P-type impurities are implanted into defined regions in the form of accelerated ions by ion implantation techniques. Further, in the DMOS device, a part of the gate 13 is located on the field oxide region 12a. The DMOS component 100 is a high voltage component, that is, it is designed to supply a higher operating voltage, and in order to withstand high voltage, increase the breakdown protection voltage, The on-resistance is often sacrificed, limiting the range of application of the component. Especially when the DMOS component 100 is an ultra-high voltage component, that is, the operating voltage is greater than 500V, if the on-resistance of the DMOS component is not sacrificed, the breakdown protection voltage must be sacrificed, or the width of the channel must be increased, but increasing the width of the channel will increase the manufacturing cost. Or, beyond the allowable area of the DMOS device, the desired on-resistance can be achieved. Limited by the manufacturing cost, and the component channel width also has its limitations, it is difficult to further reduce the on-resistance of the ultra-high voltage DMOS device.
有鑑於此，本發明即針對上述先前技術之不足，提出一種DMOS元件，在不增加製程步驟且不犧牲崩潰防護電壓的情況下，降低DMOS元件操作時之導通電阻，增加元件的應用範圍。In view of this, the present invention is directed to the above-mentioned deficiencies of the prior art, and proposes a DMOS device that reduces the on-resistance of the DMOS device during operation without increasing the process step and without sacrificing the breakdown protection voltage, thereby increasing the application range of the device.
本發明目的在提供一種DMOS元件。It is an object of the invention to provide a DMOS component.
為達上述之目的，本發明提供了一種DMOS元件，形成於一第一導電型基板中，該基板具有一上表面，該DMOS元件包含：一第二導電型高壓井區，形成於該上表面下之該基板中；一第一場氧化區，形成於該上表面上，由上視圖視之，該第一場氧化區位於該高壓井區中；一第一閘極，形成於該上表面上，且部分該第一閘極位於該第一場氧化區上；第二導電型第一源極、與第二導電型汲極，分別形成於該第一閘極兩側該上表面下方該高壓井區中，且由上視圖視之，該汲極與該第一源極由該第一閘極與該第一場氧化區隔開；一第一導電型本體區，形成於該上表面下該高壓井區中，且該第一源極位於該本體區中；一第一導電型本體極，形成於該上表面下該本體區中，用以作為該本體區之電性接點；一第二場 氧化區，形成於該上表面上，由上視圖視之，該第二場氧化區位於該高壓井區中，且該第二場氧化區與該第一場氧化區之間，由該本體區隔開；一第二閘極，形成於該上表面上，且部分該第二閘極位於該第二場氧化區上，另一部分該第二閘極位於該本體區上，該第二閘極與該第一閘極電連接；以及一第二導電型第二源極，形成於該第二閘極側邊之該上表面下方的該本體區中，且該第二源極與該第一源極電連接。In order to achieve the above object, the present invention provides a DMOS device formed in a first conductive type substrate having an upper surface, the DMOS device comprising: a second conductive type high voltage well region formed on the upper surface a first field oxide region formed on the upper surface, the first field oxide region being located in the high voltage well region; a first gate electrode formed on the upper surface And a portion of the first gate is located on the first field oxide region; the second conductive type first source and the second conductive type drain are respectively formed under the upper surface of the first gate In the high-voltage well region, and viewed from a top view, the drain and the first source are separated from the first field oxide region by the first gate; a first conductive type body region is formed on the upper surface In the high-voltage well region, the first source is located in the body region; a first conductive-type body electrode is formed in the body region under the upper surface to serve as an electrical contact of the body region; a second game An oxidation zone formed on the upper surface, viewed from a top view, the second field oxidation zone is located in the high pressure well zone, and the second field oxidation zone is between the first field oxidation zone and the body zone Separating; a second gate is formed on the upper surface, and a portion of the second gate is located on the second field oxide region, and another portion of the second gate is located on the body region, the second gate Electrically connecting to the first gate; and a second source of the second conductivity type formed in the body region below the upper surface of the second gate side, and the second source and the first The source is electrically connected.
在其中一種實施例中，該DMOS元件可更包含至少一第二導電型第一埋層，形成於該高壓井區下方，並與該高壓井區上下鄰接。In one embodiment, the DMOS device may further comprise at least one first conductivity type first buried layer formed under the high voltage well region and adjacent to the high voltage well region.
在上述實施例中，該第一埋層之數量可為複數，且第一埋層的第二導電型雜質濃度，宜高於該高壓井區的第二導電型雜質濃度。In the above embodiment, the number of the first buried layers may be a plurality, and the second conductive type impurity concentration of the first buried layer is preferably higher than the second conductive type impurity concentration of the high voltage well region.
在上述實施例中，該DMOS元件可更包含一第一導電型井區，形成於該本體區下方之該高壓井區中。In the above embodiment, the DMOS device may further include a first conductive type well region formed in the high voltage well region below the body region.
在上述實施例中，該井區宜與該本體區上下鄰接，且藉由相同遮罩形成。In the above embodiment, the well region is preferably adjacent to the body region and is formed by the same mask.
在上述實施例中，該DMOS元件可更包含至少一第一導電型第二埋層，形成於該高壓井區下方之該基板中。In the above embodiment, the DMOS device may further comprise at least one first conductivity type second buried layer formed in the substrate below the high voltage well region.
在上述實施例中，該第二埋層之數量可為複數，且第二埋層的第一導電型雜質濃度，宜高於該高壓井區的第一導電型雜質濃度，且該複數第二埋層，由上視圖示之，宜與該第一埋層交錯排列。In the above embodiment, the number of the second buried layer may be a plurality, and the first conductive type impurity concentration of the second buried layer is preferably higher than the first conductive type impurity concentration of the high voltage well region, and the plural second The buried layer, as shown in the upper view, is preferably staggered with the first buried layer.
在另一種實施例中，該DMOS元件可更包含至少一第二導電型深井區，形成於該汲極下方或/且該第二閘極下方之該高壓井區中。In another embodiment, the DMOS device can further include at least one second conductivity type deep well region formed in the high voltage well region below the drain gate and/or below the second gate.
在上述實施例中，該深井區中之第二導電型雜質濃度，宜高於該高壓井區中之第二導電型雜質濃度。In the above embodiment, the concentration of the second conductivity type impurity in the deep well region is preferably higher than the concentration of the second conductivity type impurity in the high pressure well region.
在另一種實施例中，該DMOS元件操作於導通的狀況時，宜於該汲極與該第一源極之間，形成一表層通道，且於該汲極與該第二源極之間，形成一埋層通道。In another embodiment, the DMOS device is adapted to be in a conducting state, preferably between the drain and the first source, forming a surface channel, and between the drain and the second source, A buried channel is formed.
底下藉由具體實施例詳加說明，當更容易瞭解本發明之目的、技術內容、特點及其所達成之功效。The purpose, technical content, features and effects achieved by the present invention will be more readily understood by the detailed description of the embodiments.
本發明中的圖式均屬示意，主要意在表示製程步驟以及各層之間之上下次序關係，至於形狀、厚度與寬度則並未依照比例繪製。The drawings in the present invention are schematic and are mainly intended to represent the process steps and the relationship between the layers, and the shapes, thicknesses, and widths are not drawn to scale.
請參閱第2A-2C圖，顯示本發明的第一個實施例，本實施例顯示應用本發明之DMOS元件200之製造方法示意圖。首先，如第2A與2B立體示意圖所示，提供基板21，其具有上表面21a，且基板21之導電型例如為P型但不限於為P型(在其他實施型態中亦可以為N型)；並且，基板21例如可以為非磊晶矽基板，亦可以為磊晶基板。接著，利用例如但不限於微影技術，形成光阻為遮罩(未示出)，以定義高壓井區24，並以例如但不限於離子植入技術，將N型雜質，以加速離子的形式，植入定義的區域內，於上表面21a下，形成N型高壓井區24於基板21中。接下來，如第2A圖所示，形成場氧化區22a及22b於上表面21a上。其中，場氧化區22a及22b例如為STI結構或如圖所示之LOCOS結構；並且，場氧化區22a及22b可利用但不限於相同製程步驟形成；此外，由上視圖視之(未示出，可參閱第2A與2B圖)，場氧 化區22a及22b位於高壓井區24中，且場氧化區22a及22b藉由高壓井區24與本體區27隔開(參閱第2B圖)。接著請參閱第2B圖，形成閘極23a及23b、汲極25、源極26a及26b、本體區27、與本體極27a。其中，如圖所示，閘極23a及23b形成於上表面21a上，且部分閘極23a位於場氧化區22a上；而部分閘極23b位於場氧化區22b上，另有一部分閘極23b位於本體區27上。汲極25與源極26a例如為N型但不限於為N型，分別位於閘極23a兩側上表面21a下方高壓井區24中，且由上視圖(未示出，請參閱第2B圖)視之，汲極25與源極26a由閘極23a與場氧化區22a隔開。而源極26b形成於閘極23b側邊之上表面21a下方的本體區27中；需注意的是，源極26b與源極26a皆形成於本體區27中，並互相電連接(請參閱第2C圖中，粗黑線段所示意)；其電連接的方式，例如可由後續之導電栓與金屬層達成，亦可以由基板21中的摻雜區(例如由源極26a及26b本身)達成。本體區27例如為P型但不限於為P型，形成於上表面21a下基板21中，且本體極27a形成於上表面21a下本體區27中，用以作為本體區27之電性接點。Referring to Figures 2A-2C, a first embodiment of the present invention is shown. This embodiment shows a schematic diagram of a method of fabricating a DMOS device 200 to which the present invention is applied. First, as shown in the perspective views of FIGS. 2A and 2B, a substrate 21 having an upper surface 21a is provided, and the conductivity type of the substrate 21 is, for example, a P type but is not limited to a P type (it may be N type in other embodiments). Further, the substrate 21 may be, for example, a non-devitrified germanium substrate or an epitaxial substrate. Next, using a lithography technique, for example, but not limited to, lithography, a photoresist is formed as a mask (not shown) to define a high voltage well region 24, and an N-type impurity is used to accelerate ions, such as, but not limited to, ion implantation techniques. Form, implanted within the defined area, under the upper surface 21a, an N-type high pressure well region 24 is formed in the substrate 21. Next, as shown in Fig. 2A, field oxide regions 22a and 22b are formed on the upper surface 21a. Wherein, the field oxide regions 22a and 22b are, for example, STI structures or LOCOS structures as shown; and the field oxide regions 22a and 22b may be formed using, but not limited to, the same process steps; further, viewed from a top view (not shown) , see Figures 2A and 2B), field oxygen The zones 22a and 22b are located in the high pressure well zone 24, and the field oxide zones 22a and 22b are separated from the body zone 27 by the high pressure well zone 24 (see Figure 2B). Next, referring to FIG. 2B, gates 23a and 23b, drain electrodes 25, source electrodes 26a and 26b, body region 27, and body electrode 27a are formed. Wherein, as shown, gates 23a and 23b are formed on the upper surface 21a, and a portion of the gate 23a is located on the field oxide region 22a; and a portion of the gate 23b is located on the field oxide region 22b, and a portion of the gate 23b is located. On the body area 27. The drain 25 and the source 26a are, for example, N-type but not limited to N-type, respectively located in the high-voltage well region 24 below the upper surface 21a of both sides of the gate 23a, and are viewed from above (not shown, see FIG. 2B). As such, the drain 25 and the source 26a are separated from the field oxide region 22a by the gate 23a. The source 26b is formed in the body region 27 below the upper surface 21a of the side of the gate 23b; it should be noted that the source 26b and the source 26a are both formed in the body region 27 and electrically connected to each other (see the In the 2C diagram, the thick black line segment is shown; the manner of electrical connection can be achieved, for example, by a subsequent conductive plug and a metal layer, or by a doped region in the substrate 21 (eg, by the source 26a and 26b itself). The body region 27 is, for example, P-type but not limited to a P-type, formed in the lower substrate 21 of the upper surface 21a, and the body pole 27a is formed in the lower body region 27 of the upper surface 21a for use as an electrical contact of the body region 27. .
與先前技術不同的是，在本實施例中，DMOS元件200具有兩個場氧化區22a與22b、兩個閘極23a與23b、與兩個源極26a與26b；並且，閘極23a與23b、源極26a與26b分別相互電連接；使得當DMOS元件200操作於導通的狀況時，於汲極25與源極26a之間，形成表層通道(如第2C圖中較疏之箭號虛折線所示意)；且於汲極25與源極26b之間，形成埋層通道(如第2C圖中較密之箭號虛折線所示意)。此種安排方式的優點包括：在元件規格上，由於多了一個埋層通 道，可降低DMOS元件的導通電阻；在製程上，場氧化區22b、閘極23b、源極26b，皆可以利用與場氧化區22a、閘極23a、源極26a相同的製程步驟完成，而不需要另外新增製程步驟，因此不會增加製造成本。Unlike the prior art, in the present embodiment, the DMOS device 200 has two field oxide regions 22a and 22b, two gates 23a and 23b, and two source electrodes 26a and 26b; and, gates 23a and 23b The source electrodes 26a and 26b are electrically connected to each other; respectively, such that when the DMOS device 200 is operated in a conducting state, a surface channel is formed between the drain electrode 25 and the source electrode 26a (as in the 2C figure, the arrow of the arrow is broken. Illustrated); and between the drain 25 and the source 26b, a buried channel is formed (as indicated by the dense arrow crease in Figure 2C). The advantages of this arrangement include: in the component specifications, due to the addition of a buried layer The circuit can reduce the on-resistance of the DMOS device; in the process, the field oxide region 22b, the gate 23b, and the source 26b can be completed by the same process steps as the field oxide region 22a, the gate 23a, and the source 26a. There is no need to add additional process steps, so there is no increase in manufacturing costs.
第3圖顯示本發明的第二個實施例，為應用本發明DMOS元件300之剖視示意圖。如圖所示，相較於第一個實施例，在本實施例中，DMOS元件300形成於基板31中，除包含場氧化區32a與32b、閘極33a與33b、高壓井區34、汲極35、源極36a與36b、本體區37、以及本體極37a之外，更包含至少一N型埋層38a，形成於高壓井區34下方，並與高壓井區34上下鄰接。需注意的是，埋層38a的N型雜質濃度，宜高於高壓井區34，且較佳的的安排方式，為於埋層通道中，以不連續的複數埋層38a，形成於高壓井區34下方，如此一來，可進一步降低埋層通道的導通電阻，並且對P型基板31與N型高壓井區34於元件操作於不導通狀況下，對崩潰防護電壓影響較小。Figure 3 is a cross-sectional view showing a second embodiment of the present invention for applying the DMOS device 300 of the present invention. As shown, in the present embodiment, the DMOS device 300 is formed in the substrate 31 except for the field oxide regions 32a and 32b, the gates 33a and 33b, the high voltage well region 34, and the germanium. The pole 35, the source 36a and 36b, the body region 37, and the body pole 37a further include at least one N-type buried layer 38a formed below the high-voltage well region 34 and adjacent to the high-voltage well region 34. It should be noted that the N-type impurity concentration of the buried layer 38a is preferably higher than that of the high-voltage well region 34, and the preferred arrangement is that in the buried channel, a discontinuous plurality of buried layers 38a are formed in the high-pressure well. Below the region 34, in this way, the on-resistance of the buried channel can be further reduced, and the P-type substrate 31 and the N-type high-voltage well region 34 are less affected by the collapse protection voltage when the component is operated in a non-conducting state.
第4圖顯示顯示本發明的第三個實施例，為應用本發明DMOS元件400之剖視示意圖。如圖所示，相較於第一個實施例，在本實施例中，DMOS元件400形成於基板41中，除包含場氧化區42a與42b、閘極43a與43b、高壓井區44、汲極45、源極46a與46b、本體區47、以及本體極47a之外，更包含至少一N型深井區49，形成於汲極45下方或/且閘極43b下方之高壓井區44中。其中N型深井區49中之N型雜質濃度，宜高於高壓井區44中之N型雜質濃度。與第二個實施例相似，這種安排方式，可以進一步降低DMOS元件400的導通電阻。Figure 4 is a cross-sectional view showing a third embodiment of the present invention for applying the DMOS device 400 of the present invention. As shown, in the present embodiment, the DMOS device 400 is formed in the substrate 41 except for the field oxide regions 42a and 42b, the gates 43a and 43b, the high voltage well region 44, and the germanium. The pole 45, the source 46a and 46b, the body region 47, and the body pole 47a further comprise at least one N-type deep well region 49 formed in the high voltage well region 44 below the drain 45 or/and below the gate 43b. The N-type impurity concentration in the N-type deep well region 49 is preferably higher than the N-type impurity concentration in the high-pressure well region 44. Similar to the second embodiment, this arrangement can further reduce the on-resistance of the DMOS device 400.
第5圖顯示顯示本發明的第四個實施例，為應用本發明DMOS元件500之剖視示意圖。如圖所示，與第二個實施例相似，在本實施例中，DMOS元件500形成於基板51中，除包含場氧化區52a與52b、閘極53a與53b、高壓井區54、汲極55、源極56a與56b、本體區57、以及本體極57a之外，更包含至少一N型埋層58a，形成於高壓井區54下方，並與高壓井區54上下鄰接；以及P型井區57b，形成於本體區57下方之高壓井區54中。與第二個實施例相似，這種安排方式，可以進一步降低DMOS元件500的導通電阻。需注意的是，P型井區57b宜與本體區57上下鄰接，且藉由相同遮罩形成，如此一來，可降低N型埋層58a對本體區57的影響。Fig. 5 is a cross-sectional view showing the fourth embodiment of the present invention for applying the DMOS device 500 of the present invention. As shown in the figure, similarly to the second embodiment, in the present embodiment, the DMOS device 500 is formed in the substrate 51 except for the field oxide regions 52a and 52b, the gates 53a and 53b, the high voltage well region 54, and the drain electrode. 55, the source 56a and 56b, the body region 57, and the body pole 57a, further comprising at least one N-type buried layer 58a formed under the high-voltage well region 54 and adjacent to the high-voltage well region 54; and the P-well Zone 57b is formed in high voltage well region 54 below body region 57. Similar to the second embodiment, this arrangement can further reduce the on-resistance of the DMOS device 500. It should be noted that the P-type well region 57b should be adjacent to the upper and lower portions of the body region 57 and formed by the same mask, so that the influence of the N-type buried layer 58a on the body region 57 can be reduced.
第6圖顯示顯示本發明的第五個實施例，為應用本發明DMOS元件600之剖視示意圖。如圖所示，與第二個實施例相似，在本實施例中，DMOS元件600形成於基板61中，除包含場氧化區62a與62b、閘極63a與63b、高壓井區64、汲極65、源極66a與66b、本體區67、以及本體極67a之外，更包含至少一N型埋層68a，形成於高壓井區64下方，並與高壓井區64上下鄰接；以及至少一N型深井區69，形成於汲極65下方或/且閘極63b下方之高壓井區64中。與第二個實施例相似，這種安排方式，可以進一步降低DMOS元件600的導通電阻。本實施例旨在說明，第二個實施例與第三個實施例可以結合實施。Figure 6 is a cross-sectional view showing a fifth embodiment of the present invention for applying the DMOS device 600 of the present invention. As shown in the figure, similarly to the second embodiment, in the present embodiment, the DMOS device 600 is formed in the substrate 61 except for the field oxide regions 62a and 62b, the gates 63a and 63b, the high voltage well region 64, and the drain. 65. The source 66a and 66b, the body region 67, and the body pole 67a further comprise at least one N-type buried layer 68a formed under the high voltage well region 64 and adjacent to the high voltage well region 64; and at least one N The deep well region 69 is formed in the high pressure well region 64 below the drain 65 or/and below the gate 63b. Similar to the second embodiment, this arrangement can further reduce the on-resistance of the DMOS device 600. This embodiment is intended to illustrate that the second embodiment and the third embodiment can be implemented in combination.
第7A與7B圖顯示顯示本發明的第六個實施例，分別為應用本發明DMOS元件700之剖視與上視示意圖。如第7A圖所示，與第二個實施例相似，在本實施例中，DMOS元件700形成於基板71中，除包含場氧化區72a與72b、閘極73a 與73b、高壓井區74、汲極75、源極76a與76b、本體區77、以及本體極77a之外，更包含至少一N型埋層78a，形成於高壓井區74下方，並與高壓井區74上下鄰接；以及P型埋層78b，形成於本體區77下方之高壓井區74中。與第二個實施例相似，這種安排方式，除可以進一步降低DMOS元件700的導通電阻，更可於DMOS元件700不導通時，強化高壓井區74中的空乏區，以維持所需之崩潰防護電壓。需注意的是，埋層78b的P型雜質濃度，宜較基板71的P型雜質濃高，且較佳的的安排方式，如第7B圖所示，為於埋層78a下方，由上視圖示之，與埋層78a交錯排列的方式，形成埋層78b，如此一來，其強化高壓井區74中的空乏區之效果較佳。7A and 7B are views showing a sixth embodiment of the present invention, respectively, showing a cross-sectional view and a top view of a DMOS device 700 to which the present invention is applied. As shown in FIG. 7A, similarly to the second embodiment, in the present embodiment, the DMOS device 700 is formed in the substrate 71 except for the field oxide regions 72a and 72b and the gate 73a. In addition to 73b, high-voltage well region 74, drain 75, source 76a and 76b, body region 77, and body pole 77a, at least one N-type buried layer 78a is formed, formed under high-voltage well region 74, and with high voltage The well region 74 is vertically adjacent; and the P-type buried layer 78b is formed in the high voltage well region 74 below the body region 77. Similar to the second embodiment, this arrangement can further reduce the on-resistance of the DMOS device 700, and further strengthen the depletion region in the high-voltage well region 74 when the DMOS device 700 is not conducting to maintain the required collapse. Protection voltage. It should be noted that the P-type impurity concentration of the buried layer 78b is preferably higher than that of the P-type impurity of the substrate 71, and a preferred arrangement, as shown in FIG. 7B, is below the buried layer 78a, from the top view. As shown, the buried layer 78b is formed in a staggered manner with the buried layer 78a, so that the effect of strengthening the depletion region in the high-pressure well region 74 is better.
第8圖顯示顯示本發明的第七個實施例，為應用本發明DMOS元件800之剖視示意圖。如圖所示，在本實施例中，DMOS元件800形成於基板81中，除包含場氧化區82a與82b、閘極83a與83b、高壓井區84、汲極85、源極86a與86b、本體區87、以及本體極87a之外，更包含至少一N型埋層88a、至少一N型深井區89、形成於本體區87下方之P型井區87b、以及至少一P型埋層88b。本實施例旨在說明，上述所有實施例可以結合實施。Figure 8 is a cross-sectional view showing a seventh embodiment of the present invention for applying the DMOS device 800 of the present invention. As shown, in the present embodiment, DMOS device 800 is formed in substrate 81, except for field oxide regions 82a and 82b, gates 83a and 83b, high voltage well region 84, drain 85, source electrodes 86a and 86b, The body region 87 and the body pole 87a further include at least one N-type buried layer 88a, at least one N-type deep well region 89, a P-type well region 87b formed under the body region 87, and at least one P-type buried layer 88b. . This embodiment is intended to illustrate that all of the above embodiments can be implemented in combination.
第9圖顯示顯示本發明的第八個實施例，為應用本發明DMOS元件900之上視示意圖。DMOS元件900除包含場氧化區92a與92b、閘極93a(如圖中較疏之粗虛線所示意)與93b(如圖中較密之粗虛線所示意)、高壓井區94、汲極95、源極96a與96b、本體區97、以及本體極97a之外，更包含至少一N型埋層(未示出)，形成於高壓井區94下方，並與高 壓井區94上下鄰接。本實施例旨在說明，由上視圖示之，應用本發明之DMOS元件，可以為如圖所示之圓形，或為其他任意的形狀。Fig. 9 is a top plan view showing the eighth embodiment of the present invention for applying the DMOS device 900 of the present invention. The DMOS device 900 includes field oxide regions 92a and 92b, gate electrodes 93a (shown as thicker dashed lines in the figure) and 93b (shown as thicker thick lines in the figure), high pressure well region 94, and drain 95. The source electrodes 96a and 96b, the body region 97, and the body electrode 97a further include at least one N-type buried layer (not shown) formed under the high-voltage well region 94 and high. The kill zone 94 is adjacent to the top and bottom. This embodiment is intended to illustrate that the DMOS component to which the present invention is applied may be circular as shown or of any other shape as shown in the upper view.
以上已針對較佳實施例來說明本發明，唯以上所述者，僅係為使熟悉本技術者易於了解本發明的內容而已，並非用來限定本發明之權利範圍。在本發明之相同精神下，熟悉本技術者可以思及各種等效變化。例如，在不影響元件主要的特性下，可加入其他製程步驟或結構，如臨界電壓調整區等；又如，微影技術並不限於光罩技術，亦可包含電子束微影技術；再如，DMOS元件各區之P或N之導電型可以改變，只要對其他區域之導電型與雜質濃度等做相應之改變或調整即可。本發明的範圍應涵蓋上述及其他所有等效變化。The present invention has been described with reference to the preferred embodiments thereof, and the present invention is not intended to limit the scope of the present invention. In the same spirit of the invention, various equivalent changes can be conceived by those skilled in the art. For example, other process steps or structures, such as a threshold voltage adjustment region, may be added without affecting the main characteristics of the component; for example, the lithography technology is not limited to the reticle technology, and may also include electron beam lithography; The conductivity type of P or N of each region of the DMOS device can be changed, as long as the conductivity type and impurity concentration of other regions are changed or adjusted accordingly. The above and other equivalent variations are intended to be covered by the scope of the invention.
11,21,31,41,51,61,71,81‧‧‧基板11,21,31,41,51,61,71,81‧‧‧substrate
12a,22a,32a,42a,52a,62a,72a,82a,92a,12b,22b,32b,42b,52b,62b,72b,82b,92b‧‧‧場氧化區12a, 22a, 32a, 42a, 52a, 62a, 72a, 82a, 92a, 12b, 22b, 32b, 42b, 52b, 62b, 72b, 82b, 92b‧‧ ‧ field oxidation zone
13a,23a,33a,43a,53a,63a,73a,83a,93a,13b,23b,33b,43b,53b,63b,73b,83b,93b‧‧‧閘極13a, 23a, 33a, 43a, 53a, 63a, 73a, 83a, 93a, 13b, 23b, 33b, 43b, 53b, 63b, 73b, 83b, 93b‧‧ ‧ gate
14,24,34,44,54,64,74,84,94‧‧‧高壓井區14,24,34,44,54,64,74,84,94‧‧‧High-pressure well area
15,25,35,45,55,65,75,85,95‧‧‧汲極15,25,35,45,55,65,75,85,95‧‧‧bungee
16a,26a,36a,46a,56a,66a,76a,86a,96a,16b,26b,36b,46b,56b,66b,76b,86b,96b‧‧‧源極16a, 26a, 36a, 46a, 56a, 66a, 76a, 86a, 96a, 16b, 26b, 36b, 46b, 56b, 66b, 76b, 86b, 96b‧ ‧ source
17,27,37,47,57,67,77,87,97‧‧‧本體區17,27,37,47,57,67,77,87,97‧‧‧ body area
17a,27a,37a,47a,57a,67a,77a,87a,97a‧‧‧本體極17a, 27a, 37a, 47a, 57a, 67a, 77a, 87a, 97a‧‧ ‧ body
21a‧‧‧上表面21a‧‧‧Upper surface
38a,58a,68a,78a,78b,88a,88b‧‧‧埋層38a, 58a, 68a, 78a, 78b, 88a, 88b‧‧ ‧ buried layer
49,69,89‧‧‧深井區49,69,89‧‧‧Shenjing District
57b,87b‧‧‧井區57b, 87b‧‧‧ Well Area
100,200,300,400,500,600,700,800,900‧‧‧DMOS元件100,200,300,400,500,600,700,800,900‧‧‧DMOS components
第1A-1C圖分別顯示先前技術之DMOS元件之剖視圖、立體圖、與上視圖。1A-1C are cross-sectional, perspective, and top views, respectively, of a prior art DMOS device.
第2A-2C圖顯示本發明的第一個實施例。Fig. 2A-2C shows a first embodiment of the present invention.
第3圖顯示本發明的第二個實施例。Figure 3 shows a second embodiment of the invention.
第4圖顯示本發明的第三個實施例。Fig. 4 shows a third embodiment of the present invention.
第5圖顯示顯示本發明的第四個實施例。Fig. 5 shows a fourth embodiment showing the present invention.
第6圖顯示顯示本發明的第五個實施例。Fig. 6 shows a fifth embodiment showing the present invention.
第7A與7B圖顯示顯示本發明的第六個實施例。Figures 7A and 7B show a sixth embodiment of the present invention.
第8圖顯示顯示本發明的第七個實施例。Fig. 8 shows a seventh embodiment showing the present invention.
第9圖顯示顯示本發明的第八個實施例。Fig. 9 shows an eighth embodiment showing the present invention.
21‧‧‧基板21‧‧‧Substrate
21a‧‧‧上表面21a‧‧‧Upper surface
22a,22b‧‧‧場氧化區22a, 22b‧‧‧ field oxidation zone
23a,23b‧‧‧閘極23a, 23b‧‧‧ gate
24‧‧‧高壓井區24‧‧‧High-pressure well area
25‧‧‧汲極25‧‧‧汲polar
26a,26b‧‧‧源極26a, 26b‧‧‧ source
27‧‧‧本體區27‧‧‧ Body area
27a‧‧‧本體極27a‧‧‧ body pole
200‧‧‧DMOS元件200‧‧‧DMOS components
Claims (7)
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| TW101116810A TWI476924B (en) | 2012-05-11 | 2012-05-11 | Double diffused metal oxide semiconductor device |
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|---|---|---|---|
| TW101116810A TWI476924B (en) | 2012-05-11 | 2012-05-11 | Double diffused metal oxide semiconductor device |
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| TWI476924B true TWI476924B (en) | 2015-03-11 |
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| US9627528B2 (en) | 2015-09-11 | 2017-04-18 | Macronix International Co., Ltd. | Semiconductor device having gate structures and manufacturing method thereof |
| TWI634660B (en) * | 2017-06-20 | 2018-09-01 | 世界先進積體電路股份有限公司 | High voltage semiconductor device and method for manufacturing the same |
| US10128331B1 (en) | 2017-08-01 | 2018-11-13 | Vanguard International Semiconductor Corporation | High-voltage semiconductor device and method for manufacturing the same |
| TWI673869B (en) * | 2018-07-31 | 2019-10-01 | 新唐科技股份有限公司 | High voltage semiconductor devices and methods for manufacturing the same |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4914051A (en) * | 1988-12-09 | 1990-04-03 | Sprague Electric Company | Method for making a vertical power DMOS transistor with small signal bipolar transistors |
| US6169309B1 (en) * | 1997-09-30 | 2001-01-02 | Texas Instruments Incorporated | High breakdown-voltage transistor with transient protection |
| US20070063271A1 (en) * | 2005-08-31 | 2007-03-22 | Sharp Kabushiki Kaisha | Lateral double-diffused field effect transistor and integrated circuit having same |
| US20100078720A1 (en) * | 2008-09-30 | 2010-04-01 | Nec Electronics Corporation | Semiconductor device and method for manufacturing the same |
-
2012
- 2012-05-11 TW TW101116810A patent/TWI476924B/en active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4914051A (en) * | 1988-12-09 | 1990-04-03 | Sprague Electric Company | Method for making a vertical power DMOS transistor with small signal bipolar transistors |
| US6169309B1 (en) * | 1997-09-30 | 2001-01-02 | Texas Instruments Incorporated | High breakdown-voltage transistor with transient protection |
| US20070063271A1 (en) * | 2005-08-31 | 2007-03-22 | Sharp Kabushiki Kaisha | Lateral double-diffused field effect transistor and integrated circuit having same |
| US20100078720A1 (en) * | 2008-09-30 | 2010-04-01 | Nec Electronics Corporation | Semiconductor device and method for manufacturing the same |
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