TWI434331B - Method of manufacturing depletion mos device - Google Patents

Description

Method for manufacturing depleted metal oxide semiconductor device

The present invention relates to a method of fabricating a depletion type metal oxide semiconductor device, and more particularly to a method of fabricating a depleted metal oxide semiconductor device having collapse protection.

1 is a cross-sectional view showing a prior art double-diffused drain metal oxide semiconductor (DDDMOS). As shown in FIG. 1, a P-type well region 11 is formed in a P-type germanium substrate 1. And the insulating structure 12 to define the element region 100, and the insulating structure 12 is, for example, a local oxidation of silicon (LOCOS) structure. In the element region 100, a gate 13, a drift region 14, a source 15a, a drain 15, a P-type heavily doped region 16, and a threshold voltage adjustment region 17 are formed. Wherein, the P-type well region 11 can be the substrate 1 itself, and the drift region 14, the source 15a, the drain 15 and the threshold voltage adjustment region 17 are defined by lithography techniques, and respectively, by ion implantation technology, N Type impurity, implanted in the defined region in the form of accelerated ions; P-type heavily doped region 16 is also defined by lithography technology, and ion implantation technique, P-type impurity, in the form of accelerated ions, implanted Within the defined area. The source 15a and the drain 15 are respectively located below the two sides of the gate 13 , the drift region 14 is located on the drain side and partially below the gate 13 , and the threshold voltage adjustment region 17 is partially located below the gate 13 to adjust the depletion type. The threshold voltage of the metal oxide semiconductor device is separated between the source 15a and the P-type heavily doped region 16 by the insulating structure 12. Since the impurity doped by the threshold voltage adjustment region 17 is the same as the drift region 14, it is N-type, and therefore, when the depleted MOS device is operated, it is easier than the reinforced metal oxide semiconductor device. A collapse occurs, especially in Figure 1, where the area indicated by the circular dashed line, that is, below the gate edge near the bungee, is more prone to band-to-band collapse and lower The breakdown voltage limits the application range of the component.

2 is a cross-sectional view showing a prior art lateral diffused metal oxide semiconductor (LDMOS). Compared with the prior art of FIG. 1, the LDMOS shown in FIG. 2 has a body pole 18 and a gate thereof. A portion of 13 is located on the insulating structure 12. Similarly, the LDMOS shown in this figure has the same problem as the aforementioned DDDMOS in the range indicated by the circular dotted line in the figure, that is, the band-to-band collapse is more likely to occur, and the LDMOS is reduced. The breakdown voltage limits the application range of the component.

Figure 3 is a cross-sectional view showing another prior art depletion double-diffused-drain metal oxide semiconductor device, referred to herein as DMOS, which is the same as in Figure 1, which is also indicated by a circular dashed line in the figure. It is easier to have a band-to-band crash, which reduces the breakdown voltage and limits the application range of the component.

In the past, the method for solving the above problems has focused on adjusting the implantation concentration or diffusion range of the drift region 14, the source 15a, the drain 15, or the threshold voltage adjustment region 17, but it does not effectively solve the problem. For this reason, the circuit does not have only a depleted metal oxide semiconductor component alone, but usually includes a reinforced metal oxide semiconductor device. In the process, the drift region 14, the source 15a, and the drain 15 of the reinforced and depleted components are first fabricated with the same implant parameters, and then the threshold voltage adjustment region 17 of the depletion element is implanted to the component. Transition from a reinforced component to a depleted component. In other words, the parameters of the drift region 14, the source 15a, and the drain 15 of the reinforced and depleted components in the circuit are common. If the parameters of the vacant component are adjusted, the performance of the reinforced component will be affected. Therefore, in terms of fabricating the depletion element, the only adjustment parameter is the implantation parameter of the threshold voltage adjustment region 17, but the concentration of the threshold voltage adjustment region 17 must not be too low, otherwise the reinforced component cannot be converted into a depletion component. Therefore, under the above limitations, the prior art cannot solve the problem of band-band collapse as described above.

In view of the above, the present invention is directed to the deficiencies of the prior art described above, and provides a method for manufacturing a depleted metal oxide semiconductor device, which can improve the breakdown voltage of the device operation and increase the application range of the device.

SUMMARY OF THE INVENTION An object of the present invention is to provide a method of manufacturing a depleted metal oxide semiconductor device.

In order to achieve the above object, the present invention provides a method for fabricating a depleted metal oxide semiconductor device, comprising: providing a substrate, and forming a first conductive type well region and an insulating structure in the substrate to define an element region; The drift region, the source, the drain, and the threshold voltage adjustment region are respectively defined in the component region, and second conductivity type impurities are respectively implanted to form the drift region, the source, the drain, and the threshold voltage adjustment region; Defining a collision protection zone between the drain electrode and the threshold voltage adjustment zone in the component region, and implanting a first conductivity type impurity to form the breakdown protection zone; and forming a gate in the component region; wherein the collapse protection The zone portion is located below the gate and its range includes the edge of the threshold voltage adjustment zone near the drain side.

In one embodiment, the first conductivity type is a P type and the second conductivity type is an N type. In another embodiment, the first conductivity type is an N type, and the second conductivity type is a P type.

In one embodiment, the insulating structure can be a regional oxide structure or a shallow trench isolation (STI) structure.

In the above method for manufacturing a depleted metal oxide semiconductor device, the definition of the collapse protection zone can be defined by a dedicated photomask.

In one embodiment, the definition of the crash protection zone may also be defined by a first conductivity type lightly doped yttrium reticle, which simultaneously defines another one on the same substrate. The first conductivity type lightly doped drain region of the opposite conduction type metal oxide semiconductor device.

In another embodiment, the definition of the crash protection zone may also be defined by a first conductivity type anti-through tunneling mask, which simultaneously defines another one on the same substrate. The first conductivity type reverse tunneling effect region of the opposite conduction type metal oxide semiconductor device.

In another embodiment, the depleted metal oxide semiconductor device is a double diffused drain metal oxide semiconductor (DDDMOS) or a lateral diffused metal oxide semiconductor (LDMOS). ).

The purpose, technical content, features and effects achieved by the present invention will be more readily understood by the detailed description of the embodiments.

The drawings in the present invention are schematic and are mainly intended to represent the process steps and the relationship between the layers, and the shapes, thicknesses, and widths are not drawn to scale.

Referring to the cross-sectional flowchart of FIGS. 4A-4D, an embodiment of the present invention is shown. This embodiment shows a method of fabricating a depleted double-diffused gate metal oxide semiconductor device 10. As shown in FIG. 4A, a substrate 1 is first provided, such as but not limited to a P-type or N-type germanium substrate, and then a first conductive type well region 11 and an insulating structure 12 are formed in the substrate 1 to define an element region 100. As shown in the figure, the element region 100 is defined between the insulating structures 12, and the insulating structure 12 may be formed by a region oxidation (LOCOS) or shallow trench isolation (STI) process technology. In the present embodiment, the insulating structure 12 is, for example, For the LOCOS structure. In addition, the first conductive type well region 11 may be, but not limited to, the substrate 1 itself, or may be defined by lithography technology, and is doped by ion implantation technology to dope the first conductivity type impurity to the defined region. Next, as shown in FIG. 4B, a drift region 14, a source 15a, a drain 15, a first conductive type heavily doped region 16, and a threshold voltage adjustment region 17 are formed in the element region 100. Wherein, the drift region 14, the source 15a, the drain 15 and the threshold voltage adjustment region 17 are defined by lithography techniques, and the second conductivity type impurity, such as but not limited to an N-type impurity, is ion-implanted. In the form of accelerating ions, as indicated by the dotted arrows in the figure, they are respectively implanted into the defined regions; the first conductive type heavily doped region 16 is also defined by the lithography technique, and is implanted by ion implantation technology. A conductive impurity, such as, but not limited to, a P-type impurity, is implanted in a defined region in the form of an accelerated ion. The source 15a and the drain 15 are respectively located on both sides of the gate 13. The drift region 14 is located on the drain side and partially below the gate 13. The threshold voltage adjustment region 17 is partially located below the gate 13 to adjust the depleted metal. The threshold voltage of the oxide semiconductor device is separated from the first conductive type heavily doped region 16 by the insulating structure 12.

Next, as shown in FIG. 4C, unlike the prior art, the present embodiment increases the formation of the collapse protection zone 19 in the manner indicated by the dashed arrow in FIG. 4C, and the first conductivity is performed by ion implantation technology. Type impurities, such as, but not limited to, P-type impurities, are implanted in defined regions in the form of accelerated ions; the extent of the collapse protection region 19 preferably includes the edge of the threshold voltage adjustment region 17 near the side of the drain 15 . Since the impurity implanted in the collapse protection zone 19 is opposite to the conduction pattern of the drift region 14, the drain electrode 15, and the threshold voltage adjustment region 17, the breakdown voltage can be increased. It should be noted that although the first conductive type impurity is implanted in the collapse protection zone 19, the integral component is still a depleted component, that is, the collapse protection zone 19 is a lighter second conductivity type. The scope of the crash protection zone 19 can be defined by a dedicated mask, but the preferred method is to share the mask of other components on the substrate 1 and complete the process steps of the other components to save the process steps and the cost of the mask. The common reticle and process steps suitable for use as the crash protection zone 19 will be detailed later.

Next, as shown in FIG. 4D, the gate 13 is formed in the element region 100, that is, the depletion type double-diffused gate metal oxide semiconductor device 10 is completed; wherein the manner and material of the gate 13 are formed in various ways. , well-known to the technical person, because it is not the focus of this case, it will not be repeated.

Fig. 5 is a view showing a second embodiment of the present invention. This embodiment shows a cross-sectional view of the present invention applied to a depleted laterally diffused metal oxide semiconductor device, which is manufactured in a manner similar to that of the first embodiment, and in this embodiment, collapses. The range of the guard zone 19 also includes the edge of the threshold voltage adjustment zone 17 near the side of the drain 15 but is located below the gate 13 at the interface with the insulating structure 12.

Figure 6 is a view showing a third embodiment of the present invention. This embodiment shows a cross-sectional view of the present invention applied to a depleted DMOS device. The manufacturing method is similar to that of the first embodiment. In this embodiment, the collapse protection zone 19 has the same range. The edge of the threshold voltage adjustment region 17 near the side of the drain 15 is included.

Fig. 7 shows a fourth embodiment of the present invention. This embodiment shows that on the same substrate 1, in addition to the depletion type double-diffused gate-metal oxide semiconductor device 10, another opposite is produced in the other device region 200. The conductive metal oxide semiconductor device 20 is, for example but not limited to, a reinforced high voltage component as shown, and may also be a low voltage component or a depleted component. Since it is the oppositely-conducting metal oxide semiconductor device 20, the source 25a and the drain 25 of the opposite conduction type are formed, and it is usually necessary to form the lightly doped region 19a. Therefore, the collapse protection zone 19 of the depletion element 10 can utilize the first conductivity type lightly doped deuterium reticle used in forming the lightly doped region 19a by the oppositely conductive element 20 as a common reticle. The defined range of the collapse protection zone 19 is opened, and in the same step of forming the lightly doped region 19a, the first conductivity type impurity is implanted into the collapse protection zone 19 to achieve the object of the present invention. In addition to the lightly doped dipole mask using the opposite conduction type element, similarly, the first conductivity type anti-through tunneling mask of another metal oxide semiconductor element on the same substrate 1 can also be used as the formation. a common reticle of the collapse protection zone 19, the first conductivity type anti-through tunneling mask simultaneously defining the collapse protection zone 19 of the depletion element 10, and also defining the first of the other MOS devices on the same substrate Conductive type anti-through tunneling region.

The present invention has been described with reference to the preferred embodiments thereof, and the present invention is not intended to limit the scope of the present invention. In the same spirit of the invention, various equivalent changes can be conceived by those skilled in the art. For example, other process steps or structures, such as deep well areas, may be added without affecting the main characteristics of the components; for example, lithography is not limited to reticle technology, and may include electron beam lithography. The above and other equivalent variations are intended to be covered by the scope of the invention.

1. . . Substrate

10. . . Depleted metal oxide semiconductor device

11. . . First conductivity type well area

12. . . Insulation structure

13. . . Gate

14. . . Drift zone

15. . . Bungee

15a. . . Source

16. . . First conductivity type impurity heavily doped region

17. . . Threshold voltage adjustment zone

19. . . Crash protection zone

19a. . . Lightly doped area

20. . . Another metal oxide semiconductor device

25. . . Bungee

25a. . . Source

100,200. . . Component area

Figure 1 shows a cross-sectional view of a prior art double diffused drain metal oxide semiconductor device.

Figure 2 shows a cross-sectional view of a prior art lateral diffusing element.

Figure 3 shows a cross-sectional view of another prior art double diffused drain metal oxide semiconductor device.

A cross-sectional flow chart of Figures 4A-4D shows a first embodiment of the present invention.

Fig. 5 shows a second embodiment of the present invention.

Fig. 6 shows a third embodiment of the present invention.

Fig. 7 shows a fourth embodiment of the present invention.

1. . . Substrate

11. . . First conductivity type well area

12. . . Insulation structure

13. . . Gate

14. . . Drift zone

15. . . Bungee

15a. . . Source

16. . . First conductivity type impurity heavily doped region

17. . . Threshold voltage adjustment zone

19. . . Crash protection zone

Claims (8)

A manufacturing method of a depleted metal oxide semiconductor device, comprising: providing a substrate, forming a first conductive type well region and an insulating structure in the substrate to define an element region; respectively defining a drift region and a source in the device region a pole, a drain, and a threshold voltage adjustment region, and implanting a second conductivity type impurity to form the drift region, the source, the drain, and the threshold voltage adjustment region; and the threshold voltage adjustment in the device region Defining a collision protection zone between the zones, and implanting a first conductivity type impurity to form the collapse protection zone; and forming a gate in the component region; wherein the collapse protection zone portion is located below the gate, and the range thereof comprises The threshold voltage adjustment zone is near the edge of the drain side. The method for manufacturing a depleted metal oxide semiconductor device according to claim 1, wherein the depleted metal oxide semiconductor device is a double diffused drain metal oxide semiconductor (DDDMOS). Or a lateral diffused metal oxide semiconductor (LDMOS). The method of manufacturing a depleted metal oxide semiconductor device according to claim 1, wherein the first conductivity type is a P type and the second conductivity type is an N type. The method of manufacturing a depleted metal oxide semiconductor device according to claim 1, wherein the first conductivity type is an N type and the second conductivity type is a P type. The method of manufacturing a depleted metal oxide semiconductor device according to claim 1, wherein the insulating structure is a region oxidized structure or a shallow trench insulating structure. The method for manufacturing a depleted metal oxide semiconductor device according to claim 1, wherein the definition of the collapse protection zone is defined by a dedicated photomask. A manufacturing method of a depleted metal oxide semiconductor device, comprising: providing a substrate, forming a first conductive type well region and an insulating structure in the substrate to define an element region; respectively defining a drift region and a source in the device region a pole, a drain, and a threshold voltage adjustment region, and implanting a second conductivity type impurity to form the drift region, the source, the drain, and the threshold voltage adjustment region; and the threshold voltage adjustment in the device region Defining a collision protection zone between the zones, and implanting a first conductivity type impurity to form the breakdown protection zone; forming a gate in the component region; and forming another opposite conductivity type metal oxide on the same substrate a semiconductor device in which a first conductivity type lightly doped germanium photomask is used to define a first conductivity type lightly doped drain region of the oppositely conductive metal oxide semiconductor device, and the photomask simultaneously defines the depletion A breakdown protection zone for a metal oxide semiconductor device. A manufacturing method of a depleted metal oxide semiconductor device, comprising: providing a substrate, forming a first conductive type well region and an insulating structure in the substrate to define an element region; respectively defining a drift region and a source in the device region a pole, a drain, and a threshold voltage adjustment region, and implanting a second conductivity type impurity to form the drift region, the source, the drain, and the threshold voltage adjustment region; and the threshold voltage adjustment in the device region Defining a collision protection zone between the zones, and implanting a first conductivity type impurity to form the collapse protection zone; forming a gate in the component region; Forming another metal oxide semiconductor device on the same substrate, wherein a first conductivity type anti-through tunneling mask is used to define a first conductivity type reverse tunneling effect region of the metal oxide semiconductor device, and the photomask is used At the same time, the collapse protection zone of the depleted metal oxide semiconductor device is defined.