TW201407689A - Method of manufacturing high voltage depletion metal oxide semiconductor device - Google Patents

Abstract

The present invention discloses a method of manufacturing a high voltage depletion metal oxide semiconductor (MOS) device. The method includes: providing a substrate; forming a first conductive type well and isolation regions in the substrate to define a device area; defining a drift region and a threshold voltage adjustment region, and implanting second conductive type impurities to form the drift region and the threshold voltage adjustment region, respectively; forming a gate in the device area; and forming a source and a drain at different sides of the gate in the device region. In the step of defining the threshold voltage adjustment region, a mask is formed by photoresist for masking part of the drift region to define a shield region in the threshold voltage adjustment region, such that, when the second conductive type impurities are implanted to form the threshold voltage adjustment region, the concentration of the second conductive type impurities in the shield region is lower than that in the other region of the threshold voltage adjustment region.

Description

Method for manufacturing high-voltage depletion type metal oxide semiconductor device

The present invention relates to a method for manufacturing a high voltage depletion type metal oxide semiconductor (MOS), and more particularly to a method for manufacturing a high voltage depletion metal oxide semiconductor device having a high breakdown protection voltage. .

1 is a cross-sectional view showing a prior art high-density depletion double diffused drain metal oxide semiconductor (DDDMOS) device. As shown in FIG. 1, a P-type well region is formed in a P-type germanium substrate 1. 11. The insulating structure 12 defines an element region 100, and the insulating structure 12 is, for example, a local oxidation of silicon (LOCOS) structure. In the element region 100, a gate 13, a drift region 14, a source 15a, a drain 15, a body electrode 16, and a threshold voltage adjustment region 17 are formed. Wherein, the P-type well region 11 can be the substrate 1 itself, and the drift region 14, the source 15a, the drain 15 and the threshold voltage adjustment region 17 are defined by lithography techniques, and respectively, by ion implantation technology, N Type impurity, implanted in a defined region in the form of accelerated ions; body 16 is also defined by lithography, and implanted into the defined region by ion implantation in the form of accelerated ions in the form of accelerated ions. Inside. The source 15a and the drain 15 are respectively located below the two sides of the gate 13 , the drift region 14 is located on the drain side and partially below the gate 13 , and the threshold voltage adjustment region 17 is partially located below the gate 13 so that the original is strengthened. The MOS device adjusts its threshold voltage to become a depletion MOS device, and the source 15a and the body electrode 16 are separated by an insulating structure 12. Since the impurity doped by the threshold voltage adjustment region 17 is the same as the drift region 14, both are N-type, and therefore, when the depletion type gold When the oxide semiconductor device is operated, it is more likely to collapse than the reinforced metal oxide semiconductor device, especially in the first figure, the range indicated by the circular dotted line, that is, the gate edge near the drain Below, it is easier to have a band-to-band crash, which reduces the breakdown voltage and limits the application range of the component.

2 is a cross-sectional view showing a prior art high-voltage depletion type lateral diffused metal oxide semiconductor (LDMOS) device. Compared with the prior art of FIG. 1, the high-voltage depletion LDMOS device shown in FIG. There is a body region 18 and a portion of its gate 13 is located on the insulating structure 12. Similarly, the high-voltage depletion LDMOS device shown in this figure has the same problem as the high-voltage depletion DDDMOS device in the range indicated by the circular dotted line in the figure, that is, the band-energy band (band- is more likely to occur). To-band) crashes, reducing the breakdown voltage and limiting the scope of application of the component.

In the past, the method for solving the above problems has focused on adjusting the implantation concentration or diffusion range of the drift region 14, the source 15a, the drain 15, or the threshold voltage adjustment region 17, but it does not effectively solve the problem. For this reason, the circuit does not have a high-voltage depletion-type metal oxide semiconductor device alone, but usually includes a reinforced metal oxide semiconductor device. In the process, the drift region 14, the source 15a, and the drain 15 of the reinforced and depleted components are first fabricated with the same implant parameters, and then the threshold voltage adjustment region 17 of the depletion element is implanted to the component. Transition from a reinforced component to a depleted component. In other words, the parameters of the drift region 14, the source 15a, and the drain 15 of the reinforced and depleted components in the circuit are common. If the parameters of the vacant component are adjusted, the performance of the reinforced component will be affected. Therefore, the only thing that can be adjusted for making a depleted component is the threshold voltage. The implantation parameters of the entire region 17, but the concentration of the threshold voltage adjustment region 17 must not be too low, otherwise the reinforced component cannot be converted into a depleted component. Therefore, under the above limitations, the prior art cannot solve the problem of band-band collapse as described above.

In view of the above, the present invention is directed to the deficiencies of the prior art described above, and provides a method for manufacturing a high voltage depletion type metal oxide semiconductor device, which can improve the breakdown voltage of the device operation and increase the application range of the device.

SUMMARY OF THE INVENTION An object of the present invention is to provide a method of manufacturing a high voltage depletion type metal oxide semiconductor device.

In order to achieve the above object, the present invention provides a method for fabricating a high voltage depletion metal oxide semiconductor device, comprising: providing a substrate having an upper surface, and forming a first conductive well region and a An insulating structure to define an element region; a drift region and a threshold voltage adjustment region are respectively defined in the device region, and second conductivity type impurities are respectively implanted to form the drift region and the threshold voltage adjustment region under the upper surface Forming a gate in the device region on the upper surface, and a portion of the drift region and a portion of the threshold voltage adjustment region are located under the gate; and forming a source and a drain are different from the gate a side of the upper surface of the upper surface of the component, and the drain is separated from the gate by the drift region. As viewed from above, the source and the drain are respectively connected to the two sides of the threshold voltage adjustment region; In the step of defining the threshold voltage adjustment region, a mask is formed by using a photoresist to shield a portion of the drift region, and a mask region is defined in the threshold voltage adjustment region, so that the second conductive type is implanted. In forming the threshold voltage adjusting region, the shielding region compared to the rest of the threshold voltage adjusting region of a second conductivity type having a low impurity concentration.

In one embodiment, the first conductivity type is a P type, and the second The conductivity type is N type. In another embodiment, the first conductivity type is an N type, and the second conductivity type is a P type.

In one embodiment, the insulating structure can be a regional oxide structure or a shallow trench isolation (STI) structure.

In the above method for manufacturing a depleted metal oxide semiconductor device, the definition of the collapse protection zone can be defined by a dedicated photomask.

In one embodiment, the high voltage depletion metal oxide semiconductor device is a double diffused drain metal oxide semiconductor (DDDMOS) device or a lateral diffused metal oxide semiconductor (lateral diffused metal) Oxide semiconductor, LDMOS) component.

The purpose, technical content, features and effects achieved by the present invention will be more readily understood by the detailed description of the embodiments.

The drawings in the present invention are schematic and are mainly intended to represent the process steps and the relationship between the layers, and the shapes, thicknesses, and widths are not drawn to scale.

Referring to the cross-sectional view of FIGS. 3A-3D, a first embodiment of the present invention is shown. This embodiment shows a method of fabricating a high voltage depletion type double diffused drain metal oxide semiconductor device 10. As shown in FIG. 3A, a substrate 1 is first provided, such as but not limited to a P-type or N-type germanium substrate, and then a first conductive type well region 11 and an insulating structure 12 are formed in the substrate 1 to define an element region 100. As shown in the figure, the element region 100 is defined between the insulating structures 12, and the insulating structure 12 may be formed by a region oxidation (LOCOS) or shallow trench isolation (STI) process technology. In the present embodiment, the insulating structure 12 is, for example, For LOCOS structure. In addition, the first conductive type well region 11 may be, but not limited to, the substrate 1 itself, or may be defined by lithography technology, and is doped by ion implantation technology to dope the first conductivity type impurity to the defined region. Next, as shown in FIG. 3B, a drift region 14 is formed in the element region 100, which is defined by lithography technology, and uses an ion implantation technique to deposit a second conductivity type impurity such as, but not limited to, an N-type impurity. In the form of accelerating ions, as indicated by the dashed arrows in the figure, implanted into the defined area.

Next, as shown in FIG. 3C, unlike the prior art, when the threshold voltage adjustment region 17 is formed in the present embodiment, the mask 17a is formed by the photoresist to shield the partial drift region 14 and the threshold voltage adjustment region 17 The masking region 17b is defined, and as indicated by the dashed arrow in FIG. 3C, the second conductivity type impurity, such as, but not limited to, an N-type impurity, is formed by an ion implantation technique so that the threshold voltage adjustment region 17 is formed. The region 17b has a lower second conductivity type impurity concentration than the other portion of the threshold voltage adjustment region 17. The purpose of the mask 17a is to reduce the concentration of the second conductive type impurity in a partial region. As long as the purpose is achieved, the layout pattern is not limited to a single block as shown in FIG. 3C, but may be any other layout. The pattern may be, for example, a multi-dot array, a plurality of strips, a hollow ring shape, or other regular or irregular shapes, as viewed from a top view.

Next, as shown in FIG. 3D, the gate 13 is formed in the element region 100, and the source 15a, the drain 15 and the body pole 16 are completed, that is, the high-voltage depletion type double-diffused gate metal oxide semiconductor device is completed. 10; Among them, the formation method and material of the gate 13 have various methods, which are well known to those skilled in the art, and are not described in detail because they are not the focus of this case. Wherein, from the top view (not shown), the source 15a and the drain 15 are respectively located in the element region 100 below the upper surface 11a of both sides of the threshold voltage adjustment region 17, and the drain 15 and the gate 13 are drifted. Zone 14 is separated by The upper view (not shown) views the source 15a and the drain 15 connected to both sides of the threshold voltage adjustment region 17, respectively. In addition, the body pole 16 is also defined by the lithography technique and implanted into the defined region in the form of accelerated ions by ion implantation techniques, such as, but not limited to, P-type impurities.

Fig. 4 is a view showing another embodiment of the present invention. This embodiment shows a cross-sectional view of the present invention applied to a high-voltage depletion type laterally diffused metal oxide semiconductor device 20, which is manufactured in a manner similar to that of the first embodiment, in this embodiment. The high voltage depletion type laterally diffused metal oxide semiconductor device 20 comprises a substrate 2, a well region 21, an insulating structure 22, a gate 23, a drift region 24, a source 25a, a drain 25, a body electrode 26, a threshold voltage adjustment region 27, With the body area 28. Wherein, in the step of defining the threshold voltage adjustment region, as in the first embodiment, a mask is formed by the photoresist to shield the partial drift region 24, and the mask region 27b is defined in the threshold voltage adjustment region 27 so that the implantation is performed. When the second conductivity type impurity is formed to form the threshold voltage adjustment region 27, the mask region 27b has a lower second conductivity type impurity concentration than the threshold voltage adjustment region 27 of the other portion.

5A-5B are schematic views showing the lateral sum of the second conductivity type impurity concentration from the source to the drain in the prior art and the embodiment of the present invention. Comparing the prior art shown in FIG. 5A with the embodiment of the present invention shown in FIG. 5B, it can be seen that in the embodiment of the present invention, the shielding area indicated by the circular dotted line is summed with the second conductive type impurity. The concentration is lower.

5C-5D is a schematic view showing the concentration of the second conductivity type impurity implanted by the lateral threshold voltage adjustment step from the source to the drain in the prior art and the embodiment of the present invention. Comparing the prior art shown in FIG. 5C with the embodiment of the present invention shown in FIG. 5D, it can be seen that in the embodiment of the present invention, the masking area indicated by the circular dotted line is implanted by the threshold voltage adjusting step. The concentration of the second conductivity type impurity is low.

Fig. 6 is a view showing the characteristic curve of the drain leakage current corresponding to the drain voltage in the case where the high voltage depletion type metal oxide semiconductor device is not turned on in the embodiment of the present invention. Comparing the graphs of the drain leakage current characteristics of the prior art and the embodiments of the present invention, it can be seen that the present invention is superior to the prior art, and the drain leakage current when the components are not turned on is significantly lower than the prior art by applying the embodiment of the present invention. It can also be inferred that the high-voltage depletion type metal oxide semiconductor device to which the present invention is applied has a high non-conduction collapse protection voltage.

The present invention has been described with reference to the preferred embodiments thereof, and the present invention is not intended to limit the scope of the present invention. In the same spirit of the invention, various equivalent changes can be conceived by those skilled in the art. For example, other process steps or structures, such as deep well areas, may be added without affecting the main characteristics of the components; for example, lithography is not limited to reticle technology, and may include electron beam lithography. The above and other equivalent variations are intended to be covered by the scope of the invention.

1,2‧‧‧substrate

10,20‧‧‧High voltage depletion metal oxide semiconductor components

11,21‧‧‧First Conductive Well Area

11a‧‧‧ upper surface

12,22‧‧‧Insulation structure

13,23‧‧‧ gate

14,24‧‧‧ drift zone

15,25‧‧‧汲

15a, 25a‧‧‧ source

16,26‧‧‧ body pole

17,27‧‧‧critical voltage adjustment zone

17a‧‧‧ mask

17b, 27b‧‧‧ shaded area

18, 28‧‧‧ body area

100‧‧‧Component area

Figure 1 shows a cross-sectional view of a prior art high voltage double diffused drain metal oxide semiconductor device.

Figure 2 shows a cross-sectional view of a prior art high pressure lateral diffusing element.

A cross-sectional view of Figures 3A-3D shows a first embodiment of the present invention.

Figure 4 shows another embodiment of the invention.

5A-5B are schematic views showing the lateral sum and second conductivity type impurity concentrations of the prior art and embodiments of the present invention.

5C-5D is a schematic view showing the concentration of the second conductivity type impurity implanted in the lateral threshold voltage adjustment step of the prior art and the embodiment of the present invention.

Figure 6 shows the prior art and application of the embodiment of the present invention, the drain leakage current Schematic diagram of the characteristic curve.

1‧‧‧Substrate

10‧‧‧High-voltage depletion metal oxide semiconductor components

11‧‧‧First Conductive Well Area

11a‧‧‧ upper surface

12‧‧‧Insulation structure

13‧‧‧ gate

14‧‧‧Drift area

15‧‧‧汲polar

15a‧‧‧ source

16‧‧‧ body pole

17‧‧‧critical voltage adjustment zone

17b‧‧‧shadow area

100‧‧‧Component area

Claims (7)

A method for fabricating a high-voltage depletion type metal oxide semiconductor device, comprising: providing a substrate having an upper surface, and forming a first conductive type well region and an insulating structure in the substrate to define an element region; A drift region and a threshold voltage adjustment region are respectively defined in the region, and second conductivity type impurities are respectively implanted to form the drift region and the threshold voltage adjustment region under the upper surface; and a gate is formed in the device region Is located on the upper surface, and a portion of the drift region and a portion of the threshold voltage adjustment region are located under the gate; and a source region is formed in a lower region of the upper surface of the source and a gate on a different side of the gate. And the drain and the gate are separated by the drift region, and the source and the drain are respectively connected to the two sides of the threshold voltage adjustment region; wherein, in the step of defining the threshold voltage adjustment region, Forming a mask with a photoresist to shield a portion of the drift region, and defining a mask region in the threshold voltage adjustment region such that when the second conductivity type impurity is implanted to form the threshold voltage adjustment region, Masking threshold adjustment region compared to other parts of the region of the second conductivity type having a low impurity concentration. The method for manufacturing a high voltage depletion metal oxide semiconductor device according to claim 1, wherein a part of the shielding region is located under the gate. The method of manufacturing a high-voltage depletion type metal oxide semiconductor device according to claim 1, wherein the first conductivity type is a P type and the second conductivity type is an N type. The method of manufacturing a high-voltage depletion type metal oxide semiconductor device according to claim 1, wherein the first conductivity type is an N type and the second conductivity type is a P type. High pressure depleted metal oxide semiconductor as described in claim 1 A method of manufacturing a body member, wherein the insulating structure is a region oxide structure or a shallow trench insulation structure. The method for manufacturing a high-voltage depletion type metal oxide semiconductor device according to claim 1, wherein the definition of the masking region is defined by a dedicated mask. The method for manufacturing a high voltage depletion metal oxide semiconductor device according to claim 1, wherein the depleted metal oxide semiconductor device is a double diffused drain metal oxide semiconductor (DDDMOS). a component or a lateral diffused metal oxide semiconductor (LDMOS) device.