TWI484631B - Double diffused metal oxide semiconductor device and manufacturing method thereof - Google Patents

Description

Double-diffused metal oxide semiconductor device and method of manufacturing same

The present invention relates to a double diffused metal oxide semiconductor (DMOS) device and a method of fabricating the same, and more particularly to a DMOS device for enhancing a breakdown protection voltage and a method of fabricating the same.

1A and 1B are respectively a cross-sectional view and a perspective view of a double diffused metal oxide semiconductor (DMOS) device 100 of the prior art. As shown in FIGS. 1A and 1B, the P-type substrate 11 has a plurality of isolations. The region 12 is defined to define an element region of the DMOS device 100. The isolation region 12 and the field oxide region 12a are, for example, a shallow trench isolation (STI) structure or a local oxidation of silicon (LOCOS) as shown. structure. The DMOS device 100 includes an N-type well region 14, a gate 13, a drain 15, a source 16, a body region 17, a body electrode 17a, and a field oxide region 12a. Wherein, the N-type well region 14, the drain electrode 15 and the source electrode 16 are masked by lithography techniques or with some or all of the gate electrodes 13 to define various regions, and the N-type impurities are respectively implanted by ion implantation techniques. , in the form of accelerated ions, implanted within defined areas. Wherein, the drain 15 and the source 16 are respectively located below the two sides of the gate 13; the body region 17 and the body pole 17a are masked by lithography or with some or all of the gates 13 to define regions and respectively P-type impurities are implanted into defined regions in the form of accelerated ions by ion implantation techniques. Further, in the DMOS device, a part of the gate 13 is located on the field oxide region 12a. DMOS components are high voltage components, that is, they are designed to supply higher operating voltages, but when DMOS components need to be integrated with components with lower operating voltages. On the same substrate, in order to match the component process with lower operating voltage, it is necessary to fabricate DMOS components and low-voltage components with the same ion implantation parameters, or to fabricate high-voltage DMOS components in non-epitaxial silicon. On the substrate, the ion implantation parameters or component quality of the DMOS device are limited, thereby reducing the DMOS component collapse protection voltage and limiting the application range of the component. If the DMOS component collapse protection voltage is not sacrificed, the process steps must be added, and the DMOS components should be fabricated separately with different ion implantation parameters, or as typical high voltage components, all components can be fabricated on epitaxial silicon. In the substrate, but this will increase the manufacturing cost to achieve the desired collapse protection voltage.

In view of the above, the present invention is directed to the above-mentioned deficiencies of the prior art, and proposes a DMOS device and a manufacturing method thereof, and in the case of adding a small number of low-cost process steps, and using a cheaper non-excipherated germanium substrate, the component can be improved. The crash protection voltage of the operation increases the application range of the component and can be integrated into the process of the low voltage component.

It is an object of the present invention to provide a DMOS device and a method of fabricating the same.

In order to achieve the above object, the present invention provides a DMOS device comprising: a first conductive type substrate having an upper surface; and a second conductive type high voltage well region formed in the substrate under the upper surface; a first conductive type deep buried region is formed below the high voltage well region, and the distance from the high pressure well interval is not less than a predetermined interval; an oxidation zone is formed on the upper surface, which is viewed from a top view, a field oxide region is located in the high voltage well region; a first conductive type body region is formed in the substrate under the upper surface; a gate is formed on the upper surface, and a portion of the gate is located on the field oxide region; And a second conductivity type source, And a second conductive type drain, respectively formed under the upper surface of the gate electrode, and viewed from a top view, the drain and the source are separated from the field oxide region by the gate, wherein the gate A pole is formed in the high voltage well region and the source is located in the body region.

In another aspect, the present invention also provides a method for fabricating a DMOS device, comprising: providing a first conductive type substrate having an upper surface; forming a substrate of a second conductive type high voltage well region under the upper surface Forming a first conductive type deep buried area below the high pressure well area and not less than a predetermined distance from the high pressure well section; forming an oxidation zone on the upper surface, as viewed from a top view, a field oxide region is located in the high voltage well region; a first conductive type body region is formed in the substrate below the upper surface; a gate is formed on the upper surface, and a portion of the gate is located on the field oxide region; and respectively formed a second conductive type source and a second conductive type drain are disposed below the upper surface of the gate, and viewed from a top view, the drain and the source are separated from the field by the gate Wherein the drain is formed in the high voltage well region and the source is located in the body region.

In one embodiment, the predetermined spacing is preferably 1.5 microns.

In another embodiment, at least a portion of the body region may be separated from the substrate by the high voltage well region such that the body region is not directly electrically connected to the substrate; or at least a portion of the body region may be coupled to the substrate Alternatively, the substrate may be connected via a first conductivity type connection well region to electrically connect the body region to the substrate.

In yet another embodiment, the deep buried region is viewed from a top view and preferably between the source and the drain.

In still another embodiment, the deep buried region may include a plurality of sub-buried regions, and the plurality of deep buried regions are viewed from a top view and arranged in a parallel strip or matrix manner.

The purpose, technical content, features and effects achieved by the present invention will be more readily understood by the detailed description of the embodiments.

The drawings in the present invention are schematic and are mainly intended to represent the process steps and the relationship between the layers, and the shapes, thicknesses, and widths are not drawn to scale.

Referring to Figures 2A-2D, a first embodiment of the present invention is shown. This embodiment shows a schematic diagram of a method of fabricating a DMOS device 200 to which the present invention is applied. First, as shown in FIG. 2A, a substrate 21 having an upper surface 21a is provided, and the conductivity type of the substrate 21 is, for example, P-type but not limited to being P-type (it may be N-type in other embodiments); The substrate 21 may be, for example, a non-excipherated germanium substrate or an epitaxial substrate. Next, an ion implantation technique is used, for example, but not limited to, an N-type impurity, implanted in the substrate 21 in the form of accelerated ions, and an N-type high-pressure well region 24 is formed under the upper surface 21a. Reusing, for example, but not limited to, lithography, forming photoresist 28a as a mask to define deep buried region 28, and using ion implantation techniques, such as but not limited to P-type impurities, to accelerate the form of ions (as shown) The dotted arrow indicates that, within the defined area of the implant, below the high-pressure well region 24, a P-type deep buried region 28 is formed in the substrate 21, and the above-described process steps of forming the high-pressure well region 24 and the deep buried region 28 are interchangeable. It should be noted that the high-pressure well region 24 and the deep-buried region 28 are formed by different ion implantation process steps, and the distance between the deep-buried region 28 and the high-voltage well region 24 is not less than a preset spacing d, and the preset spacing d is, for example. But not limited to 1.5 microns.

Next, as shown in FIG. 2B, the isolation region 22 and the field oxide region 22a are formed on the upper surface 21a, wherein the isolation region 22 and the field oxide region 22a are, for example, an STI structure or a region-oxidized LOCOS structure as shown in the drawing; Also, the field oxide region 22a can be formed using, but not limited to, the same process steps as the isolation region 22; further, from the top view, FIG. 2D, the isolation region 22 and the field oxide region 22a are located in the high voltage well region 24.

Next, referring to FIG. 2C, a gate 23, a drain 25, a source 26, a body region 27, and a body electrode 27a are formed. Here, as shown, the gate 23 is formed on the upper surface 21a, and a portion of the gate 23 is located on the field oxide region 22a. The drain 25 and the source 26 are, for example, N-type but not limited to the N-type, respectively located below the upper surface 21a of the gate 23, and the drain 25 and the source 26 are separated by the gate 23 (the upper view is not shown in FIG. 2D) 2C is separated from the field oxide region 22a; from the top view 2D, the drain 25 is formed in the high voltage well region 24, and the source 26 is located in the body region 27 (illustrated by the dashed line) )in. The main body region 27 is, for example, a P-type but not limited to a P-type, and is formed in the lower substrate 21 of the upper surface 21a.

Unlike the prior art, in the present embodiment, the deep buried region 28 is formed below the high pressure well region 24. Advantages of this arrangement include: in the component specification, the collapse protection voltage of the DMOS component can be improved; in addition, since the collapse protection voltage of the DMOS component can be improved by the present invention, the impurity concentration of the high voltage well region 24 can be increased, thereby Reduce the on-resistance of the DMOS device.

Fig. 3 shows a second embodiment of the present invention, which is a perspective view of a DMOS device 300 to which the present invention is applied. Different from the first embodiment, in the first embodiment, the body region 27 and the substrate 21 are separated by the high voltage well region 24, so that the body region 27 and the substrate 21 are not electrically connected directly, so that the DMOS device 200 is It can be used as a high side component in a power supply circuit. On the other hand, as shown in Fig. 3, the DMOS device 300 of the present embodiment has an element region defined by the isolation region 32; the DMOS device 300 further includes a field oxide region 32a, a gate 33, a high voltage well region 34, and 汲The pole 35, the source 36, the body region 37, the body pole 37a, and the deep buried region 38. Unlike the first embodiment, in the present embodiment, a portion of the body region 37 is connected to the substrate 31 to electrically connect the body region 37 with the substrate 31, which allows the DMOS device 300 to function as a lower bridge in the power supply circuit ( Low side) component.

Fig. 4 is a perspective view showing a third embodiment of the present invention, which is a DMOS device 400 to which the present invention is applied. As shown, the DMOS device 400 of the present embodiment has an element region defined by the isolation region 42. The DMOS device 400 further includes a field oxide region 42a, a gate 43, a high voltage well region 44, a drain 45, and a source 46. The body region 47, the body pole 47a, and the deep buried region 48. The difference from the second embodiment is that in the embodiment, a portion of the body region 47 and the substrate 41 are connected via the P-type connection well region 49, so that the body region 47 is electrically connected to the substrate 41, which makes the DMOS Element 400 can function as a low side component in a power supply circuit.

In the present invention, by using the deep buried region, a depletion region can be formed in the drift region of the DMOS device from the lower side of the high voltage well region during operation of the DMOS device, especially under the operation of the DMOS device being non-conducting. The lateral depletion region of the DMOS device itself is combined to form a wide range of depletion regions, forming a reduced surface field (RESURF) to suppress the high electric field of the DMOS device during non-conduction operation; Arranging the distance between the deep buried area and the high pressure well area can increase the junction collapse protection voltage. That is to say, with the present invention, the electric field generated by the DMOS device during operation can be reduced, and the component collapse protection voltage can be increased.

Of course, in the method of forming a high-pressure well zone and a deep-buried zone, under the same mask, a high-pressure well zone may be formed first, or a deep-buried zone may be formed first; and the steps of forming a high-pressure well zone and a deep-buried zone may be Before or after the field oxidation zone is formed. The concept of the present invention is not limited to only one method implementation.

Figures 5 and 6 show the fourth and fifth embodiments of the present invention, respectively. These two embodiments show that the deep buried region is viewed from a top view and may include a plurality of sub-buried regions, and the plurality of sub-buried regions are arranged in a parallel strip or matrix. In detail, the DMOS device 500 according to the present invention displays DMOS as shown in FIG. The high voltage well region 54, the isolation region 52, the field oxide region 52a, the drain 55, the source 56, and the plurality of sub-buried regions 58a of the element 500 are schematic views. The plurality of sub-buried regions 58a are arranged in a parallel strip pattern, and it is also within the scope of the present invention to show such an arrangement.

The DMOS device 600 according to the present invention, as shown in Fig. 6, shows the high voltage well region 64, the isolation region 62, the field oxide region 62a, the drain 65, the source 66, and the plurality of sub-buried regions 68a of the DMOS device 600. See the schematic. The plurality of sub-buried regions 68a are arranged in a matrix, and it is also within the scope of the present invention to show such an arrangement.

The present invention has been described with reference to the preferred embodiments thereof, and the present invention is not intended to limit the scope of the present invention. In the same spirit of the invention, various equivalent changes can be conceived by those skilled in the art. For example, other process steps or structures, such as a threshold voltage adjustment region, may be added without affecting the main characteristics of the component; for example, the lithography technique is not limited to the reticle technology, and may include electron beam lithography. The above and other equivalent variations are intended to be covered by the scope of the invention.

11,21,31,41‧‧‧substrate

12,22,32,42,52,62‧‧ ‧Isolation area

12a, 22a, 32a, 42a, 52a, 62a‧‧ ‧ field oxidation zone

13,23,33,43‧‧‧ gate

14‧‧‧ Well Area

15,25,35,45,55,65‧‧‧bungee

16,26,36,46‧‧‧Source

17,27,37,47‧‧‧ body area

17a, 27a, 37a, 47a‧‧‧ body

21a‧‧‧Upper surface

24,34,44,54,64‧‧‧High-pressure well area

28a‧‧‧Light resistance

28,38,48,58,68‧‧‧Deep burial area

100,200,300,400,500,600‧‧‧DMOS components

Figure 1A shows a cross-sectional view of a prior art DMOS device.

Figure 1B shows a perspective view of a prior art DMOS device.

2A-2D shows a first embodiment of the present invention.

Figure 3 shows a second embodiment of the invention.

Fig. 4 shows a third embodiment of the present invention.

Fig. 5 shows a fourth embodiment of the present invention.

Figure 6 shows a fifth embodiment of the present invention.

21‧‧‧Substrate

21a‧‧‧Upper surface

22‧‧‧Insert Area

22a‧‧‧Field Oxidation Zone

23‧‧‧ gate

24‧‧‧High-pressure well area

25‧‧‧汲polar

26‧‧‧ source

27‧‧‧ Body area

27a‧‧‧ body pole

200‧‧‧DMOS components

Claims (10)

A double diffused metal oxide semiconductor (DMOS) device comprising: a P-type substrate having an upper surface; an N-type high voltage well region formed in the substrate under the upper surface; a P-type deep buried region is formed in the substrate below the high-voltage well region, directly connected to the substrate, and the distance from the high-pressure well interval is not less than a predetermined interval; and an oxidation zone is formed on the upper surface Viewed from the top view, the field oxidation zone is located in the high voltage well region; a P-type body region is formed in the substrate below the upper surface; a gate is formed on the upper surface, and a portion of the gate is located The field oxide region; and the N-type source and the N-type drain are respectively formed under the upper surface on both sides of the gate, and viewed from a top view, the drain and the source are connected by the gate The field oxidation zone is separated, wherein the drain is formed in the high voltage well region, and the source is located in the body region; wherein, when the DMOS device is not conducting, a first depletion region is formed in the deep buried region Formed with the high pressure well zone and a second empty zone In the high voltage well region, wherein the first depletion region is connected to the second depletion region; wherein the deep buried region is between the source and the drain. The DMOS device of claim 1, wherein the predetermined pitch is 1.5 microns. The DMOS device of claim 1, wherein the body region and the substrate are separated by the high voltage well region such that the body region is not directly connected to the substrate; or at least part of the body region is Connecting the substrate or connecting the substrate via a P-type connection well region to electrically connect the body region to the substrate Pick up. The DMOS device of claim 1, wherein the deep buried region is viewed from a top view between the source and the drain. The DMOS device of claim 1, wherein the deep buried region comprises a plurality of sub-buried regions, and the plurality of deep buried regions are viewed from a top view and arranged in a parallel strip or matrix manner. A method of manufacturing a double diffused metal oxide semiconductor (DMOS) device, comprising: providing a P-type substrate having an upper surface; forming an N-type high-voltage well region under the upper surface of the substrate Forming a P-type deep buried region in the substrate below the high-voltage well region, directly connected to the substrate, and spaced apart from the high-pressure well interval by a predetermined distance; forming an oxidation zone on the upper surface Viewed from the top view, the field oxide region is located in the high voltage well region; a P-type body region is formed in the substrate below the upper surface; a gate is formed on the upper surface, and a portion of the gate is located in the field oxide And forming an N-type source and an N-type drain under the upper surface on both sides of the gate, and viewed from a top view, the drain and the source are formed by the gate and the field oxide region Separating, wherein the drain is formed in the high voltage well region, and the source is located in the body region; wherein, when the DMOS device is not conducting, a first depletion region is formed in the deep buried region and the high voltage well Between the zones, and a second empty zone is formed between In the high voltage well region, wherein the first depletion region is connected to the second depletion region; wherein the deep buried region is between the source and the drain. The method for manufacturing a DMOS device according to claim 6, wherein The preset spacing is 1.5 microns. The method for fabricating a DMOS device according to claim 6, wherein the body region and the substrate are separated by the high voltage well region such that the body region is not directly connected to the substrate; or at least part of the body The region is connected to the substrate or connected to the substrate via a P-type connection well region to electrically connect the body region to the substrate. The method of fabricating a DMOS device according to claim 6, wherein the deep buried region is viewed from a top view between the source and the drain. The DMOS device manufacturing method according to claim 6, wherein the deep buried region comprises a plurality of sub-buried regions, and the plurality of deep buried regions are viewed from a top view and arranged in a parallel strip or matrix manner.