TWI440184B - High voltage device and manufacturing method thereof - Google Patents

Description

High voltage component and method of manufacturing same

The present invention relates to a high voltage component and a method of manufacturing the same, and more particularly to a high voltage component that can be integrated into a process of a low voltage component and that enhances a breakdown protection voltage and a method of fabricating the same.

1A and 1B are respectively a cross-sectional view and a perspective view of a double diffused drain metal oxide semiconductor (DDDMOS) device of the prior art, as shown in FIGS. 1A and 1B, in the P-type substrate 11. The insulating structure 12 is formed to define an element region 100, such as a shallow trench isolation (STI) structure or a local oxidation of silicon (LOCOS) structure. In the element region 100, a gate 13, a source 14, a drain 15, and a drift region 16 are formed. The source 14, the drain 15 and the drift region 16 are defined by lithography techniques, and the N-type impurities are implanted into the defined region in the form of accelerated ions by ion implantation techniques, respectively. The source 14 and the drain 15 are respectively located below the two sides of the gate 13 , and the drift region 16 is located on the side of the drain 14 and partially below the gate 13 . The DDDMOS component is a high voltage component, that is, it is designed to be used for higher operating voltages, but when the DDDMOS component needs to be integrated on the same substrate as a component with a generally lower operating voltage, it is a component process for a lower operating voltage. The DDDMOS component and the low voltage component need to be fabricated with the same ion implantation parameters, so that the ion implantation parameters of the DDDMOS component are limited, thereby reducing the DDDMOS component breakdown protection voltage and limiting the application range of the component. If the DDDMOS component crash protection voltage is not sacrificed, the process step must be added, and the DDDMOS component is separately fabricated with different ion implantation parameters, but this will increase the manufacturing cost to achieve the desired collapse protection voltage.

In view of the above, the present invention is directed to the above-mentioned deficiencies of the prior art, and provides a high-voltage component and a manufacturing method thereof, which can improve the breakdown protection voltage of the component operation, increase the application range of the component, and can be integrated in the process without increasing the process steps. Process of low voltage components.

It is an object of the present invention to provide a high voltage component and a method of manufacturing the same.

To achieve the above object, the present invention provides a high voltage component comprising: a substrate having an insulating structure to define an element region; a drift region located in the component region, wherein the drift region comprises, viewed from a top view, the drift region comprises a plurality of sub-regions spaced apart from each other, the plurality of sub-regions being electrically coupled to each other; a second conductivity type source and a second conductivity type drain located in the component region; and being located on the surface of the substrate in the component region A gate between the source and the drain.

The high-voltage component may further include a first conductive type well region, the first conductive type well region covering the source, wherein the first conductive type well region and the drift region are located at different positions in a horizontal direction And separated from each other by a distance.

The high voltage component described above may further comprise a buffer zone on both sides of the drain.

In the above high voltage device, the plurality of sub-regions can be electrically coupled to each other by the buffer.

In the above high voltage component, the plurality of sub-regions may be electrically coupled to each other by a bonding region or at least one wire.

In the above high voltage device, the lightly doped drain (LDD) of the drift region and the low voltage component on the same substrate can be fabricated by the same process steps.

In another aspect, the present invention also provides a method of fabricating a high voltage device, comprising: providing a substrate and forming an insulating structure therein to define an element region; forming a drift region in the device region, wherein, by a top view The drift region includes a plurality of sub-regions spaced apart from each other, the plurality of sub-regions being electrically coupled to each other; forming a second conductivity type source and a second conductivity type drain in the device region; and forming the substrate On the surface, in the element region, a gate is formed between the source and the drain.

The purpose, technical content, features and effects achieved by the present invention will be more readily understood by the detailed description of the embodiments.

The drawings in the present invention are schematic and are mainly intended to represent the process steps and the relationship between the layers, and the shapes, thicknesses, and widths are not drawn to scale.

Referring to Figures 2A-2B, a first embodiment of the present invention is shown. Figure 2A shows a perspective view of the present invention applied to a DDDMOS device, and Figure 2B shows a top view of the present invention applied to a DDDMOS device. It should be noted that, in order to show the focus of the invention, the gate 23 is displayed separately from the substrate 21 in FIG. 2A (the gate 23 of the actual element is located immediately on the substrate 21), and the gate 23 is shown in FIG. 2B. Displayed in a semi-transparent manner for easy understanding. As shown in FIG. 2A-2B, in the substrate 21, an insulating structure 22 is formed to define an element region 200, wherein the substrate 21 is, for example, P-type but not limited to a P-type; and the insulating structure 22 is, for example, an STI structure or a region-oxidized LOCOS structure. . In the element region 200, a gate 23, a source electrode 24, a drain electrode 25 and a drift region 26 are formed; wherein the source electrode 24 and the drain electrode 25 are, for example, N-type but not limited to N-type. Unlike the prior art, the drift region 26 (for example, N-type but not limited to the N-type) includes a plurality of sub-regions 26a that are spaced apart from each other to form a fence-like structure as a whole and are buffered by a buffer. The 26b are electrically coupled to each other; the buffer 26b is located on both sides of the drain 25 to prevent direct contact of the drain 25 with the P-type conduction region of the substrate 21 itself. The advantages of this arrangement include: in the component parameters, the collapse protection voltage of the DDDMOS component can be improved; in the process, when the DDDMOS component of the embodiment is integrated into the low-voltage component process, the drift region 26 can be connected to the low-voltage component on the same substrate. The lightly doped drain (LDD) is fabricated in the same process steps, so there is no need to add additional masks or process steps to reduce manufacturing costs.

Referring to FIGS. 3A-3D, a method for integrating the DDDMOS device of the present embodiment into a low voltage device process is shown. The steps are as follows: First, as shown in FIG. 3A, a substrate 21 is provided, and an insulating structure 22 is formed therein to define An element region 200, 300 in which a high voltage DDDMOS device is formed in the element region 200, and a low voltage device is formed in the device region 300; then, as shown in FIG. 3B, an N-type impurity is implanted in the device region 300 by ion implantation to form an impurity. The impurity region 36 is formed by using the light-doped gate 36 of the low-voltage component, and the drift region 26 is simultaneously formed in the device region 200; and then, as shown in FIG. 3C, the ion region is applied to the device region 200, 300. The N-type impurity (N+ type impurity) implanted in the middle forms an N-type source 24, 34 and an N-type drain 25, 35; finally, as shown in FIG. 3D, on the surface of the substrate 21, the element region 200, 300 In the middle, a gate 23 between the source 24 and the drain 25 and a gate 33 between the source 34 and the drain 35 are formed. The structure shown in Fig. 3E is the same as that of Fig. 3D, but in Fig. 3E, in order to show the focus of the invention, the gates 23, 33 are displayed separately from the substrate 21 (the gates 23, 33 in the actual element are located next to the substrate 21). on). It should be noted that the structures shown in FIGS. 3A-3E are only schematic and are not intended to limit the present invention. For example, the number and shape of the sub-regions 26a are not limited to those shown in the drawings, and the shape of the buffer 26b is not Limited to the figure shown.

Fig. 4 shows a second embodiment of the present invention. It is to be noted that in order to show the focus of the invention, the gate 23 is separately shown from the substrate 21 in Fig. 4 (the gate 23 of the actual element is located next to the substrate 21). On) to facilitate understanding. As shown in FIG. 4, in the substrate 21, a P-type well region 27 and an insulating structure 22 are formed to define an element region 200, wherein the P-type well region 27 is, for example, a P-type but not limited to a P-type; and the insulating structure 22 is, for example, The STI structure or region oxidizes the LOCOS structure. In the element region 200, a gate 23, a source electrode 24, a drain electrode 25 and a drift region 26 are formed; wherein the source electrode 24 and the drain electrode 25 are, for example, N-type but not limited to N-type. The main difference between this embodiment and the first embodiment is the P-type well region 27, wherein the P-type well region 27 and the drift region 26 are located at different positions in the horizontal direction and are spaced apart from each other. Compared with the prior art, this embodiment has the same advantages as the first embodiment, and therefore will not be described again.

Figures 5A-5B show a third embodiment of the invention. Fig. 5A is a perspective view showing the present embodiment, and Fig. 5B is a top view showing the present embodiment. It should be noted that, in order to show the focus of the invention, the gate 23 and the substrate 21 are separately displayed in FIG. 5A (the gate 23 of the actual element is immediately on the substrate 21), and the other portion is shown in FIG. 5B. Omitted to facilitate understanding. Different from the first embodiment, the plurality of sub-regions 26a of the embodiment are not electrically coupled to each other by the buffer region 26b, but are electrically coupled to each other by the bonding region 26c. Referring to FIG. 2A-2B, in the 2A-2B and 5A-5B, the buffer 26b is interposed between the substrate 22 and the drain 24 to prevent the substrate 21 from being electrically connected directly to the drain 24. . In the 2A-2B diagram, the buffer 26b also has the function of electrically coupling the plurality of sub-regions 26a to each other; but actually, as shown in FIG. 5A-5B, the plurality of sub-regions 26a are further formed by the connection region 26c. Electrically coupled to each other.

Fig. 6 is a top plan view showing a fourth embodiment of the present invention. It should be noted that in order to show the focus of the invention, the other parts are omitted in FIG. 6 for easy understanding. Different from the first embodiment, the plurality of sub-regions 26a of the embodiment are not electrically coupled to each other by the buffer 26b, but are electrically coupled to each other by the wires 28.

The present invention has been described with reference to the preferred embodiments thereof, and the present invention is not intended to limit the scope of the present invention. In the same spirit of the invention, various equivalent changes can be conceived by those skilled in the art. For example, the sub-region 26a shown in the embodiment has a rectangular strip shape or a block shape, but the sub-region 26a may have other regular shapes such as a circle, an ellipse, a polygon, a zigzag, a wave, a lightning bolt, or an arbitrary irregular shape. For example, other process steps or structures, such as deep well areas, may be added without affecting the main characteristics of the components; for example, lithography is not limited to reticle technology, but may also include electron beam lithography; When the drift region is integrated into the low-voltage component process, it is not limited to the use of the LDD mask and the process, and other masks and processes can be utilized. Of course, a mask and process dedicated to the drift region can also be utilized. The above and other equivalent variations are intended to be covered by the scope of the invention.

11, 21‧‧‧ substrate

21,22‧‧‧Insulation structure

13,23,33‧‧‧ gate

14,24,34‧‧‧ source

15,25,35‧‧‧汲

16,26‧‧‧ drift zone

26a‧‧‧Sub-area

26b‧‧‧buffer

26c‧‧‧ Linked Area

27‧‧‧P type well area

28‧‧‧Wire

36‧‧‧Lightly doped bungee

100,200,300‧‧‧Component area

Figure 1A shows a cross-sectional view of a prior art DDDMOS device.

Figure 1B shows a perspective view of a prior art DDDMOS device.

Fig. 2A-2B shows a first embodiment of the present invention.

Figures 3A-3D show the process steps of the first embodiment of the present invention.

Fig. 3E shows a first embodiment of the present invention.

Figure 4 shows a second embodiment of the invention.

Figures 5A-5B show a third embodiment of the invention.

Fig. 6 shows a fourth embodiment of the present invention.

twenty one. . . Substrate

twenty two. . . Insulation structure

twenty three. . . Gate

twenty four. . . Source

25. . . Bungee

26. . . Drift zone

26a. . . Drift region subregion

26b. . . Buffer

200. . . Component area

Claims (12)

A high voltage component comprising: a substrate having an insulating structure to define an element region; a drift region located in the component region, wherein the drift region includes a plurality of sub-regions spaced apart from each other, as viewed from a top view, a plurality of sub-regions electrically coupled to each other; a source and a drain in the component region; a buffer region on both sides of the drain; and a surface of the substrate, in the component region, between the source and the drain One of the gates. The high voltage component of claim 1, further comprising a well region covering the source and having a conductivity type different from the source. The high voltage component of claim 2, wherein the well zone and the drift zone are at different positions in a horizontal direction and are spaced apart from each other. The high voltage component of claim 1, wherein the plurality of subregions are electrically coupled to each other by the buffer. The high voltage component of claim 1, wherein the plurality of subregions are electrically coupled to each other by a bonding region or at least one wire. The high voltage component of claim 1, wherein the drift region and the lightly doped drain (LDD) of the low voltage component on the same substrate are fabricated in the same process step. A method of manufacturing a high voltage component, comprising: providing a substrate and forming an insulating structure therein to define an element region; forming a drift region in the component region, wherein the drift region comprises a plurality of mutual Separating sub-regions, the plurality of sub-regions being electrically coupled to each other; Forming a source and a drain in the device region; forming a buffer on both sides of the drain; and forming a gate between the source and the drain in the device region on the surface of the substrate. The method of manufacturing a high voltage component according to claim 7, further comprising forming a well region that covers the source and is of a different conductivity type from the source. The method of manufacturing a high voltage component according to claim 8, wherein the well region and the drift region are located at different positions in a horizontal direction and are spaced apart from each other. The method of manufacturing a high voltage component according to claim 7, wherein the plurality of subregions are electrically coupled to each other by the buffer. The method of manufacturing a high voltage component according to claim 7, wherein the plurality of subregions are electrically coupled to each other by a bonding region or at least one wire. The method of manufacturing a high voltage component according to claim 7, wherein the drift region and the lightly doped drain (LDD) of the low voltage component on the same substrate are fabricated in the same process step.