TWI422036B - High voltage device and manufacturing method thereof - Google Patents
High voltage device and manufacturing method thereof Download PDFInfo
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本發明係有關一種高壓元件及其製造方法,特別是指一種利用源極與汲極間之深溝絕緣結構以提高崩潰電壓之高壓元件及其製造方法。The present invention relates to a high voltage component and a method of fabricating the same, and more particularly to a high voltage component utilizing a deep trench isolation structure between a source and a drain to increase a breakdown voltage and a method of fabricating the same.
第1圖顯示一種高壓元件剖視圖,其結構如下。於P型基板11中形成絕緣結構12以定義第一元件區100與第二元件區200,絕緣結構12例如為區域氧化(local oxidation of silicon,LOCOS)結構。於P型基板11上,形成閘極13;於第一元件區100中,形成N型源極14、P型本體極16、與P型本體區17;於第二元件區200中,形成N型汲極15;在源極14與汲極15之間,形成N型井區18。當元件於操作時,往往會耦接至數十至數百伏特的高壓,為提高高壓元件所能承受之高電壓,以增加高壓元件之應用範圍,需要在高壓元件中,降低高電壓所產生的高電場,以提高元件的崩潰電壓。Fig. 1 shows a cross-sectional view of a high voltage element, which is structured as follows. The insulating structure 12 is formed in the P-type substrate 11 to define a first element region 100 and a second element region 200, and the insulating structure 12 is, for example, a local oxidation of silicon (LOCOS) structure. On the P-type substrate 11, a gate 13 is formed; in the first element region 100, an N-type source 14, a P-type body 16 and a P-type body region 17 are formed; and in the second device region 200, a N is formed. The type drain 15; between the source 14 and the drain 15, forms an N-type well region 18. When the component is in operation, it is often coupled to a high voltage of tens to hundreds of volts. In order to increase the high voltage that the high voltage component can withstand, to increase the application range of the high voltage component, it is necessary to reduce the high voltage in the high voltage component. The high electric field to increase the breakdown voltage of the component.
有鑑於此,本發明即針對上述先前技術之不足,提出一種高壓元件及其製造方法,可降低高電壓在元件內部所造成的高電場;或是提高元件操作之崩潰電壓,以增加高壓元件的應用範圍。In view of the above, the present invention is directed to the above-mentioned deficiencies of the prior art, and provides a high voltage component and a manufacturing method thereof, which can reduce a high electric field caused by a high voltage inside the component, or increase a breakdown voltage of the component operation to increase the high voltage component. Application range.
本發明目的在提供一種種高壓元件及其製造方法。It is an object of the present invention to provide a high voltage component and a method of manufacturing the same.
為達上述之目的,本發明提供了一種高壓元件,包含:一第一導電型基板,其具有絕緣結構以定義元件區;一閘極,形成於該第一導電型基板上;一源極與一汲極,形成於該元件區中,具有第二導電型雜質摻雜,分別形成於該閘極兩側;一第二導電型井區,形成於該第一導電型基板中,由上視圖視之,該汲極位於該第二導電型井區中;以及至少一第一深溝絕緣結構,形成於該第一導電型基板中,由上視圖視之,該第一深溝絕緣結構位於該第二導電型井區中,且位於該汲極與源極之間,由剖視圖視之,其深度大於該第二導電型井區。To achieve the above object, the present invention provides a high voltage component comprising: a first conductivity type substrate having an insulating structure to define an element region; a gate formed on the first conductivity type substrate; a source and a drain electrode formed in the element region, having a second conductivity type impurity doped, respectively formed on both sides of the gate; a second conductivity type well region formed in the first conductive type substrate, from a top view </ RTI> the first deep trench isolation structure is formed in the first conductive type substrate, and the first deep trench isolation structure is located in the first conductive type substrate The second conductive type well region is located between the drain and the source, and is deeper than the second conductive type well region by a cross-sectional view.
就另一觀點,本發明也提供了一種高壓元件製造方法,包含:於一第一導電型基板,形成一絕緣結構以定義元件區;形成一閘極於該第一導電型基板上;分別形成一源極與一汲極於該元件區中並設置於該閘極兩側,該源極與汲極具有第二導電型雜質摻雜;形成一第二導電型井區於該第一導電型基板中,由上視圖視之,該汲極位於該第二導電型井區中;以及形成至少一第一深溝絕緣結構於該第一導電型基板中,由上視圖視之,該第一深溝絕緣結構位於該第二導電型井區中,且位於該汲極與源極之間,由剖視圖視之,其深度大於該第二導電型井區。In another aspect, the present invention also provides a method for manufacturing a high voltage device, comprising: forming an insulating structure on a first conductive type substrate to define an element region; forming a gate on the first conductive type substrate; respectively forming a source and a drain are disposed in the component region and disposed on both sides of the gate, the source and the drain have a second conductivity type impurity doping; forming a second conductivity type well region in the first conductivity type In the substrate, viewed from a top view, the drain is located in the second conductive type well region; and at least one first deep trench insulating structure is formed in the first conductive type substrate, which is viewed from a top view, the first deep trench The insulating structure is located in the second conductive type well region and is located between the drain and the source, and is deeper than the second conductive type well region by a cross-sectional view.
上述高壓元件可更包含一第一外圍區,具有第一導電型雜質摻雜,由上視圖視之,該第一外圍區完全或部分包圍該第一深溝絕緣結構,由剖視圖視之,其深度小於該第二導電型井區。The high voltage component may further include a first peripheral region having a first conductivity type impurity doping. The first peripheral region completely or partially surrounds the first deep trench isolation structure from a top view, which is viewed from a cross-sectional view. Less than the second conductivity type well region.
上述高壓元件可更包含一本體區,由上視圖與剖視圖視之,該本體區包覆該源極。The high voltage component may further comprise a body region, which is covered by a top view and a cross-sectional view, the body region covering the source.
上述高壓元件由剖視圖視之,其中該絕緣結構與該閘極可部分重疊,且部分該絕緣結構位於該閘極下方。The high voltage component is viewed from a cross-sectional view, wherein the insulating structure partially overlaps the gate, and a portion of the insulating structure is located below the gate.
上述高壓元件可更包含一第二深溝絕緣結構,形成於該元件區外圍,與該絕緣結構共同定義該元件區。The high voltage component may further comprise a second deep trench isolation structure formed on a periphery of the component region, and the component region is defined together with the insulating structure.
上述高壓元件可更包含一第二外圍區,具有第二導電型雜質摻雜,由上視圖視之,該第二外圍區完全或部分包圍該第一外圍區,由剖視圖視之,其深度小於該第二導電型井區。The high voltage component may further comprise a second peripheral region having a second conductivity type impurity doping, wherein the second peripheral region completely or partially surrounds the first peripheral region, as viewed from a cross-sectional view, the depth is less than The second conductive type well region.
底下藉由具體實施例詳加說明,當更容易瞭解本發明之目的、技術內容、特點及其所達成之功效。The purpose, technical content, features and effects achieved by the present invention will be more readily understood by the detailed description of the embodiments.
本發明中的圖式均屬示意,主要意在表示製程步驟以及各層之間之上下次序關係,至於形狀、厚度與寬度則並未依照比例繪製。The drawings in the present invention are schematic and are mainly intended to represent the process steps and the relationship between the layers, and the shapes, thicknesses, and widths are not drawn to scale.
請參閱第2A與2B圖,顯示本發明的第一個實施例。第2A圖顯示本實施例之上視圖;請同時參閱第2B圖,顯示在第2A圖中,AA’剖線的剖視示意圖。首先,提供第一導電型基板11,其具有絕緣結構12以定義元件區100與200。接著,於第一導電型基板11上,形成閘極13。然後,於第一元件區100中,形成第二導電型源極14、第一導電型本體極16、與第一導電型本體區17。於第二元件區200中,形成第二導電型汲極15。在源極14與汲極15之間,形成第二導電型井區18。於基板11中,形成第一深溝絕緣結構19,由上視圖第2A圖視之,第一深溝絕緣結構19位於第二導電型井區18中,且位於汲極14與源極15之間,由剖視圖第2B圖視之,第一深溝絕緣結構19深度大於第二導電型井區18。其中,由剖視圖第2B圖視之,絕緣結構12與閘極13部分重疊,且部分絕緣結構12位於13閘極下方。由上視圖第2A圖與剖視圖第2B圖視之,本體區17包覆源極14。Referring to Figures 2A and 2B, a first embodiment of the present invention is shown. Fig. 2A shows a top view of the present embodiment; please also refer to Fig. 2B, showing a cross-sectional view taken along line AA' in Fig. 2A. First, a first conductive type substrate 11 having an insulating structure 12 to define the element regions 100 and 200 is provided. Next, a gate 13 is formed on the first conductive substrate 11. Then, in the first element region 100, the second conductive type source 14, the first conductive type body electrode 16, and the first conductive type body region 17 are formed. In the second element region 200, a second conductivity type drain 15 is formed. Between the source 14 and the drain 15, a second conductivity type well region 18 is formed. In the substrate 11, a first deep trench isolation structure 19 is formed. The second deep trench isolation structure 19 is located in the second conductive well region 18 and is located between the drain 14 and the source 15 as viewed from a second view of FIG. As seen in section 2B of the cross-sectional view, the first deep trench isolation structure 19 is deeper than the second conductivity type well region 18. Herein, the insulating structure 12 partially overlaps the gate 13 and the partial insulating structure 12 is located below the 13 gate, as viewed in section 2B of the cross-sectional view. The body region 17 encloses the source 14 from the second view of the top view and the second view of the cross-sectional view.
請參閱第2C與2D圖,解釋第一個實施例如何降低元件內部電場。如第2C圖所示,於PN接面中,例如於N型區域內,形成第一深溝絕緣結構19,且第一深溝絕緣結構19深度較N型區域深。較佳的實施方式,為複數個第一深溝絕緣結構19以垂直於電場方向並相隔適當距離排列,但此僅為較佳而非絕對必要,亦即第一深溝絕緣結構19不必須對齊成為一列,且其間距離不必須為等距關係。請參考第2D圖,顯示PN接面中,電場與位置之關係曲線。如圖所示,未設置第一深溝絕緣結構19之電場與位置關係曲線如圖中之虛線所示,於PN接面附近有電場的相對極大值。圖中的實線顯示具有第一深溝絕緣結構19之電場與位置關係曲線。相對於未設置第一深溝絕緣結構19之電場與位置關係曲線,具有第一深溝絕緣結構19之電場與位置關係曲線明顯將PN接面附近的電場降低。Please refer to Figures 2C and 2D to explain how the first embodiment reduces the internal electric field of the component. As shown in FIG. 2C, in the PN junction, for example, in the N-type region, the first deep trench isolation structure 19 is formed, and the first deep trench isolation structure 19 is deeper than the N-type region. In a preferred embodiment, the plurality of first deep trench isolation structures 19 are arranged perpendicular to the direction of the electric field and at an appropriate distance, but this is only preferred but not absolutely necessary, that is, the first deep trench isolation structures 19 do not have to be aligned into one column. And the distance between them does not have to be equidistant. Please refer to Figure 2D for the relationship between electric field and position in the PN junction. As shown, the electric field versus position curve of the first deep trench isolation structure 19 is not shown, as shown by the dashed line in the figure, and there is a relative maximum value of the electric field near the PN junction. The solid line in the figure shows the electric field versus position curve of the first deep trench isolation structure 19. The electric field versus position curve having the first deep trench isolation structure 19 significantly reduces the electric field near the PN junction relative to the electric field versus position curve in which the first deep trench isolation structure 19 is not disposed.
第3A-3D圖顯示顯示本發明的第二個實施例。第3A圖顯示本實施例之上視圖;而第3B-3D圖顯示本實施例在第3A圖中,BB’剖線的製造流程剖視示意圖。請參閱第3A圖,顯示本實施例與第一個實施例不同之處在於:在第一深溝絕緣結構19的外圍,形成了具有第一導電型雜質摻雜之第一外圍區20。由上視圖第3A圖視之,第一外圍區20可完全包圍第一深溝絕緣結構19(如圖),或僅部分包圍第一深溝絕緣結構19(後者情況下,例如,第一外圍區20可僅包圍第一深溝絕緣結構19的上側、下側、或上下兩側);由剖視圖第3D圖視之視之,第一外圍區20深度小於第二導電型井區18。Figures 3A-3D show a second embodiment showing the invention. Fig. 3A is a top view showing the embodiment; and Fig. 3B-3D is a cross-sectional view showing the manufacturing flow of the BB' line in Fig. 3A of the present embodiment. Referring to FIG. 3A, it is shown that the present embodiment is different from the first embodiment in that a first peripheral region 20 doped with a first conductivity type impurity is formed on the periphery of the first deep trench insulating structure 19. As seen from the top view 3A, the first peripheral region 20 may completely surround the first deep trench isolation structure 19 (as shown) or only partially surround the first deep trench isolation structure 19 (in the latter case, for example, the first peripheral region 20) The upper side, the lower side, or the upper and lower sides of the first deep trench isolation structure 19 may be surrounded only; the first peripheral region 20 is deeper than the second conductive well region 18 as viewed from a 3D view of the cross-sectional view.
請參閱第3B-3D圖之製造流程示意圖。首先提供具有第一導電型基板11,基板11例如但不限於P型基板,並於其中形成第一外圍區20與第一深溝絕緣結構19。接下來,如第3C圖所示,形成絕緣結構12以定義第一元件區100與第二元件區200,以及第二導電型井區18;其中,絕緣結構12例如可為如第3B圖所示之LOCOS結構,亦可為淺溝槽絕緣(shallow trench isolation,STI)結構。Please refer to the schematic diagram of the manufacturing process in Figure 3B-3D. First, a substrate 11 having a first conductivity type, such as, but not limited to, a P-type substrate, is provided, and a first peripheral region 20 and a first deep trench isolation structure 19 are formed therein. Next, as shown in FIG. 3C, the insulating structure 12 is formed to define the first element region 100 and the second element region 200, and the second conductive type well region 18; wherein the insulating structure 12 can be, for example, as shown in FIG. 3B. The LOCOS structure shown may also be a shallow trench isolation (STI) structure.
接下來請繼續參閱第3D圖,於基板11上,形成閘極13。接著,藉由微影技術與閘極13的遮罩,並以離子植入技術,將第一導電型雜質,例如但不限於為P型雜質,以加速離子的形式,植入定義的區域內,以形成本體區17與本體極16。Next, please continue to refer to FIG. 3D to form the gate 13 on the substrate 11. Then, by the lithography technique and the mask of the gate 13 and the ion implantation technique, the first conductivity type impurity, such as but not limited to a P type impurity, is implanted into the defined region in the form of accelerated ions. To form the body region 17 and the body pole 16.
再接下來,藉由微影技術與閘極13的遮罩,並以離子植入技術,將第二導電型雜質,例如但不限於為N型雜質,以加速離子的形式,植入定義的區域內,以形成源極14與汲極16。Next, by lithography and the mask of the gate 13, and by ion implantation technology, the second conductivity type impurities, such as but not limited to N-type impurities, are implanted in the form of accelerated ions. Within the region, a source 14 and a drain 16 are formed.
第4圖顯示本發明的第三個實施例,與第一個實施例不同的是,本實施例應用本發明於另一種高壓元件中,如第4圖所示之橫向雙擴散金屬氧化物半導體(lateral double diffused metal oxide semiconductor,LDMOS)元件。與第一個實施例不同的是,本實施例顯示本發明可以應用於不具有本體區17之LDMOS元件。Figure 4 shows a third embodiment of the present invention. Unlike the first embodiment, this embodiment applies the present invention to another high voltage device, such as the lateral double diffused metal oxide semiconductor shown in Fig. 4. (lateral double diffused metal oxide semiconductor, LDMOS) component. Unlike the first embodiment, this embodiment shows that the present invention can be applied to an LDMOS device having no body region 17.
第5圖顯示本發明的第四個實施例,本實施例與第三個實施例相似,但應用本發明於另一種高壓元件,也就是雙擴散汲極金屬氧化物半導體(double diffused drain metal oxide semiconductor,DDDMOS)之剖視示意圖。與第三個實施例不同的是,本實施例顯示本發明可以應用於閘極13與絕緣結構不相互重疊之DDDMOS元件。其中,絕緣結構12例如可為如第5圖所示之LOCOS結構,亦可為STI結構。Figure 5 shows a fourth embodiment of the present invention, which is similar to the third embodiment, but which is applied to another high voltage component, that is, a double diffused drain metal oxide semiconductor. Schematic diagram of semiconductor, DDDMOS). Different from the third embodiment, this embodiment shows that the present invention can be applied to a DDDMOS device in which the gate 13 and the insulating structure do not overlap each other. The insulating structure 12 may be, for example, a LOCOS structure as shown in FIG. 5 or an STI structure.
第6A與第6B圖顯示本發明的第五個實施例,第6A圖顯示本實施例之上視圖;而第6B圖顯示本實施例在第6A圖中,CC’剖線的剖視示意圖。與第一個實施例不同的是,此高壓元件中,由上視圖第6A圖視之,第一外圍區20僅位於第一深溝絕緣結構19的上下兩側邊,而非完全包圍第一深溝絕緣結構19。由此可知,第一外圍區20亦可以為各種形狀之設計,而不限定於各實施例所示之矩形。6A and 6B show a fifth embodiment of the present invention, and Fig. 6A shows a top view of the present embodiment; and Fig. 6B shows a cross-sectional view of the CC' line of the present embodiment in Fig. 6A. Different from the first embodiment, in the high-voltage component, as seen from the top view 6A, the first peripheral region 20 is located only on the upper and lower sides of the first deep trench isolation structure 19, rather than completely surrounding the first deep trench. Insulation structure 19. It can be seen that the first peripheral region 20 can also be designed in various shapes, and is not limited to the rectangular shape shown in each embodiment.
接下來請參閱第7A與7B圖,顯示本發明的第六個實施例,第7A圖顯示本實施例之上視圖;而第7B圖顯示本實施例在第7A圖中,DD’剖線的剖視示意圖。與第二個實施例不同的是,此高壓元件之閘極13係環狀結構。另外,本實施例意在說明,某些高壓元件具有第二深溝絕緣結構21,形成於元件區100與200外圍,與絕緣結構12共同定義元件區100與200,而本發明可應用於此種具有第二深溝絕緣結構21之高壓元件中。在製程上,第一深溝絕緣結構19可與第二深溝絕緣結構21利用相同的製程步驟形成,而不需要增加步驟。7A and 7B, showing a sixth embodiment of the present invention, FIG. 7A shows a top view of the embodiment; and FIG. 7B shows a DD' line of the present embodiment in FIG. 7A. A schematic cross-sectional view. Unlike the second embodiment, the gate 13 of the high voltage element has a ring structure. In addition, the present embodiment is intended to illustrate that some of the high voltage elements have a second deep trench isolation structure 21 formed on the periphery of the element regions 100 and 200, together with the insulating structure 12 defining the element regions 100 and 200, and the present invention is applicable to such In the high voltage component having the second deep trench insulation structure 21. In the process, the first deep trench isolation structure 19 can be formed using the same process steps as the second deep trench isolation structure 21 without the need for additional steps.
第8A與8B圖顯示本發明的第七個實施例,與第二個實施例不同的是,此高壓元件更包含第二外圍區21,具有第二導電型雜質摻雜,由上視圖第8A圖視之,第二外圍區21可完全包圍第一外圍區20(如圖),或僅部分包圍第一外圍區20(例如包圍其上側、下側、或上下兩側)。由剖視圖第8B圖視之,第二外圍區21深度小於第二導電型井區18。8A and 8B show a seventh embodiment of the present invention. Unlike the second embodiment, the high voltage device further includes a second peripheral region 21 having a second conductivity type impurity doping, which is viewed from the top view. As a matter of view, the second peripheral region 21 may completely surround the first peripheral region 20 (as shown) or may only partially surround the first peripheral region 20 (eg, surrounding its upper side, lower side, or upper and lower sides). As seen in section 8B of the cross-sectional view, the second peripheral region 21 is deeper than the second conductive well region 18.
以上已針對較佳實施例來說明本發明,唯以上所述者,僅係為使熟悉本技術者易於了解本發明的內容而已,並非用來限定本發明之權利範圍。在本發明之相同精神下,熟悉本技術者可以思及各種等效變化。例如,在不影響元件主要的特性下,可加入其他製程步驟或結構,如深井區等;又如,微影技術並不限於光罩技術,亦可包含電子束微影技術;再如,本發明亦可以應用於對稱型之高壓元件,只要將相關之其他區,例如第二導電型井區18等作相對設置即可,並可相對設置第一深溝絕緣結構19、第一外圍區20、與第二外圍區21等;再如,各實施例所述之高壓元件製造方法流程,其步驟順序亦可以改變或互換,只要考量相對關係與熱預算等。本發明的範圍應涵蓋上述及其他所有等效變化。The present invention has been described with reference to the preferred embodiments thereof, and the present invention is not intended to limit the scope of the present invention. In the same spirit of the invention, various equivalent changes can be conceived by those skilled in the art. For example, other process steps or structures, such as deep well areas, may be added without affecting the main characteristics of the components; for example, lithography is not limited to reticle technology, and may also include electron beam lithography; The invention can also be applied to a symmetrical high-voltage component, as long as the other regions, such as the second conductive well region 18, are disposed oppositely, and the first deep trench isolation structure 19, the first peripheral region 20, For example, in the flow of the high-voltage component manufacturing method described in the embodiments, the order of the steps may be changed or interchanged, as long as the relative relationship and the thermal budget are considered. The above and other equivalent variations are intended to be covered by the scope of the invention.
11...基板11. . . Substrate
12...絕緣結構12. . . Insulation structure
13...閘極13. . . Gate
14...源極14. . . Source
15...汲極15. . . Bungee
16...本體極16. . . Body pole
17...本體區17. . . Body area
18...第二導電型井區18. . . Second conductivity type well area
19...第一深溝絕緣結構19. . . First deep trench insulation structure
20...第一外圍區20. . . First peripheral area
21...第二深溝絕緣結構twenty one. . . Second deep trench insulation structure
22...第二外圍區twenty two. . . Second peripheral zone
100,200...元件區100,200. . . Component area
第1圖顯示一種高壓元件剖視圖。Figure 1 shows a cross-sectional view of a high voltage component.
第2A與2B圖顯示本發明的第一個實施例。Figures 2A and 2B show a first embodiment of the present invention.
第2C與2D圖,解釋第一個實施例如何降低元件內部電場。The 2C and 2D diagrams explain how the first embodiment reduces the internal electric field of the component.
第3A-3D圖顯示顯示本發明的第二個實施例。Figures 3A-3D show a second embodiment showing the invention.
第4圖顯示本發明的第三個實施例。Fig. 4 shows a third embodiment of the present invention.
第5圖顯示本發明的第四個實施例。Fig. 5 shows a fourth embodiment of the present invention.
第6A與第6B圖顯示本發明的第五個實施例。Figures 6A and 6B show a fifth embodiment of the present invention.
第7A與7B圖,顯示本發明的第六個實施例。Figures 7A and 7B show a sixth embodiment of the present invention.
第8A與8B圖顯示本發明的第七個實施例Figures 8A and 8B show a seventh embodiment of the present invention
11...基板11. . . Substrate
12...絕緣結構12. . . Insulation structure
13...閘極13. . . Gate
14...源極14. . . Source
15...汲極15. . . Bungee
16...本體極16. . . Body pole
17...本體區17. . . Body area
18...第二導電型井區18. . . Second conductivity type well area
19...第一深溝絕緣結構19. . . First deep trench insulation structure
Claims (10)
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US20020185705A1 (en) * | 2001-06-11 | 2002-12-12 | Wataru Saitoh | Power semiconductor device having RESURF layer |
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US20020185705A1 (en) * | 2001-06-11 | 2002-12-12 | Wataru Saitoh | Power semiconductor device having RESURF layer |
TW201003917A (en) * | 2008-07-09 | 2010-01-16 | Dongbu Hitek Co Ltd | Lateral double diffused metal oxide semiconductor (LDMOS) device and manufacturing method of LDMOS device |
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