201234590 六、發明說明： 【發明所屬之技術領域】 本發明係有關一種高壓元件及其製造方法，特別是指一種 利用源極與沒極間之深溝絕緣結構以提高崩潰電壓之高壓元 件及其製造方法。 【先前技術】 第1圖顯示一種局壓元件剖視圖’其結構如下。於p型基 板11中形成絕緣結構12以定義第一元件區1 〇〇與第二元件 區200 ’絕緣結構12例如為區域氧化（i〇cai 〇xidati〇n 〇f silicon，LOCOS)結構。於P型基板11上，形成閉極13 ;於 第一元件區100中，形成N型源極14、P型本體極16、與p 型本體區17 ’於第二元件區200中’形成n型汲極15 ;在 源極14與沒極15之間，形成N型井區18。當元件於操作時， 往往會耦接至數十至數百伏特的高壓，為提高高壓元件所能 承受之高電壓，以增加高壓元件之應用範圍，需要在高壓元 件中，降低高電壓所產生的高電場，以提高元件的崩潰電壓。 有鑑於此，本發明即針對上述先前技術之不足，提出一種 高壓元件及其製造方法，可降低高電壓在元件_所造成的高 電場；或是提高元件操作之崩潰電壓，以增加高壓元件的應用 範圍。 。 【發明内容】 本發明目的在提供一種種高壓元件及其製造方法。 為達上述之目的，本發明提供了一種高壓元件，包含： 一第-導電型基板’其具有絕緣結構以定義元件區；一閑極， 201234590 形成於該第-導電型基板上；—源極與—祕，形成於該元 件區中，具有第二導電型雜質摻雜，分別形成於該閘極兩側； -第二導電型井區，形成於該第一導電型基板中由上視圖 視之，該汲極位於該第二導電型井區中；以及至少一第一深溝 絕緣結構，職於該第-導電縣板巾，由上棚視之，該第 -深溝絕緣結構位於該第二導電型井區中，且位於該沒極與源 極之間’由剖視圖視之，其深度大於該第二導電型井區。 就另一觀點，本發明也提供了一種高壓元件製造方法， 包含：於H電型基板，形成—絕緣結構以定義元件區； 形成-閘極於該第-導電型基板上；分別形成―源極與一沒 極於該元件區中並設置於該閘極兩側，該源極與汲極具有第二 導電型雜質摻雜；形成-第二導電型井區於該第—導電型基 板中，由上視圖視之，該没極位於該第二導電型井區中；以及 形成至少一第一深溝絕緣結構於該第一導電型基板中，由上視 圖視之’該第一深溝絕緣結構位於該第二導電型井區中，且位 於該汲極與源極之間，由剖視圖視之，其深度大於該第二導電 型井區。 、 一 上述咼壓元件可更包含一第一外圍區，具有第一導電型 雜質摻雜，由上視圖視之，該第-外，完全或部分包圍該 第一深溝絕緣結構，由剖視圖視之，其深度小於該第二 井區。 上述冋壓元件可更包含-本體區，由上視圖與剖視圖視 之，該本體區包覆該源極。 上述高壓元件由剖視圖視之，其中該絕緣結構與該閘極 可部分重疊，且部分該絕緣結構位於該閘極下方。、 上述高壓元件可更包含-第二深溝絕緣結構，形成於該 201234590 元件區外圍，與該絕緣結構共同定義該元件區。 上述高壓元件可更包含一第二外圍區，具有第二導電型 雜質摻雜，由上視圖視之，該第二外圍區完全或部分包圍該 第一外圍區’由剖視圖視之，其深度小於該第二導電型井區。 底下藉由具體實施例詳加說明，當更容易瞭解本發明之 目的、技術内容、特點及其所達成之功效。 【實施方式】 本發明中的圖式均屬示意，主要意在表示製程步驟以及各 層之間之上下次序關係，至於形狀、厚度與寬度則並未依照比 例繪製。 請參閱第2A與2B圖，顯示本發明的第一個實施例。第 2A圖顯示本實施例之上視圖；請同時參閱第2B圖，顯示在 第2A圖中，AA’剖線的剖視示意圖。首先，提供第一導電 型基板11，其具有絕緣結構12以定義元件區1〇〇與2〇〇。接 著，於第一導電型基板11上，形成閘極13。然後，於第一 元件區100中，形成第二導電型源極14、第一導電型本體極 16、與第一導電型本體區17 ^於第二元件區2〇〇中，形成第 二導電型汲極15。在源極14與汲極15之間，形成第二導電 型井區18。於基板11中’形成第一深溝絕緣結構]9，由上 視圖第2A圖視之，第一深溝絕緣結構19位於第二導電型井 區18中’且位於汲極14與源極15之間，由剖視圖第2B圖 視之，第一深溝絕緣結構19深度大於第二導電型井區18。其 中，由剖視圖第2B圖視之’絕緣結構12與閘極π部分重疊， 且部分絕緣結構12位於13閘極下方。由上視圖第2A圖與剖 視圖第2B圖視之，本體區17包覆源極14。 201234590 請參閱第2C與2D ϋ，解釋第一個實施例如何降低元 件内部電場。如第2C圖所示，於ρΝ接面中，例如於㈣ =域内’形成[深溝絕緣結構19，且第—深溝絕緣結構19 冰度較Ν魏域深。較佳的實施方式，域數 緣結構19以垂直於電場方向並憾適當距離·，但此|為 較^而非絕對必要’亦即第-深溝絕緣結構19不必須對齊成 列’且其間距離不必須為等距關係。請參考第2d圖臂 示PN接面中，電場與位置之關係曲線。如圖所示，未設置第 冰溝絕緣、、、。構I9之電場與位置關係曲線如圖中之虛線所 示，於PN接面附近有電場的相對極大值。圖中的實線顯示具 有第-深溝絕緣結構19之電場與位置_曲線。相對於未設 置第-深溝絕緣結構19之電場與位置_曲線，具有第一深 溝絕緣結構19之電場與位置關係曲線明顯將PN接面附近的 電場降低。 第3A-3D ®顯示顯示本發明的第二個實施例。第3八圖顯 示本實施例之上視圖；而第犯_犯_示本實施例在第3A圖 中，BB剖線的製造流程剖視示意圖。請參閱第圖，顯示 本實施例與第—個實__之處在m深溝絕緣結構 19的外圍，形成了具有第—導電型雜f摻雜之第一外圍區 20。由上視圖第3A圖視之，第一外圍區2〇可完全包圍第一 深溝絕緣結構19(如圖），或僅部分包圍第—深溝絕緣結構 賺者情況下’例如，第-外圍區2()可僅包圍第—深溝絕緣 結構19的上側、下側、或上下兩側）；由剖視圖第沁圖视之 視之’第-外圍區2G ;罙度小於第二導電型井區18。 請參閱第3B_3D圖之製造流程示意圖。首先提供具有 第-導電型基板1卜基板11例如但不限於p型基板，並於 201234590 其中形成第-外圍區20與第一深溝絕緣結構19。接下來如 第咒圖所示，形成絕緣結構12以定義第一元件區觸與第 -兀件區200，以及第二導電型井區18 ;其中絕緣結構 例如可為如第3Β _示之L〇c〇s結構，亦可為淺溝槽絕 緣(shallow trench isolation，STI)纟士構 接下來請繼續參閱第3D ®，於基板11上，形成閘極 13。接著，藉由微影技術與_ 13的遮罩，並以離子植入 技術’將第-導電型雜質，例如但不限於為ρ型雜質，以加 • 速離子的形式’植入定義的區域内，以形成本體區η與本體 極16 〇 再接下來，藉由微影技術與閘極13的遮罩，並以離子 植入技術，將第二導電型雜質，例如但不限於為雜質， 以加速離子的形式，植入定義的區域内，以形成源極14與汲 極16。 第4圖顯示本發明的第三個實施例，與第一個實施例不 同的是，本實施例應用本發明於另一種高壓元件中，如第4 圖所示之橫向雙擴散金屬氧化物半導體(lateral double diffused metal oxide semiconductor，LDMOS)元件。與第一個實施例不 同的是，本實施例顯示本發明可以應用於不具有本體區17 之LDM0S元件。 .第5圖顯示本發明的第四個實施例，本實施例與第三個 實施例相似’但應用本發明於另一種高壓元件，也就是雙擴散 沒極金屬氧化物半導體(double diffused drain metal oxide semiconductor, DDDMOS)之剖視示意圖。與第三個實施例不 同的是，本實施例顯示本發明可以應用於閘極13與絕緣結構 不相互重疊之DDDMOS元件。其中，絕緣結構12例如可為 201234590 如第5圖所示之LOCOS結構，亦可為STI結構。 第6A與第6B圖顯示本發明的第五個實施例，第6A圖 顯示本實施例之上視圖；而第6B圖顯示本實施例在第6A圖 中，CC’剖線的剖視示意圖。與第一個實施例不同的是，此 咼壓元件中，由上視圖第6A圖視之，第一外圍區20僅位於 第一丨木溝絕緣結構19的上下兩側邊，而非完全包圍第一深溝 絕緣結構19。由此可知，第一外圍區2〇亦可以為各種形狀 之設計，而不限定於各實施例所示之矩形。 接下來請參閱第7A與7B圖，顯示本發明的第六個實 施例，第7A圖顯示本實施例之上視圖；而第7B圖顯示本實 施例在第7A圖中，DD’剖線的剖視示意圖。與第二個實施 例不同的是，此高壓元件之閘極13係環狀結構。另外，本 實施例意在說明，某些高壓元件具有第二深溝絕緣結構21， 形成於元件區100與200外圍，與絕緣結構12共同定義元件 區100與200 ’而本發明可應用於此種具有第二深溝絕緣結 構21之高壓元件中。在製程上，第一深溝絕緣結構19可與 第二深溝絕緣結構21利用相同的製程步驟形成，而不需要增 加步驟。 3 第8A與8B圖顯示本發明的第七個實施例，與第二個 實施例不同的是，此高壓元件更包含第二外圍區21，具有第 二導電型雜質摻雜，由上視圖第8A圖視之，第二外圍區21 可完全包圍第-外圍區2〇(如圖或僅部分包圍第一外圍區 20(例如包圍其上側、下側、或上下兩側）。由剖視圖第犯圖 視之，第二外圍區21深度小於第二導電型井區18。 以上已針對較佳實施例來說明本發明，唯以上所述者， 僅係為使熟悉本技術者易於了解本發明的内容而已，並非用 201234590201234590 VI. Description of the Invention: [Technical Field] The present invention relates to a high voltage component and a method of fabricating the same, and more particularly to a high voltage component utilizing a deep trench isolation structure between a source and a pole to increase a breakdown voltage and manufacturing thereof method. [Prior Art] Fig. 1 shows a cross-sectional view of a local pressure element' whose structure is as follows. The insulating structure 12 is formed in the p-type substrate 11 to define the first element region 1 and the second element region 200'. The insulating structure 12 is, for example, a region oxide (LOCOS) structure. On the P-type substrate 11, a closed pole 13 is formed; in the first element region 100, an N-type source 14 is formed, a P-type body pole 16 is formed, and a p-type body region 17' is formed in the second element region 200. Type drain 15; between the source 14 and the pole 15 forms an N-type well region 18. When the component is in operation, it is often coupled to a high voltage of tens to hundreds of volts. In order to increase the high voltage that the high voltage component can withstand, to increase the application range of the high voltage component, it is necessary to reduce the high voltage in the high voltage component. The high electric field to increase the breakdown voltage of the component. In view of the above, the present invention is directed to the above-mentioned deficiencies of the prior art, and provides a high voltage component and a manufacturing method thereof, which can reduce a high electric field caused by a high voltage in the component _ or increase a breakdown voltage of the component operation to increase the high voltage component. Application range. . SUMMARY OF THE INVENTION An object of the present invention is to provide a high voltage element and a method of manufacturing the same. In order to achieve the above object, the present invention provides a high voltage device comprising: a first conductivity type substrate having an insulating structure to define an element region; a dummy electrode, 201234590 formed on the first conductivity type substrate; Formed in the element region, having a second conductivity type impurity doping, respectively formed on both sides of the gate; - a second conductivity type well region formed in the first conductivity type substrate from a top view The bungee is located in the second conductive type well region; and at least one first deep trench insulation structure is disposed in the first conductive county plate, as viewed from the upper shelf, the first deep trench insulating structure is located in the second conductive In the well zone, and between the pole and the source, the depth is greater than the second conductivity type well region. In another aspect, the present invention also provides a method for manufacturing a high voltage device, comprising: forming an insulating structure to define an element region on an H type substrate; forming a gate on the first conductive substrate; respectively forming a source a pole and a pole are not disposed in the component region and are disposed on both sides of the gate, the source and the drain have a second conductivity type impurity doping; forming a second conductivity type well region in the first conductivity type substrate Viewing from the top view, the pole is located in the second conductive type well region; and forming at least one first deep trench insulation structure in the first conductive type substrate, which is viewed from a top view as the first deep trench isolation structure It is located in the second conductive type well region and is located between the drain and the source, and is deeper than the second conductive type well region by a cross-sectional view. The above-mentioned rolling element may further comprise a first peripheral region having a first conductivity type impurity doping, which is viewed from a top view, the first outer portion completely or partially surrounding the first deep trench insulating structure, which is viewed from a cross-sectional view , the depth is less than the second well area. The stamping element may further comprise a body region which is covered by a top view and a cross-sectional view, the body region encasing the source. The high voltage component is viewed from a cross-sectional view, wherein the insulating structure partially overlaps the gate and a portion of the insulating structure is located below the gate. The high voltage component may further include a second deep trench isolation structure formed on a periphery of the 201234590 component region, and the component region is defined together with the insulating structure. The high voltage component may further comprise a second peripheral region, having a second conductivity type impurity doping, which is viewed from a top view, the second peripheral region completely or partially surrounding the first peripheral region 'as viewed from a cross-sectional view, the depth is less than The second conductive type well region. The purpose, technical contents, features and effects achieved by the present invention will be more readily understood by the detailed description of the embodiments. [Embodiment] The drawings in the present invention are schematic, mainly intended to indicate the process steps and the relationship between the layers, and the shape, thickness and width are not drawn in proportion. Referring to Figures 2A and 2B, a first embodiment of the present invention is shown. Fig. 2A shows a top view of the present embodiment; please also refer to Fig. 2B, which shows a cross-sectional view taken along line AA' of Fig. 2A. First, a first conductive type substrate 11 having an insulating structure 12 to define element regions 1 and 2 is provided. Next, a gate 13 is formed on the first conductive substrate 11. Then, in the first device region 100, the second conductive type source 14, the first conductive type body electrode 16, and the first conductive type body region 17 are formed in the second element region 2, to form a second conductive Type bungee 15. Between the source 14 and the drain 15, a second conductive well region 18 is formed. Forming a first deep trench isolation structure 9 in the substrate 11, as viewed from the top view 2A, the first deep trench isolation structure 19 is located in the second conductive well region 18 and located between the drain 14 and the source 15 As seen from the cross-sectional view of FIG. 2B, the first deep trench isolation structure 19 is deeper than the second conductive well region 18. Here, the 'insulating structure 12' is partially overlapped with the gate π by the second view of the cross-sectional view, and the partially insulating structure 12 is located under the 13 gate. The body region 17 encloses the source 14 from the top view 2A and the cross-sectional view 2B. 201234590 See 2C and 2D ϋ to explain how the first embodiment reduces the internal electric field of the component. As shown in Fig. 2C, in the ρ junction, for example, in the (four) = domain, the [deep trench insulation structure 19 is formed, and the first deep trench insulation structure 19 is deeper than the Wei domain. In a preferred embodiment, the domain number edge structure 19 is perpendicular to the direction of the electric field and has a proper distance, but this is more than absolutely necessary, that is, the first deep trench isolation structure 19 does not have to be aligned in a column and the distance therebetween It does not have to be an equidistant relationship. Please refer to Figure 2d for the relationship between electric field and position in the PN junction. As shown in the figure, the ice barrier insulation, , , is not set. The electric field and positional relationship curve of the structure I9 is shown by the dotted line in the figure, and there is a relative maximum value of the electric field near the PN junction. The solid line in the figure shows the electric field and position_curve having the first-deep trench insulation structure 19. The electric field versus position curve having the first deep trench isolation structure 19 significantly reduces the electric field near the PN junction relative to the electric field and position_curve of the first deep trench isolation structure 19. The 3A-3D® display shows a second embodiment of the present invention. Fig. 3 is a top view showing the embodiment; and the first embodiment is a cross-sectional view showing the manufacturing flow of the BB line in the third embodiment. Referring to the figure, the first peripheral region 20 having the first conductivity type impurity f doping is formed on the periphery of the m deep trench isolation structure 19 in this embodiment and the first embodiment. As seen from the top view 3A, the first peripheral region 2〇 may completely surround the first deep trench isolation structure 19 (as shown in the figure), or may only partially surround the first deep trench isolation structure. For example, the first peripheral region 2 () may surround only the upper side, the lower side, or the upper and lower sides of the first deep trench insulating structure 19; and the 'peripheral peripheral region 2G' will be viewed from the cross-sectional view as the second conductive type well region 18. Please refer to the manufacturing process diagram of Figure 3B_3D. First, a substrate having a first-conductivity type substrate 1 such as, but not limited to, a p-type substrate is provided, and a first peripheral region 20 and a first deep trench insulating structure 19 are formed therein in 201234590. Next, as shown in the first graph, the insulating structure 12 is formed to define the first element region contact with the first element region 200, and the second conductive type well region 18; wherein the insulating structure can be, for example, the third layer The structure of the 〇c〇s may also be a shallow trench isolation (STI). Next, please continue to refer to the 3D® to form the gate 13 on the substrate 11. Next, by lithography and _ 13 mask, and by ion implantation technology 'the first conductive type impurities, such as but not limited to p-type impurities, implanted into the defined area in the form of accelerated ions Inside, to form the body region η and the body electrode 16 and then, by the lithography technique and the mask of the gate 13, and by ion implantation technology, the second conductivity type impurities, such as but not limited to impurities, The implanted regions are implanted in the form of accelerated ions to form source 14 and drain 16 . Fig. 4 shows a third embodiment of the present invention. Unlike the first embodiment, this embodiment applies the present invention to another high voltage device, such as the lateral double diffused metal oxide semiconductor shown in Fig. 4. (lateral double diffused metal oxide semiconductor, LDMOS) component. Unlike the first embodiment, this embodiment shows that the present invention can be applied to an LDMOS element having no body region 17. Fig. 5 shows a fourth embodiment of the present invention, which is similar to the third embodiment 'but the invention is applied to another high voltage element, that is, a double diffused drain metal Schematic diagram of oxide semiconductor, DDDMOS). Unlike the third embodiment, this embodiment shows that the present invention can be applied to a DDDMOS device in which the gate 13 and the insulating structure do not overlap each other. The insulating structure 12 can be, for example, a LOCOS structure as shown in FIG. 5 of 201234590, or an STI structure. 6A and 6B show a fifth embodiment of the present invention, and Fig. 6A shows a top view of the present embodiment; and Fig. 6B shows a cross-sectional view of the CC' line taken in Fig. 6A of the present embodiment. Different from the first embodiment, in the rolling element, as seen from the top view 6A, the first peripheral region 20 is located only on the upper and lower sides of the first rafter insulating structure 19, rather than completely surrounding. The first deep trench insulation structure 19. It can be seen that the first peripheral region 2〇 can also be of various shapes and is not limited to the rectangular shape shown in the respective embodiments. 7A and 7B, showing a sixth embodiment of the present invention, FIG. 7A shows a top view of the embodiment; and FIG. 7B shows a DD' line of the present embodiment in FIG. 7A. A schematic cross-sectional view. Unlike the second embodiment, the gate 13 of the high voltage element has a ring structure. In addition, this embodiment is intended to illustrate that some of the high voltage elements have a second deep trench isolation structure 21 formed on the periphery of the element regions 100 and 200, together with the insulating structure 12 defining the element regions 100 and 200' and the present invention is applicable to such In the high voltage component having the second deep trench insulation structure 21. In the process, the first deep trench isolation structure 19 can be formed using the same process steps as the second deep trench isolation structure 21 without the need for an additional step. 3 Figures 8A and 8B show a seventh embodiment of the present invention. Unlike the second embodiment, the high voltage device further includes a second peripheral region 21 having a second conductivity type impurity doping, as viewed from above. 8A, the second peripheral region 21 may completely surround the first peripheral region 2〇 (as shown or only partially surrounding the first peripheral region 20 (eg, surrounding its upper side, lower side, or upper and lower sides). As shown, the second peripheral region 21 is deeper than the second conductive well region 18. The present invention has been described above with respect to the preferred embodiments, but the above is only for those skilled in the art to readily understand the present invention. Content only, not 201234590
來限定本發明之權利。在本發明之減精神下熟悉本 技術者可以思及各種等效變化。例如，在不影響元件主要的 特性下’可加人其他製程步驟或結構，如深井區等；又如， 微影技術並不赚光料術，亦可包含電子束郷技術；再 如，本發明亦可以顧於對_之高壓元件，只要將相關之其 他區’例如第二導電型賴18等作相對設置即可，並可相對 ，置第一深溝絕緣結構19、第一外圍區2〇、與第二外圍區21 等，再如，各實施例所述之高壓元件製造方法流程，其步驟 順序亦^以改變或互換’只要考量減義越預算等。本 發明的範圍應涵蓋上述及其他所有等效變化。 【圖式簡單說明】 第1圖顯示-種高壓元件剖視圖。 第2A與2B圖顯示本發明的第一個實施例。 第C 一 2D圖，解釋第一個實施例如何降低元件内部電場 第3A_3D _示顯示本發明的第三個實施例。 第4圖顯示本發明的第三個實施例。 第5圖顯示本發_第四個實施例。 第6A與第6B圖顯示本發明的第五個實施例。 第 7A 與 7¾ 1¾ θ _ 圑’顯示本發明的第六個實施例。 第 8A 與 8B _ # _ 圖顯不本發明的第七個實施例 【主要元件符_糊】 11基板 14源極 15汲極 16本體極 12絕緣結構 13閘極 201234590 17本體區 18第二導電型井區 19第一深溝絕緣結構 20第一外圍區 21第二深溝絕緣結構 22第二外圍區 100,200元件區The right to the invention is defined. Those skilled in the art can appreciate various equivalent changes in the spirit of the invention. For example, without affecting the main characteristics of the component, other process steps or structures may be added, such as deep well areas; for example, lithography is not a light-emitting technique, and may also include electron beam raft technology; The invention can also take into account the high-voltage components of the _, as long as the other regions associated with each other, such as the second conductivity type 18, can be oppositely disposed, and the first deep trench isolation structure 19 and the first peripheral region 2 can be oppositely disposed. And the second peripheral area 21 and the like, and, for example, the high-voltage component manufacturing method flow described in each embodiment, the order of the steps is also changed or interchanged as long as the budget is reduced and the budget is equal. The above and other equivalent variations are intended to be covered by the scope of the invention. [Simple description of the drawing] Fig. 1 shows a cross-sectional view of a high-voltage element. Figures 2A and 2B show a first embodiment of the present invention. The C-2D diagram explains how the first embodiment reduces the internal electric field of the element. 3A_3D_ shows a third embodiment of the present invention. Fig. 4 shows a third embodiment of the present invention. Fig. 5 shows the fourth embodiment of the present invention. Figures 6A and 6B show a fifth embodiment of the present invention. 7A and 73⁄4 13 θ _ 圑 ' show a sixth embodiment of the present invention. 8A and 8B _ # _ shows a seventh embodiment of the present invention [main component symbol_paste] 11 substrate 14 source 15 drain 16 body 12 insulation structure 13 gate 201234590 17 body region 18 second conductive Type well area 19 first deep trench insulation structure 20 first peripheral area 21 second deep trench insulation structure 22 second peripheral area 100, 200 element area