JP2015153988A - semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device which inhibits insulation breakdown occurring between a surface of an element region and a rear face of a termination region in a semiconductor device and which can achieve high voltage, low on-resistance and improvement in reliability of a gate oxide film.SOLUTION: In a trench MOSFET semiconductor device comprising a gate wiring layer which is connected with a gate electrode embedding part formed in a trench in an element region and lifted up from an upper end of a sidewall of the trench to above a semiconductor substrate, and a trench sidewall upper end corner semiconductor layer which produces enhanced oxidation of an oxide film at a trench sidewall upper end corner which insulates the gate wiring layer, a shape and an arrangement of the trench sidewall upper end corner semiconductor layer is made so as to reduce a hole generated by avalanche of a guard ring trench sidewall of a termination region and a pinch region formed in a transit route of an electron.

Description

The present invention relates to a semiconductor device, and more particularly to a trench MOSFET (Metal Oxide) having a high breakdown voltage and a high breakdown voltage while maintaining a low on-resistance.
Semiconductor Field Effect Transistor) relates to semiconductor devices.

In recent years, trench type MOSFET semiconductor devices are used for high current and high voltage devices. Such trench MOSFET semiconductor devices are strongly required to improve performance such as low voltage driving, low on-resistance, and low switching loss. In particular, for low on-resistance, an improvement in performance is particularly required from the viewpoint of reducing current consumption.
In the trench MOSFET semiconductor device, the main factors governing the on-resistance are the resistance of the channel portion of the second conductivity type base diffusion layer formed in the first conductivity type epitaxial layer, and the first conductivity type. It is the resistance of the drift region provided in the epitaxial layer.
On the other hand, the breakdown voltage between the source and drain of the trench MOSFET semiconductor device is determined by the electric field strength at the main junction of the first conductivity type epitaxial layer and the second conductivity type base layer. For this reason, the breakdown voltage between the source and the drain largely depends on the concentration of the first conductivity type epitaxial layer serving as the drift region.
For these reasons, there is a trade-off relationship between on-resistance and source / drain breakdown voltage.

  It has been proposed to use a guard ring structure in a trench MOSFET semiconductor device in order to increase the epitaxial concentration to lower the on-resistance and to ensure a certain breakdown voltage. In the guard ring structure, the termination trench is provided in the termination region adjacent to the element region in which the MOSFET trench is provided. The depletion layer generated in the main junction of the element region extends to the adjacent termination region beyond the bottom of the MOSFET trench, and the electric field strength of the main junction is relaxed, and a certain breakdown voltage or more can be secured. (See Patent Document 1 and Patent Document 2)

  In order to improve the reliability of the trench MOSFET semiconductor device, it is particularly important to improve the reliability of the gate oxide film. To this end, it is necessary to ensure the breakdown voltage of the oxide film at the upper corner of the inner wall of the trench. Necessary. As a method of ensuring the breakdown voltage of the oxide film at the upper corner of the inner wall of the trench, after etching the trench, chemical dry etching (CDE) is performed to make the trench upper shape an obtuse angle, or after etching the trench, There is a method of preventing the gate oxide film from being thinned at the upper corner of the trench by rounding the upper shape of the trench by high-temperature heat treatment in a hydrogen atmosphere. (See Patent Document 3)

  Also, impurities such as arsenic or phosphorus are ion-implanted in advance into the upper corner of the trench, and accelerated oxidation during gate oxidation is used to prevent the gate oxide film at the upper corner of the trench from becoming thin. A method has been proposed. In this method, by using the ion implantation step as the source formation step, a high oxide film breakdown voltage can be obtained without any special additional step. (See Patent Document 4 and Patent Document 5)

JP 09-283754 A JP2013-066986A JP 2005-142265 A JP-A-63-133664 JP 07-249769 A

In order to solve the contradictory relationship between the on-resistance and the source-drain breakdown voltage, the inventor has improved the breakdown voltage by the trench guard ring structure and the gate oxide film by the accelerated oxidation at the upper corner of the trench sidewall. We studied a semiconductor device that simultaneously improves the reliability of the device. FIG. 5 shows a plan view of an example of a semiconductor device to be examined, FIG. 6 shows a cross section AA ′ of FIG. 5, and FIG. 7 shows a cross section BB ′ of FIG.
In the semiconductor device to be studied, a trench is formed in the epitaxial semiconductor layer, the base semiconductor layer, and the source semiconductor layer stacked on the semiconductor substrate in the element region, and a gate electrode is formed in the trench via an oxide film. . The semiconductor device operates as a trench MOSFET semiconductor device. A termination guard ring trench for relaxing an electric field is provided in a termination region surrounding the element region.
Further, in the semiconductor device to be studied, the gate wiring is connected to the gate electrode buried portion formed in the trench of the element region and is pulled up from the both ends of the trench to the upper side of the semiconductor substrate through the oxide film at the upper corner portion of the trench side wall. A trench sidewall upper corner semiconductor layer is formed to accelerate oxidation of the layer and the oxide film at the trench sidewall upper corner. The semiconductor device considered was expected to achieve both improved breakdown voltage and lower on-resistance.
However, the inventors have found that in the semiconductor device, dielectric breakdown occurs between the front surface of the element region and the back surface of the termination region, and it is difficult to further improve the breakdown voltage performance.

  The present invention suppresses dielectric breakdown that occurs between the surface of the element region of the semiconductor device and the back surface of the termination region, and can simultaneously achieve high breakdown voltage, low on-resistance, and improved reliability of the gate oxide film. An object is to provide a semiconductor device.

In order to solve the above problems, a semiconductor device of the present invention includes a first conductivity type semiconductor substrate,
A first conductive type epitaxial semiconductor layer that functions as a drain and is formed from the surface of the first conductive type epitaxial semiconductor layer in an element region that is formed on the semiconductor substrate and serves as a main energization path of the MOSFET. A second conductivity type base semiconductor layer functioning as a base in the element region, and a first conductivity type source formed inside from the surface of the second conductivity type base semiconductor layer and functioning as a source in the element region In the semiconductor layer and the element region, the first conductive layer penetrates from the surface of the first conductive type source semiconductor layer to the inside of the first conductive type source semiconductor layer and the second conductive type base semiconductor layer. Embedded in a stripe-shaped trench reaching the epitaxial semiconductor layer of the type via a gate oxide film, and functions as a gate In a gate electrode buried portion and a termination region for the guard ring of the MOSFET, a stripe-shaped termination trench that penetrates the inside of the second conductivity type base semiconductor layer and reaches the first conductivity type first semiconductor layer A guard ring electrode buried portion buried in the inside of the gate electrode buried in the gate electrode, and one end of a selected part of the gate electrode buried portion of the gate electrode buried portion, and the stripe-shaped trench And is pulled up from one end to the oxide film at the upper corner of the trench side wall above the semiconductor substrate, and is connected to the other end of the unselected gate electrode buried portion of the gate electrode buried portion, and The gate is pulled up from the other end of the stripe-shaped trench above the semiconductor substrate onto the oxide film at the upper corner of the trench sidewall. A first conductive layer provided adjacent to one end or the other end of the stripe-shaped trench where the gate wiring layer is pulled up above the semiconductor substrate at an upper corner of the sidewall of the stripe-shaped trench A trench sidewall upper end corner semiconductor layer, and of the trench sidewall upper end corner semiconductor layer, the trench sidewall upper end corner semiconductor layer provided adjacent to one end of the stripe-shaped trench includes the stripe shape Each of the trenches is formed independently at one end.

  The semiconductor device according to the present invention is connected to the gate wiring layer connected to the gate wiring layer at one end of the stripe-shaped trench and to the gate wiring layer at the other end opposite to the one end of the stripe-shaped trench. The gate electrode buried portions may be alternately arranged.

  A semiconductor device of the present invention includes a first conductivity type semiconductor substrate, a first conductivity type epitaxial semiconductor layer formed on the semiconductor substrate and functioning as a drain in an element region serving as a main conduction path of the MOSFET, Formed from the surface of the first conductivity type epitaxial semiconductor layer to the inside, and formed from the surface of the second conductivity type base semiconductor layer and the second conductivity type base semiconductor layer functioning as a base in the element region A first conductive type source semiconductor layer functioning as a source in the element region; and in the element region, the first conductive type source semiconductor layer and the second conductive layer from a surface of the first conductive type source semiconductor layer. A gate is formed inside the stripe-shaped trench that penetrates the inside of the conductive type base semiconductor layer and reaches the first conductive type epitaxial semiconductor layer. A gate electrode buried portion functioning as a gate buried through a trioxide film, and a termination region for a guard ring, penetrating through the inside of the second conductivity type base semiconductor layer, and A stripe-shaped terminal trench reaching one semiconductor layer and connected to a guard ring electrode buried portion buried via an oxide film and a central portion located between both ends of the gate electrode buried portion; A gate wiring layer that is pulled up on the oxide film at the upper corner of the trench side wall above the semiconductor substrate from a central portion located between both ends of the trench, and the gate wiring layer at the upper corner of the side wall of the stripe-shaped trench On the side wall of the first conductivity type trench provided around the center of the stripe-shaped trench that is pulled up above the semiconductor substrate Characterized in that it comprises a corner portion semiconductor layer.

  A semiconductor device of the present invention is connected to a gate electrode buried portion formed in a trench in an element region of a MOSFET, and a trench that insulates a lifted portion of the gate wiring layer from a gate wiring layer that is pulled up from the upper end of the trench side to the semiconductor substrate. An oxide film at the upper end corner of the side wall and a semiconductor layer at the upper end corner of the trench side wall are provided. In the semiconductor device of the present invention, the shape and arrangement of the semiconductor layer at the upper corner of the trench sidewall are determined so as to reduce the pinch region formed in the traveling path of holes and electrons generated by the avalanche on the guard ring trench sidewall in the termination region. As a result, the dielectric breakdown that occurs between the element region and the termination region of the semiconductor device is suppressed, and high breakdown voltage, low on-resistance, and improved gate oxide film reliability are realized.

1 is a plan view showing a semiconductor device according to a first embodiment. It is sectional drawing which shows the A-A 'cross section of the semiconductor device based on 1st Embodiment illustrated by FIG. It is sectional drawing which shows the semiconductor device which concerns on 2nd Embodiment. It is a top view which shows the semiconductor device which concerns on 3rd Embodiment. It is a top view which shows the semiconductor device which concerns on the example of examination. It is sectional drawing which shows the A-A 'cross section of the semiconductor device based on the examination example illustrated by FIG. FIG. 6 is a cross-sectional view showing a B-B ′ cross section of the semiconductor device according to the study example illustrated in FIG. 5. It is a figure explaining the mechanism of the dielectric breakdown of a semiconductor device.

Hereinafter, a semiconductor device of the present invention (hereinafter also referred to as “MOSFET semiconductor device” or “MOSFET”) will be described with reference to the drawings.
[First Embodiment]
FIG. 1 is a partial schematic plan view showing the arrangement of the surface of the semiconductor layer of the semiconductor device 51 according to the first embodiment of the present invention, and FIG. 2 is a cross-sectional view showing the AA ′ cross section of FIG. is there.

  The semiconductor device 51 according to the first embodiment includes an element region 90 that is located in the central portion of the semiconductor device and serves as a main energization path of the MOSFET semiconductor device, and an electric field that surrounds the main energization path located in the central portion of the semiconductor device. It has a termination region 92 that relaxes.

  In addition, the semiconductor device 51 according to the first embodiment includes a first conductive type semiconductor substrate 1 and an element region 90 formed on the first conductive type semiconductor substrate 1 and serving as a main conduction path of the MOSFET. A first conductivity type epitaxial semiconductor layer 2 that functions as a drain; a second conductivity type base semiconductor layer 3 that is formed from the surface of the first conductivity type epitaxial semiconductor layer 2 and functions as a base in the element region 90; The first conductivity type source semiconductor layer 4 is formed from the surface of the second conductivity type base semiconductor layer 3 and functions as a source in the element region 90. In the semiconductor device 51 according to the first embodiment, a drain electrode is formed on the back surface of the first conductivity type semiconductor substrate 1.

  In the element region 90, the first conductive type epitaxial semiconductor layer penetrates the inside of the first conductive type source semiconductor layer 4 and the second conductive type base semiconductor layer 3 from the surface of the first conductive type source semiconductor layer 4. A stripe-shaped trench 5 reaching 2 is formed. A gate electrode buried portion 8 a that functions as the gate of the semiconductor device 51 is buried in the stripe-shaped trench 5 through the gate oxide film 6. As shown in FIG. 1, the first conductive type source semiconductor layer 4 and the stripe-shaped trench 5 are arranged so as to intersect at a right angle.

  In the termination region 92 for the guard ring, a stripe-shaped termination trench 5 that penetrates the inside of the second conductivity type base semiconductor layer 3 and reaches the first conductivity type epitaxial semiconductor layer 2 is formed. A guard ring electrode 9 is embedded in the stripe-shaped termination trench 5 via an oxide film.

  In the semiconductor device according to the first embodiment shown in FIG. 1, six trenches 5 are shown in the element region and four trenches are shown in the termination region. The number of the trenches 5 is an example, and is not limited to the number of the trenches 5 illustrated.

The semiconductor device 51 according to the first embodiment has a gate wiring layer 8 b formed on the surfaces of the semiconductor substrate 1 and the epitaxial semiconductor layer 2 via the field oxide film 7. The gate wiring layer 8 b is connected to the gate electrode buried portion 8 a and the gate electrode terminal portion 8 c to constitute the gate electrode 20.
The gate wiring layer 8b is connected to one end of the gate electrode buried portion 8a and is pulled up from one end of the stripe-shaped trench 5 above the semiconductor substrate via the oxide film 43 at the upper corner portion of the trench side wall.
The gate wiring layer 8b is connected to the other end (not shown) opposite to one end of the gate electrode buried portion 8a that is not connected to one end of the gate electrode buried portion 8a, and from the other end of the stripe-shaped trench to above the semiconductor substrate. Is pulled up through an oxide film at the upper corner of the trench sidewall.

That is, the gate electrode buried portion 8a is formed on the gate wiring layer 8b on either the one end on the right side of the stripe-shaped trench 5 shown in FIG. 1 or 2 or the other end on the left side of the stripe-shaped trench 5 (not shown). And pulled up above the semiconductor substrate.
The gate electrode buried portion 8a is alternately connected to the gate wiring layer 8b at one end or the other end of the stripe-shaped trench 5 illustrated on the right side of the stripe-shaped trench of FIG. 1 or FIG. May be.

The oxide film at the upper corner of the trench side wall refers to the oxide film 43 covering the upper corner of the stripe-shaped trench 5.
In the semiconductor device according to the first embodiment, as an example, the gate electrode buried portion and the gate wiring are formed of polysilicon, and the gate electrode terminal portion is formed of aluminum.

  In the termination region 92 of the semiconductor device 51 according to the first embodiment, the guard ring electrode embedded portion 9 is pulled up by the gate wiring 8b and the gate electrode terminal similarly to the gate electrode embedded portion 8a of the element region 90. The gate electrode 20 is equipotentially connected to the portion 8c.

In the semiconductor device 51 according to the first embodiment, the first conductivity type trench sidewall upper end corner semiconductor layer 41 is the upper end corner of the sidewall of the stripe-shaped trench 5 and the gate wiring layer is pulled up above the semiconductor substrate. The stripe-shaped trench 5 is provided adjacent to one end or the other end. When the oxide film 43 at the upper corner portion of the trench sidewall is formed on the semiconductor layer 41, the first conductive type trench sidewall upper corner portion semiconductor layer 41 is subjected to accelerated oxidation at one end of the stripe-shaped trench. At the other end, the thickness of the oxide film 43 at the upper corner of the side wall of the stripe-shaped trench 5 is increased.
When the gate electrode buried portion 8a is alternately connected to the gate wiring layer 8b at one end or the other end of the stripe-shaped trench 5 and pulled up above the semiconductor substrate, the first conductivity type trench sidewall upper corner semiconductor The layer 41 is also provided alternately at one end and the other end adjacent to one end or the other end of the stripe-shaped trench 5.

  Impurity doping of the first conductivity type trench sidewall upper corner semiconductor layer 41 is performed by ion implantation or thermal diffusion. The film thickness of the oxide film at the upper corner of the sidewall of the trench formed on the first conductive type trench upper edge corner semiconductor layer 41 determines the dielectric strength of the oxide film at the upper corner of the trench. When impurities are doped into the trench sidewall upper corner semiconductor layer 41, the thickness of the oxide film 43 formed on the trench sidewall upper corner semiconductor layer 41 is increased compared to the portion where no impurity is doped. As a result, the withstand voltage is increased and the reliability is improved.

The first conductivity type trench sidewall upper corner semiconductor layer 41 may be formed in the same step as the step of forming the first conductivity type source semiconductor layer 4 from the surface of the second conductivity type base semiconductor layer 3 to the inside. . In this case, the first conductivity type trench sidewall upper corner semiconductor layer 41 and the first conductivity type source semiconductor layer 4 can be formed with the same impurity concentration and the same depth.
For example, arsenic (As) is ion-implanted at 4 to 5 × E15 cm −3 to form the source semiconductor layer 4 and the trench sidewall upper corner semiconductor layer 41, and 800 to 850 ° C. on the trench sidewall upper corner semiconductor layer 41. When the gate oxide film is formed by wet oxidation of H 2 / O 2 gas at a temperature of 5 ° C., the thickness of the oxide film 43 formed on the semiconductor sidewall 41 at the upper corner portion of the trench sidewall is implanted with arsenic ions. It is about 2 to 2.5 times as much as that of the unexposed portion.

[Dielectric breakdown of a semiconductor device including a guard ring structure and a semiconductor layer at the upper corner of a trench side wall]
The present invention has been made in the course of examining ESD (Electro-Static-Discharge) dielectric breakdown in the semiconductor device shown in FIGS. The semiconductor device shown in FIGS. 5 to 7 simultaneously improves the breakdown voltage by the trench guard ring structure and improves the breakdown voltage and reliability of the gate oxide film by the accelerated oxidation at the upper corner of the trench side wall.

With reference to FIG. 8, the dielectric breakdown in the element region 190 and the termination region 192 of the trench type MOSFET semiconductor device 151 of the examination example will be described. In order to facilitate understanding of the phenomenon, the case where the first conductivity type is N-type and the second conductivity type is P-type will be described as an example.
In the trench type MOSFET semiconductor device shown in FIG. 8, when a drain voltage is applied to the drain terminal D, the main junction between the N-type epitaxial semiconductor layer 102 functioning as a drain and the P-type base semiconductor layer 103 functioning as a base. A depletion layer is generated. This depletion layer extends beyond the bottom of the trench 105 in the element region 190 to the termination guard ring trench 105 and relaxes the electric field between the element region 190 and the termination guard ring region 192.
On the other hand, the electric field strength increases in a region adjacent to the termination guard ring trench 105. As a result, an avalanche is generated in a region having a high electric field strength on the side wall of the termination guard ring trench 105, and an electron / hole pair is generated. The electrons of the electron-hole pair move from the N-type epitaxial semiconductor layer 102 functioning as a drain to the N-type semiconductor substrate 101 side. On the other hand, the hole moves to the side of the source electrode at the ground potential. (See region A in FIG. 8)

  In the trench type MOSFET semiconductor device 151 according to the examination example, in order to increase the film thickness of the oxide film at the upper corner of the trench side wall of the element region 190, N + type source impurity layer or impurity diffusion is performed simultaneously with the N + type source semiconductor layer 104. A trench sidewall upper end corner semiconductor layer 141 is formed. The P-type base semiconductor layer 103 under the N + type trench sidewall upper-end corner semiconductor layer 141 forms a pinch structure with the N-type epitaxial semiconductor layer 102, so that its resistance increases and holes accumulate. .

  For this reason, the potential of the P-type base semiconductor layer 103 in which the hole travels is higher than the ground potential, and the forward potential between the P-type base semiconductor layer 103 and the N + type source semiconductor layer 104 is lowered. As a result, a parasitic NPN transistor is formed among the N-type epitaxial semiconductor layer 102, the P-type base semiconductor layer 103, and the N + -type source semiconductor layer 104 functioning as drains, and the snap-back phenomenon is caused by the operation of the parasitic NPN transistor. It can be considered that dielectric breakdown occurs. (See region C in FIG. 8)

  In particular, in the trench type MOSFET semiconductor device of the examination example, in order to increase the thickness of the oxide film at the upper corner of the trench side wall of the element region, N + type source impurity layer 104 is simultaneously implanted with impurity ions or impurity diffusion. When the trench sidewall upper corner semiconductor layer 141 is formed, the bulk resistance to the contact 110 in the element region 190 is increased, the potential of the base semiconductor layer 103 is increased, the snapback phenomenon is likely to occur, and the dielectric strength is increased. descend.

[Comparison of Semiconductor Device According to First Embodiment and Semiconductor Device According to Examination Example]
The semiconductor device according to the first embodiment is compared with the semiconductor device according to the study example.
As shown in FIGS. 5 and 6, in the semiconductor device 151 according to the study example, the gate electrode buried portions 108 a of the stripe-shaped trenches 105 arranged side by side are arranged at both ends of the stripe-shaped trench 105. Is connected to the gate electrode terminal portion 108c of the gate electrode 120.
N + type trench sidewall upper end corner semiconductor layers 141 are provided adjacent to the raised portions of the gate wiring 108 b at the upper end corners of both ends of the sidewall of the stripe-shaped trench 105.
Therefore, the area of the region where the N + type trench sidewall upper corner semiconductor layer 141 is provided is increased. The P-type base semiconductor layer 103 under the N + -type trench sidewall upper-end corner semiconductor layer 141 forms a pinch structure with the N-type epitaxial semiconductor layer 102, so that its resistance increases and holes accumulate. The potential of the P-type base semiconductor layer 112 is increased. As a result, the operation of a parasitic NPN transistor formed between the N-type epitaxial semiconductor layer 102, the P-type base semiconductor layer 103, and the N + -type source semiconductor layer 104 causes a snapback phenomenon and causes dielectric breakdown.

  Since the semiconductor device of the study example has been described as an example in which the first conductivity type is N-type and the second conductivity type is P-type, the semiconductor device of the study example and the semiconductor device according to the first embodiment are compared below. Also in the description, the semiconductor device according to the first embodiment will be described as an example in which the first conductivity type is N-type and the second conductivity type is P-type.

In the semiconductor device 51 according to the first embodiment, in order to increase the film thickness of the oxide film at the upper corner portion of the side wall of the trench 5, the semiconductor layer 41 at the upper corner portion of the N + trench side wall is formed of the stripe-shaped trench 5. The gate wiring layer 8b is provided adjacent to either one end or the other end of the stripe-shaped trench 5 that is pulled up above the semiconductor substrate at the upper corner of the side wall.
Further, when the gate electrode buried portion 8a is alternately connected to the gate wiring layer 8b at one end or the other end of the stripe-shaped trench 5 and pulled up above the semiconductor substrate, the semiconductor layer at the upper corner portion of the N + type trench sidewall 41 is also alternately provided adjacent to one end or the other end of the stripe-shaped trench 5.

That is, in the semiconductor device 51 according to the first embodiment, the N + type trench sidewall upper-end corner semiconductor layer 41 is provided on one side of the stripe-shaped trench 5. On the line extending from the trench end of the termination region 92 to the base contact semiconductor layer 12 of the element region 90, a region where the N + type trench sidewall upper corner semiconductor layer 41 does not exist is provided.
Thus, in the semiconductor device 51 according to the first embodiment, the N + type trench sidewall upper end corner semiconductor layer 41 of the N + type trench sidewall upper end corner semiconductor layer 141 of the semiconductor device 151 of the examination example is compared. Since the area can be reduced, the pinch structure region of the gate wiring pulling portion can be reduced, the snapback phenomenon can be suppressed, and the withstand voltage can be improved.

  As described above, in the semiconductor device 51 according to the first embodiment, the area of the region where the N + type trench sidewall upper corner semiconductor layer 41 is provided is reduced. The depletion layer extending from the trench 5 in the element region 90 which is the main junction reaches the trench 5 in the termination region 92, and the electric field between the trench in the element region 90 and the trench 5 in the termination region 92 is relaxed. Thereby, the electric field at the side wall of the termination trench 5 is increased. For this reason, an avalanche is generated on the side wall of the termination trench 5, and an electron / hole pair is generated. The area of the region where the N + type trench sidewall upper end corner semiconductor layer 41 is provided is reduced to reduce the parasitic pinch region. As a result, holes generated by the avalanche are quickly absorbed by the base contact layer 12 having the ground potential, and the potential of the base semiconductor layer 3 is prevented from becoming higher than the ground potential. Thereby, the occurrence of the snapback phenomenon is suppressed, and the withstand voltage is improved.

[Effect of the invention according to the first embodiment]
In the semiconductor device according to the first embodiment of the present invention, corresponding to the gate wiring connected to the gate electrode buried portion at one of the one end or the other end of the stripe-shaped trench and pulled up above the semiconductor substrate, A trench sidewall upper corner semiconductor layer that accelerates oxidation of the oxide film at the upper corner of the trench sidewall is also disposed at one end or the other end of the stripe-shaped trench. Thereby, the area of the trench sidewall upper corner semiconductor layer can be reduced, the pinch region formed under the trench sidewall upper corner semiconductor layer is reduced, and the operation of the parasitic transistor is suppressed. Therefore, in the semiconductor device according to the first embodiment, dielectric breakdown occurring between the element region and the termination region of the semiconductor device is prevented, and high breakdown voltage, low on-resistance, and improvement in gate oxide film reliability are realized. It becomes possible.

[Second Embodiment]
A semiconductor device 52 according to the second embodiment will be described with reference to FIG. In the semiconductor device 52 according to the second embodiment, the guard ring electrode embedded portion 9 embedded in the trench of the termination region 92 is pulled up to the semiconductor surface and is not connected to the gate electrode 20. As a result, the guard ring electrode embedded portion 9 is electrically floating with respect to the gate electrode 20. As a result, it is possible to omit placing the first conductivity type trench upper corner semiconductor layer adjacent to the termination region 92 in which the guard ring electrode embedded portion 9 is embedded, and a pinch structure is formed in the termination region 92. It can be prevented from occurring.

  As shown in FIG. 3, in the gate electrode 20 of the semiconductor device 52 according to the second embodiment, the gate electrode terminal portion 8 c is formed across the insulating films 7 and 14 on the trench 5 in the termination region 92, The gate electrode terminal portion 8c may be connected to the gate electrode buried portion 8a through the contact hole 11 by the gate wiring 8b.

  According to the second embodiment of the present invention, a semiconductor device having a high dielectric breakdown resistance of a transistor can be obtained. Further, by combining the second embodiment and the first embodiment of the present invention, a semiconductor device having a higher dielectric breakdown resistance of the transistor can be obtained.

[Third Embodiment]
A semiconductor device 53 according to the third embodiment will be described with reference to FIG. The semiconductor device 53 according to the third embodiment is manufactured through the same manufacturing process as the semiconductor devices according to the first and second embodiments. However, the semiconductor device 53 according to the third embodiment has a configuration in which the gate electrode buried portion 8 in the stripe-shaped trench 5 is pulled up in the element region 90 at the center between both ends of the stripe-shaped trench 5. The semiconductor device is different from the semiconductor device according to the first embodiment and the second embodiment in that it has the above.

  In the semiconductor device 53 according to the third embodiment, the first conductivity type trench sidewall upper corner semiconductor layer 41 is provided around the raised portion of the gate electrode buried portion 8a in the center of the stripe-shaped trench 5, and the trench A thick oxide film is formed at the upper corner of the side wall. As a result, since the first conductivity type trench sidewall upper corner semiconductor layer 41 is not formed at the end of the stripe-shaped trench 5, a pinch structure is formed between the base contact semiconductor layer 12 and the trench sidewall of the termination region 92. It is possible to reduce the base resistance by preventing the occurrence of.

  As a result, the semiconductor device according to the third embodiment has a structure in which the snapback phenomenon is unlikely to occur, and the breakdown resistance of the transistor is increased, so that high breakdown voltage, low on-resistance, and reliability of the gate oxide film are improved. Can be realized.

DESCRIPTION OF SYMBOLS 1,101: Semiconductor substrate 2, 102: Epitaxial semiconductor layer 3, 103: Base semiconductor layer 4, 104: Source semiconductor layer 5, 105: Trench groove 6, 106: Gate oxide film 7, 107: Field oxide film 8a, 108a : Gate electrode buried portion 8b, 108b: gate wiring 8c, 108c: gate electrode terminal portion 9, 109: guard ring electrode buried portion 10, 110: contact hole 11, 111: contact hole 12, 112: base contact semiconductor layer 14, 114: insulating film 20, 120: gate electrode 21, 121: electrode 30, 130: drain electrode 41, 141: trench sidewall upper corner semiconductor layer 42, 142: termination region semiconductor layer 43, 143: trench sidewall upper corner Oxide films 51, 52, 53, 151: Semiconductor devices 90, 190: Elementary Area 92,192: the termination region

Claims (3)

A first conductivity type semiconductor substrate;
An epitaxial semiconductor layer of a first conductivity type formed on the semiconductor substrate and functioning as a drain in an element region serving as a main energization path of the MOSFET;
A second conductive type base semiconductor layer formed from the surface of the first conductive type epitaxial semiconductor layer and functioning as a base in the element region;
A first conductive type source semiconductor layer formed inside from the surface of the second conductive type base semiconductor layer and functioning as a source in the element region;
In the element region, the first conductivity type epitaxial semiconductor penetrates from the surface of the first conductivity type source semiconductor layer to the inside of the first conductivity type source semiconductor layer and the second conductivity type base semiconductor layer. A gate electrode buried portion that is buried through a gate oxide film inside a stripe-shaped trench reaching the layer and functions as a gate;
In the termination region for the guard ring of the MOSFET, an oxide film is formed inside the stripe-shaped termination trench that reaches the first semiconductor layer of the first conductivity type through the inside of the base semiconductor layer of the second conductivity type. A guard ring electrode embedded portion embedded through,
A portion of the gate electrode buried portion that is selected is connected to one end of the gate electrode buried portion, and is pulled up from one end of the stripe-shaped trench above the semiconductor substrate onto the oxide film at the upper corner of the trench sidewall. In addition, the upper end angle of the trench sidewall is connected to the other end of the non-selected part of the gate electrode buried portion of the gate electrode buried portion and from the other end of the stripe-shaped trench to above the semiconductor substrate. A gate wiring layer pulled up on the oxide film of the part,
The upper edge of the first conductivity type trench sidewall provided adjacent to one end or the other end of the stripe-shaped trench where the gate wiring layer is pulled up above the semiconductor substrate at the upper corner of the sidewall of the stripe-shaped trench Of the trench sidewall upper end corner semiconductor layer, the trench sidewall upper end corner semiconductor layer provided adjacent to one end of the stripe-shaped trench is one end of each stripe-shaped trench. Each of the semiconductor devices is formed independently.   A gate electrode buried portion connected to the gate wiring layer at one end of the stripe-shaped trench and a gate electrode buried portion connected to the gate wiring layer at the other end opposite to the one end of the stripe-shaped trench are alternately arranged. The semiconductor device according to claim 1, wherein the semiconductor device is disposed on the substrate. A first conductivity type semiconductor substrate;
An epitaxial semiconductor layer of a first conductivity type formed on the semiconductor substrate and functioning as a drain in an element region serving as a main energization path of the MOSFET;
A second conductive type base semiconductor layer formed from the surface of the first conductive type epitaxial semiconductor layer and functioning as a base in the element region;
A first conductive type source semiconductor layer formed inside from the surface of the second conductive type base semiconductor layer and functioning as a source in the element region;
In the element region, the first conductivity type epitaxial semiconductor penetrates from the surface of the first conductivity type source semiconductor layer to the inside of the first conductivity type source semiconductor layer and the second conductivity type base semiconductor layer. A gate electrode buried portion that is buried through a gate oxide film inside a stripe-shaped trench reaching the layer and functions as a gate;
In the termination region for the guard ring, an oxide film is embedded inside the stripe-shaped termination trench that penetrates the inside of the second conductivity type base semiconductor layer and reaches the first conductivity type first semiconductor layer. A guard ring electrode embedded portion,
It is connected to the central portion located between both ends of the gate electrode buried portion, and is pulled up from the central portion located between both ends of the stripe-shaped trench above the oxide film at the upper corner portion of the trench side wall above the semiconductor substrate. A gate wiring layer;
First-conductivity-type trench sidewall upper-end corner semiconductor provided around the central portion of the stripe-shaped trench where the gate wiring layer is pulled up above the semiconductor substrate at the upper-end corner of the stripe-shaped trench sidewall A semiconductor device comprising a layer.

Images