JP2004200441A - Semiconductor device and its manufacturing method - Google Patents

Semiconductor device and its manufacturing method Download PDF

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JP2004200441A
JP2004200441A JP2002367716A JP2002367716A JP2004200441A JP 2004200441 A JP2004200441 A JP 2004200441A JP 2002367716 A JP2002367716 A JP 2002367716A JP 2002367716 A JP2002367716 A JP 2002367716A JP 2004200441 A JP2004200441 A JP 2004200441A
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trench
gate electrode
type column
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Yoshikuni Hatsutori
佳晋 服部
Makoto Kuwabara
誠 桑原
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Toyota Central R&D Labs Inc
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/063—Reduced surface field [RESURF] pn-junction structures
    • H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices
    • H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • H01L29/0852—Source or drain regions of field-effect devices of field-effect transistors with insulated gate of DMOS transistors
    • H01L29/0873—Drain regions
    • H01L29/0878—Impurity concentration or distribution

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Chemical & Material Sciences (AREA)
  • Composite Materials (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To make an increase in on-state resistance hardly happen even if there is a misalignment of a mask when forming a trench, to reduce on-state resistance, to stabilize the breakdown characteristic, and to make a parasitic transistor hardly turn on. <P>SOLUTION: A semiconductor device comprises a semiconductor section 21 wherein trenches 33 are formed, a gate insulation film 34 formed along the wall face of the trenches 33, and gate electrodes 36 formed inside the trenches 33. A p-type body region 30 of the semiconductor section 21 includes an area adjacent to the gate electrodes 36. P-type column regions 24 and n-type column regions 26 are extended in a direction vertical to the depthwise direction of the gate electrodes 36 in a plain view, and are in contact with the p-type body region 30. The p-type column regions 24 and the n-type column regions 26 are in contact with each other. An n-type region 28 includes an area formed between the bottoms of the gate electrodes 36 and top faces of the p-type column regions 24. <P>COPYRIGHT: (C)2004,JPO&NCIPI

Description

【０００１】
【発明の属する技術分野】本発明は、半導体装置とその製造方法に関する。
【０００２】
【従来の技術と発明が解決しようとする課題】
【特許文献１】
特開平９−２６６３１１号公報（その公報の図面の図７〜図９等）
【特許文献２】
特開２０００−２６０９８４号公報（その公報の図面の図１、図４等）
【０００３】
特許文献１には、図１に示すように、ドリフト領域にいわゆるスーパージャンクション構造部２３を設けたパワーＭＯＳＦＥＴが示されている。スーパージャンクション構造部２３には、ｐ型コラム領域２４とｎ型コラム領域２６が交互に形成されている。
ドリフト領域にスーパージャンクション構造部２３を設けると、ドリフト領域がｎ型領域のみの場合に比べて、オン抵抗とソース・ドレイン間耐圧のトレードオフの関係を改善できる。
【０００４】
図１の構造では、ｐ型コラム領域２４とｎ型コラム領域２６は、平面視したときにゲート電極３６の奥行方向に対して非平行方向（この例では直交方向）に伸びている。別の表現をすると、ｐ型コラム領域２４とｎ型コラム領域２６は、平面視したときにゲート電極３６の奥行方向に対して非直交方向（この例では平行方向）に交互に形成されている。これらの態様を以下では「第１態様」という。
これに対し、図２に示すように、ｐ型コラム領域２４とｎ型コラム領域２６が、平面視したときにゲート電極３６の奥行方向に対して平行方向に伸びる構造がある。別の表現をすると、ｐ型コラム領域２４とｎ型コラム領域２６が、平面視したときにゲート電極の奥行方向に対して直交方向に交互に形成されている構造がある。これらの態様を以下では「第２態様」という。
第１態様は、トレンチ３３を形成する際のマスクずれが生じた場合（例えば図示横方向にずれた場合）でも、ゲート電極３６とｎ型コラム領域２６が重なる領域の変化が小さい。よって、第２態様に比べてオン抵抗の変化が小さいという利点がある。
【０００５】
第２態様の場合、トレンチ３３を形成する際のマスクが図示横方向にずれたときに、オン抵抗が増加し易い。第２態様において、本来図３に示す位置にトレンチ３３を形成するはずであったのに、マスクずれによって図４に示す位置にトレンチ３３が形成されたとする。図３の場合、半導体装置のオン時には、ゲート電極３６に隣接するボディ領域３０にチャネル３０ｘが形成される。一方、図４の場合、このチャネル３０ｘに加えて、本来チャネルを形成する予定になかったｐ型領域の部分２４ｘにもチャネル（反転層）が形成されてしまう。この反転層２４ｘの部分は３０ｘの部分に比べて高抵抗になる。よって、オン抵抗が増加してしまう。
これに対し、図１に例示される第１態様によると、上記のようなマスクずれが生じた場合でも、オン抵抗が増加しにくい。
【０００６】
特許文献２には、図５に示すように、ボディ領域３０の底面とスーパージャンクション構造部２３の頂面の間全体に、ｎ−型領域５０を設けた構造が示されている。このようなｎ−型領域５０を設けると、オン抵抗を低減できる旨が特許文献２に記載されている。
【０００７】
しかし、図５に示す構造によると、ｐ型コラム領域２４がフローティングの電位状態となってしまう。ｐ型コラム領域２４がフローティングの電位状態になると、耐圧時にｐ型コラム領域２４とｎ型コラム領域２６のｐｎ接合部に、これらの領域２４，２６を空乏化させるための充分な電圧がかからない場合が生じる。この結果、耐圧特性が不安定となる場合が生じる。
【０００８】
特許文献２にはさらに図６に示すように、半導体装置の後部に、ｐ型コラム領域５４の後部頂面とｐ型ボディ領域３０の後面をつなぐためのｐ型の接続用領域５８を設けた構造が示されている。この構造によると、ｐ型コラム領域５４がフローティングの電位状態となることを回避できる。
【０００９】
しかし、このようにｐ型ボディ領域３０とｐ型コラム領域５４の間に接続用領域５８を設けると、ｐ型ボディ領域３０とｐ型コラム領域５４の間の電流経路が長くなる。この結果、この電流経路が長くなった分、抵抗が増加してしまう。これにより、ｎ＋型ソース領域３２とｐ型ボディ領域３０とｎ＋型ドレイン領域２２で形成されるｎｐｎ構造の寄生トランジスタのベース抵抗が高くなる。このため、この寄生トランジスタがオンし易くなってしまう。
【００１０】
本発明は、半導体装置について以下の課題を解決することを目的とする。
（１）トレンチを形成する際のマスクずれが生じてもオン抵抗が増加しにくくすること。
（２）オン抵抗を低減すること。
（３）耐圧特性を安定化すること。
（４）寄生トランジスタをオンさせにくくすること。
【００１１】
【課題を解決するための手段及び作用と効果】本発明に係る半導体装置は、トレンチが形成された半導体部と、トレンチの壁面に沿って形成されたゲート絶縁膜と、トレンチ内に形成されたゲート電極を備えている。半導体部は、第１導電型のボディ領域と、第１導電型の第１領域と、第２導電型の第２領域と、第２導電型の第３領域を有する。ボディ領域は、ゲート電極にゲート絶縁膜を介して隣合う領域を有する。第１領域は、平面視したときにゲート電極の奥行方向に対して非平行方向に伸びているとともにボディ領域に接している。第２領域は、平面視したときにゲート電極の奥行方向に対して非平行方向に伸びているとともに第１領域と隣合っている。第３領域は、ゲート電極と第１領域の間に形成されている。
ここで、第１領域と第２領域は接していてもよいし、第１領域と第２領域の間に例えば絶縁層が介在していてもよい。
【００１２】
本発明に係る他の半導体装置は、トレンチが形成された半導体部と、トレンチの壁面に沿って形成されたゲート絶縁膜と、トレンチ内に形成されたゲート電極を備えている。半導体部は、第１導電型のボディ領域と、第１導電型の第１領域と、第２導電型の第２領域と、第２導電型の第３領域を有する。ボディ領域は、ゲート電極にゲート絶縁膜を介して隣合う領域を有する。第１領域と第２領域は、平面視したときにゲート電極の奥行方向に対して非直交方向に交互に形成されている。第３領域は、ゲート電極と第１領域の間に形成されている。
【００１３】
本発明者は研究の結果、図１に例示される態様（第１態様）に関する新たな知見を得た。具体的には、半導体装置のオン時に、ｎ型コラム領域２６だけでなく、ｐ型コラム領域２４のうちゲート電極３６に隣接する領域にも電流が流れるという知見を得た（図７〜図１０を参照して実施例の欄で説明する内容を参照）。図１に示す構造では、ｐ型コラム領域２４のゲート電極３６に隣接する領域に反転層が形成され、電流が流れる。この反転層の部分は高抵抗であるため、オン抵抗を増加させる要因となる。
本発明者は、上記知見から図１のゲート電極３６とｐ型コラム領域２４の間に、高抵抗の反転層の代わりに予めｎ型領域（上記第３領域の一例）を設けておけば、オン抵抗を低減できることを見出した。
また、本発明者は、上記知見から図１の構造のようにｐ型ボディ領域３０とｐ型コラム領域２４の間の全体にｎ型領域５０を設けなくてもオン抵抗を低減できることを見出した。即ち、ｐ型コラム領域２４がｐ型ボディ領域３０に直接的に接する構造でも、オン抵抗を効果的に低減できることを見出した。
【００１４】
（１）本発明に係る半導体装置では、第１領域と第２領域は、平面視したときにゲート電極の奥行方向に対して非平行方向に伸びている。あるいは、第１領域と第２領域は、平面視したときにゲート電極の奥行方向に対して非直交方向に交互に形成されている。よって、トレンチを形成する際のマスクずれが生じた場合等でも、オン抵抗が増加しにくい。
（２）本発明に係る半導体装置は、ゲート電極と第１領域の間に形成された第３領域を有する。よって、上記したようにオン抵抗をより低減できる。
（３）本発明に係る半導体装置では、第１導電型の第１領域は第１導電型のボディ領域に接している。よって、第１領域がフローティングの電位状態となることを回避できる。このため、耐圧特性を安定化できる。
（４）本発明に係る半導体装置では、第１領域はボディ領域に接している。よって、第１領域とボディ領域間の電流経路を短くできる。このため、半導体装置内の寄生トランジスタをオンさせにくくすることができる。
【００１５】
第１領域と第２領域は、平面視したときにゲート電極の奥行方向に対してほぼ直交方向に伸びていることが好ましい。第１領域と第２領域は、平面視したときにゲート電極の奥行方向に対してほぼ平行方向に交互に形成されていることが好ましい。
【００１６】
第１領域は、ゲート電極の下方に位置する領域を有し、第３領域は、ゲート電極の底面と第１領域の頂面の間に形成された領域を有することが好ましい。また、第３領域は、ゲート電極の側面と第１領域の間に形成された領域を有することが好ましい。
これによると、オン抵抗をより有効に低減できる。
【００１７】
第３領域の不純物濃度は、第１領域及び／又は第２領域の不純物濃度よりも高いことが好ましい。
これによると、耐圧の低下を抑制しながら、オン抵抗をより低減できる。
【００１８】
半導体部は、第１領域及び／又は第２領域に接する第１導電型のドレイン領域を有することが好ましい。半導体部は、ボディ領域に接する第２導電型のソース領域を有することが好ましい。
第１領域と第２領域は、ボディ領域とドレイン領域の間に形成されていることが好ましい。第１領域と第２領域は、ほぼ同じ方向にストライプ状に伸びていることが好ましい。第１領域はオフ状態で実質的に完全空乏化することが好ましい。第２領域はオン状態で電流が流れ、オフ状態で実質的に完全空乏化することが好ましい。
【００１９】
本発明に係る半導体装置の製造方法は、第１導電型の第１領域と第２導電型の第２領域上の半導体領域の一部を少なくとも除去して、平面視したときに第１領域と第２領域が伸びる方向に対して非平行方向に伸び、かつ、第１領域と第２領域が露出する深さまで達するトレンチを形成する工程と、トレンチの底面に隣接する第１領域に第２導電型不純物を添加する工程を有する。この製造方法は、第２導電型不純物を活性化する工程をさらに有することが好ましい。
上記トレンチ形成工程に代えて、第１導電型の第１領域と第２導電型の第２領域上の半導体領域の一部を少なくとも除去して、平面視したときに第１領域と第２領域が交互に形成された方向に対して非直交方向に伸び、かつ、第１領域と第２領域が露出する深さまで達するトレンチを形成する工程を採用してもよい。
この製造方法によると、第１領域と第２領域上に半導体領域が存在する場合でも、第１領域に第２導電型不純物を効率的な方法で添加できる。
【００２０】
トレンチを形成する工程では、半導体領域のうちトレンチを形成しない領域上をマスクで覆い、マスクで覆っていない領域を除去してトレンチを形成し、第２導電型不純物を添加する工程では、半導体領域を前記マスクで覆ったままの状態で第２導電型不純物を添加することが好ましい。
これによると、第２導電型不純物を添加するために、新たにマスクを追加しなくてもよい。よって、製造工程を簡単化できる。
【００２１】
トレンチの側面に隣合う半導体領域への第２導電型不純物の侵入を抑制するマスクでトレンチの側面を覆う工程を有することが好ましい。
これによると、トレンチの側面に隣合う半導体領域に第２導電型不純物が侵入することで生じるゲートしきい値電圧の変動等を抑制できる。
【００２２】
また、他の半導体装置の製造方法は、第１導電型の第１領域と第２導電型の第２領域上に、第１領域を含む所定領域上が開口したマスクを配置する工程と、前記所定領域に第２導電型不純物を添加する工程と、第１領域と第２領域上に半導体領域を形成する工程と、少なくとも半導体領域の一部を除去して、第１領域と第２領域が伸びる方向に対して非平行方向に伸び、かつ、第２導電型不純物を添加した領域が露出する深さまで達するトレンチを形成する工程を有する。
上記トレンチ形成工程に代えて、少なくとも半導体領域の一部を除去して、平面視したときに第１領域と第２領域が交互に形成された方向に対して非直交方向に伸び、かつ、第２導電型不純物を添加した領域が露出する深さまで達するトレンチを形成する工程を採用してもよい。
【００２３】
【発明の実施の形態】本発明の実施例の半導体装置について説明する前に、図１に示す従来の半導体装置について行ったシミュレーションの内容と結果を説明する。
図７は、従来の半導体装置としてシミュレーションを行った構造の斜視図を示す。シミュレーションは、スーパージャンクション構造部２３の繰返しの最小単位（ハーフセル）で行った。基板２２はｎ＋型シリコン基板を用いた。ｐ型コラム領域２４及びｎ型コラム領域２６の幅は２μｍとした。ｐ型コラム領域２４の奥行方向の長さは１．５μｍ、不純物濃度は１×１０１６ｃｍ−３とした。ｎ型コラム領域２６の奥行方向の長さは０．５μｍ、不純物濃度は３×１０１６ｃｍ−３とした。スーパージャンクション構造部２３の深さは、耐圧２００Ｖを想定して１２μｍとした。ｐ型ボディ領域３０は１×１０１７ｃｍ−３の表面濃度を持ち、２μｍの深さまでガウス分布を持つようにした。ｎ型ソース領域３２とｐ＋型ボディコンタクト領域３０ａの厚さは共に０．５μｍ、不純物濃度は共に１×１０１９ｃｍ−３とした。ゲート電極３６の幅は０．３μｍ、深さは２．５μｍとした。ゲート絶縁膜３４の厚さは０．１μｍとした。
【００２４】
図８（Ａ）は図７のＡ−Ａ断面図、即ちｎ型コラム領域２６のオン時の電流分布を示す。図８（Ｂ）は図７のＢ−Ｂ断面図、即ちｐ型コラム領域２４のオン時の電流分布を示す。図８（Ｃ）は図７のＣ−Ｃ断面図、即ちｐ型コラム領域２４のオン時の電流分布を示す。図９（Ａ）〜（Ｃ）はそれぞれ、図８（Ａ）〜（Ｃ）のゲート電極３６付近の拡大図である。
この時のバイアス条件は、ソース電圧（ＶＳ）＝０Ｖ、ドレイン電圧（ＶＤ）＝０．１Ｖ、ゲート電圧（ＶＧ）＝１５Ｖとした。
【００２５】
図８と図９において、色が濃くなっている箇所が電流の流れている箇所である。色が濃くなるにつれて（黒色に近づくにつれて）、電流密度が高くなっている。但し、ゲート絶縁膜３４の部分は除く。
図８（Ａ）から、ｎ＋型ドレイン領域２２を流れ出た電流は、ｎ型コラム領域２６を通り、さらに、ゲート電極３６に隣合うｐ型ボディ領域３０に形成されたチャネルを経由して、ｎ＋型ソース領域３２へ流れていることがわかる。
図８（Ｂ）（Ｃ）と図９（Ｂ）（Ｃ）から、ｎ型コラム領域２６を流れる電流は、ｎ型コラム領域２６の直上のｐ型ボディ領域（但し、ゲート電極３６の側面に隣接した領域）３０だけでなく、ｐ型コラム領域２４の直上のｐ型ボディ領域のゲート電極３６の側面に隣接した領域３０にも流れていることがわかる。この結果から、ｐ型コラム領域２４とｎ型コラム領域２６がゲート電極３６の奥行方向と非平行に（この例では直交して）伸びている構造では、ｐ型ボディ領域３０（ゲート電極３６）の下方のスーパージャンクション構造部２３の導電型に関係なく、ｐ型ボディ領域３０のゲート電極３６の側面に隣接した領域にチャネルが形成され、電流が流れていることがわかる。
また、図９（Ｂ）（Ｃ）から明らかなように、ゲート電極３６の底面に隣接するｐ型コラム領域２４の上部（頂部）にも反転層が形成され、電流が流れていることがわかる。
しかし、ｎ型コラム領域２６を流れる電流の密度と、ゲート電極３６の底面に隣接するｐ型コラム領域２４の反転層を流れる電流の密度を比較すると、ｐ型コラム領域２４の反転層の方が電流の密度が少ないことがわかる。これが、オン抵抗の増加の要因となっていることがわかる。
【００２６】
図１０は、図７に示す構造のオン時のゲート電圧（ＶＧ）−ドレイン電流（ＩＤ）特性を示す。このときのバイアス条件は、ソース電圧（ＶＳ）＝０Ｖ、ドレイン電圧（ＶＤ）＝０．１Ｖである。図１０に示す特性から、ゲート電圧（ＶＧ）＝１５Ｖのときの規格化オン抵抗（Specific On resistance:Ｒon）を求めると、０．１６Ω・ｍｍ２であった。なお、耐圧は２２５Ｖであった。
【００２７】
図１１は、本発明の第１実施例の半導体装置の斜視図を示す。本実施例で説明する半導体装置は、トレンチゲート構造を有するパワーＭＯＳＦＥＴである。この半導体装置は、半導体部２１を備えている。半導体部２１は、ｎ＋型ドレイン領域２２と、ドリフト領域と、ｐ型ボディ領域３０と、ｎ＋型ソース領域３２を有する。ドリフト領域は、スーパージャンクション構造部２３と、ｎ型領域（第３領域の一例）２８を有する。スーパージャンクション構造部２３は、ｐ型コラム領域（第１領域の一例）２４とｎ型コラム領域（第２領域の一例）２６を有する。半導体部２１には、トレンチ３３が形成されている。このトレンチ３３の壁面（底面と側面）に沿って、ゲート絶縁膜３４が形成されている。トレンチ３３内には、ゲート電極３６が形成されている。ゲート電極３６はゲート端子に接続されている。なお、トレンチ３３の形状は、Ｕ型でもよいし、Ｖ型でもよいし、その他の形状であってもよい。
【００２８】
スーパージャンクション構造部２３のｐ型コラム領域２４とｎ型コラム領域２６は、ｎ＋型ドレイン領域２２とｐ型ボディ領域３０の間に位置している。ｐ型コラム領域２４とｎ型コラム領域２６は、ｎ＋型ドレイン領域２２に接している。ｐ型コラム領域２４とｎ型コラム領域２６は、ｐ型ボディ領域３０に接している。ｐ型コラム領域２４とｎ型コラム領域２６は、平面視したときにゲート電極３６の奥行方向（長手方向ともいえる）に対して非平行方向（この例では直交方向）に伸びている。ｐ型コラム領域２４とｎ型コラム領域２６は、同じ方向にストライプ状に伸びている。別の表現をすると、ｐ型コラム領域２４とｎ型コラム領域２６は、平面視したときにゲート電極３６の奥行方向に対して非直交方向（この例では平行方向）に交互に繰返し形成されている。
【００２９】
ｐ型コラム領域２４とｎ型コラム領域２６は接している。ｐ型コラム領域２４とｎ型コラム領域２６は、ゲート電極３６の下方に位置する領域を有する。ｐ型コラム領域２４とｎ型コラム領域２６は、ゲート電極３６の下方において、ゲート電極３６の奥行方向に平行な方向に交互に繰返し形成された領域を有する。ｐ型コラム領域２４はオフ状態で実質的に完全空乏化する。ｎ型コラム領域２６はオン状態でドリフト電流が流れ、オフ状態で実質的に完全空乏化する。
なお、ｐ型コラム領域２４とｎ型コラム領域２６は、接していなくてもよい。例えばｐ型コラム領域２４とｎ型コラム領域２６の間に絶縁層が介在していてもよい。
【００３０】
ｎ型領域２８は、ゲート電極３６とｐ型コラム領域２４の間に形成されている。この例では、ｎ型領域２８は、ゲート電極３６の底面とｐ型コラム領域２４の頂面の間に形成されている。
ｎ型領域２８の不純物濃度は、ｐ型コラム領域２４の不純物濃度よりも高く設定することが好ましい。ｎ型領域２８の不純物濃度は、１×１０１７ｃｍ−３〜１×１０１９ｃｍ−３であることが好ましい。ｎ型領域２８の厚さは、チャネルの厚さ以上に設定することが好ましい。ｎ型領域２８の厚さは、０．１μｍ〜０．５μｍであることが好ましい。
ｎ型領域２８の不純物濃度は、ｐ型コラム領域２４及び／又はｎ型コラム領域２６の不純物濃度よりも高く設定すると、オン抵抗を効果的に低減できる。
【００３１】
ｐ型ボディ領域３０は、ｎ＋型ソース領域３２に接している。ｐ型ボディ領域３０は、ゲート電極３６にゲート絶縁膜３４を介して隣合う領域を有する。この領域は、ｎ＋型ソース領域３２とスーパージャンクション構造部２３の間に形成されている。この領域にはチャネルが形成される。
ｎ＋型ドレイン領域２２の底面には、ドレイン電極２０が接続されている。ドレイン電極２０はドレイン端子に接続されている。ｎ＋型ソース領域３２とｐ型ボディ領域３０（ボディコンタクト領域３０ａ）には、ソース電極（図示省略）が接続されている。ソース電極は、ソース端子に接続されている。
【００３２】
次に、第１実施例の半導体装置の動作を説明する。ｎ＋型ドレイン領域２２に正電圧を印加し、ｎ＋型ソース領域３２とｐ型ボディ領域３０（ｐ＋型ボディコンタクト領域）を接地する。この状態で、ゲート電極３６に正電圧を印加する。すると、半導体装置がオンし、ｎ＋型ドレイン領域２２からｎ＋型ソース領域３２に電流が流れる。より具体的には、ｐ型ボディ領域３０中の電子はゲート電極３６に隣接する領域に集まり、ｎ型チャネルが形成される。これにより、ｎ＋型ソース領域３２から供給される電子は、ｐ型ボディ領域３０のｎ型チャネル、ゲート電極３６の側面に隣接するｎ型コラム領域２６、ｎ型領域２８、ｎ型コラム領域２６の順に流れ、ｎ＋型ドレイン領域２２に達する。但し、ｎ＋型ソース領域３２から供給される電子の中には、ｐ型ボディ領域３０のｎ型チャネル、ゲート電極３６の側面に隣接するｐ型コラム領域２４に形成された反転層、ｎ型領域２８、ｎ型コラム領域２６の順に流れ、ｎ＋型ドレイン領域２２に達するものもある。
【００３３】
このように、第１実施例の半導体装置では、ｐ型ボディ領域３０のｎ型チャネルを流れ出た電子は、ｎ型領域２８を経由して、ｎ＋型ドレイン領域２２に達する。従来のようにｎ型領域２８がない構造では、このｎ型領域２８が位置する領域にもｐ型コラム領域２４の上部（頂部）が形成されている（図１参照）。図１の構造では、オン時にはこのｐ型コラム領域２４の上部（頂部）に反転層が形成される。この反転層は高抵抗であるため、オン抵抗を増加させる要因となる。
これに対し、第１実施例の半導体装置では、高抵抗の反転層の代わりに上記のように予めｎ型領域２８を設けている。従って、同じにゲートバイアスの場合、オン時にｐ型コラム領域２４を流れる電流を増加させることができる。よって、このようなｎ型領域２８が設けられていない場合に比べて、オン抵抗を低減できる。
【００３４】
一方、ｎ＋型ソース領域３２とｎ＋型ドレイン領域２２間の耐圧測定時には、ゲート電極３６とｎ＋型ソース領域３２の電位を０Ｖにする。また、ｎ＋型ドレイン領域２２の電位を０Ｖから徐々に上昇させる。すると、（１）ｐ型コラム領域２４とｎ型コラム領域２６のｐｎ接合部、（２）ｐ型コラム領域２４とｎ型領域２８のｐｎ接合部、及び（３）ｐ型ボディ領域３０とｎ型コラム領域２６のｐｎ接合部から、各領域２４，２６，２８，３０に空乏層が広がる。但し、ｎ型領域２８の不純物濃度が高い場合は、ｎ型領域２８には空乏層が広がりにくい。所望の耐圧時には、ｐ型コラム領域２４とｎ型コラム領域２６が実質的に完全空乏化される。即ち、ドリフト領域が実質的に完全空乏化することによって高耐圧が確保される。
【００３５】
また、先に述べたように、ｐ型コラム領域２４はｐ型ボディ領域３０に接している。ｐ型ボディ領域３０（ｐ＋型ボディコンタクト領域）は、ソース電極に接続されている。よって、ｐ型コラム領域２４はフローティングの電位状態とならない。このため、耐圧特性を安定化できる。
【００３６】
また、ｐ型コラム領域２４はｐ型ボディ領域３０に接しているので、ｐ型ボディ領域３０とｐ型コラム領域２４間の電流経路を短くできる。よって、ｎ＋型ソース領域３２とｐ型ボディ領域３０とｎ＋型ドレイン領域２２で形成されるｎｐｎ構造の寄生トランジスタのベース抵抗を低くできる。このため、この寄生トランジスタをオンさせにくくすることができる。
【００３７】
また、ｐ型コラム領域２４とｎ型コラム領域２６は、平面視したときにゲート電極３６の奥行方向に対して直交方向に伸びている。別の表現をすると、ｐ型コラム領域２４とｎ型コラム領域２６は、平面視したときにゲート電極３６の奥行方向に対して平行方向に交互に繰返し形成されている。よって、トレンチ３３を形成する際のマスクずれが生じた場合でも、オン抵抗が増加しにくい。
【００３８】
図１２は、本発明の第２実施例の半導体装置の斜視図を示す。この半導体装置は、ｎ型領域３８が、ゲート電極３６の底面とｐ型コラム領域２４の頂面の間のみならず、ゲート電極３６の側面とｐ型コラム領域２４の側面の間にも形成されている。上記の点で第１実施例の半導体装置と異なる。
【００３９】
第２実施例の半導体装置では、ゲート電極３６の側面に隣接する領域にもｎ型領域３８が形成されている。第１実施例では、このゲート電極３６の側面に隣接する領域にもｐ型コラム領域２４が形成されており、オン時にはこのｐ型コラム領域２４に反転層が形成され、電流が流れる。よって、第２実施例のようにゲート電極３６の側面に隣接する領域にもｐ型コラム領域２４に代えてｎ型領域２８を形成することで、よりオン抵抗を低減できる。
【００４０】
図１３は、本発明の実施例としてシミュレーションを行った構造の斜視図を示す。図１３に示す構造は、図７に示す構造において、ゲート電極３６の底面とｐ型コラム領域２４の頂面の間にｎ型領域２８を介在させた構造である。このｎ型領域２８の厚さは０．５μｍ、不純物濃度は１×１０１７ｃｍ−３である。その他のデバイスパラメータは、図７に示す構造と同様である。
【００４１】
図１４は、図１３に示す半導体装置のオン時の電流分布を示す。図１４に示すように、ｎ＋型ドレイン領域２２から、ｎ型コラム領域２６、ｎ型領域２８、ｐ型ボディ領域３０のチャネルを経て、ｎ＋型ソース領域３２へ電流が流れていることがわかる。
【００４２】
図１５は、図１３に示す半導体装置のオン時のゲート電圧（ＶＧ）−ドレイン電流（ＩＤ）特性を示す。バイアス条件は、図１０の場合と同様である。図１５に示す特性から求めた規格化オン抵抗（Ｒon）は０．１５Ω・ｍｍ２であった。図７に示す構造のオン抵抗（０．１６Ω・ｍｍ２）と比較すると、約６％オン抵抗が減少していることがわかる。これにより、図１３に示す構造が有効であることがわかる。
【００４３】
図７と図１３に示す構造において、スーパージャンクション構造部２３の深さは１２μｍである。これは先に述べたように耐圧２００Ｖを想定した設定した値である。耐圧はスーパージャンクション構造部２３の深さで決まる。今回対象とした半導体装置のサイズの場合、オン抵抗のうちドリフト抵抗（ドリフト領域としてのｎ型コラム領域２６の抵抗成分）は約８５％を占める。図１３に示す構造のゲート電極３６とｐ型コラム領域２４の間に設けたｎ型領域２８は、ドリフト抵抗の低減には基本的に寄与しない。このｎ型領域２８は、ドリフト抵抗以外の抵抗成分（ｐ型コラム領域２４の抵抗成分）を減少させる効果がある。
【００４４】
耐圧が低い構造では、スーパージャンクション構造部２３の深さは浅くなる。この結果、オン抵抗のうちドリフト抵抗の占める割合が減少する。換言すると、オン抵抗のうちドリフト抵抗以外の抵抗成分の占める割合が増加する。上記したように、ｎ型領域２８を設けると、このドリフト抵抗以外の抵抗成分を減少させることができる。よって、耐圧が低い構造（スーパージャンクション構造部２３の深さが浅い構造）では、ｎ型領域２８を設けることによるオン抵抗の低減効果がより顕著になる。
【００４５】
また、図１３に示す構造の耐圧は２２１Ｖであり、図１０に示す構造（耐圧２２５Ｖ）とほぼ同様の耐圧値が得られた。
【００４６】
図１６〜図１８は、本発明の実施例の半導体装置の第１製造方法の説明図を示す。図１６に示すように、ｎ＋型の半導体基板２２上に、ｐ型コラム領域２４とｎ型コラム領域２６が交互に繰返された構造（スーパージャンクション構造部）を形成する。スーパージャンクション構造部の形成方法としては種々の方法がある。例えば、斜めイオン注入法（例えばISPSD2000，p.77-80）、マルチエピタキシャル法（例えばIEDM98，p683-685）、埋込みエピタキシャル法（例えばISPSD2001，p.363-366）によって形成することができる。次に、ｐ型コラム領域２４とｎ型コラム領域２６上にｐ型半導体領域３０をエピタキシャル成長させる。
【００４７】
次に、上記のように形成されたｐ型半導体領域３０を貫通するトレンチ３３を形成する。具体的には、ｐ型半導体領域３０上にマスク４２をＣＶＤ（ChemicalVapor Deposition）法によって形成する。本実施例ではマスク材として、アンドープド・シリケート・ガラス（Undoped Silicate Glass：以下では「ＵＳＧ」という）を用いている。なお、マスク４２とｐ型半導体領域３０の間には、酸化膜４０を形成している。また、トレンチフォト工程とマスクエッチングにより、ｐ型コラム領域２４とｎ型コラム領域２６が伸びる方向に対して直交する方向に伸びるｐ型半導体領域３０をマスク４２から露出させる。
次に、露出しているｐ型半導体領域３０等をＲＩＥ等のドライエッチング（異方性エッチング）で所定深さまで除去する。この例では、この所定深さは、ｐ型の半導体領域３０を貫通して、ｐ型コラム領域２４とｎ型コラム領域２６の上部（頂部）に達するまでの深さである。これにより、トレンチ３３が形成される。
【００４８】
次に、図１７に示すように、トレンチ３３の底面に隣接するｐ型コラム領域２４とｎ型コラム領域２６に、所定深さまでｎ型不純物（ドーパント）をイオン注入する。このイオン注入は、ｐ型半導体領域３０上をマスク４２で覆ったままの状態で行う。符号３８の領域がｎ型不純物がイオン注入された領域である。このｎ型不純物の注入は、トレンチ３３の底面に垂直な方向に行う。
【００４９】
次に、図１８に示すように、熱酸化法やＣＶＤ法等によってトレンチ３３の壁面に沿ってゲート絶縁膜３４を形成する。次に、ＣＶＤ法等によってトレンチ３３内に電極材料（ポリシリコン等）３６を積層する。次に、ｐ型半導体領域３０の上部のうち、トレンチ３３の側面に近い側の領域にｎ型不純物をイオン注入する。この領域は、ｎ＋型ソース領域３２となる。また、ｐ型半導体領域３０の上部のうち、ｎ型不純物をイオン注入した領域に隣合う領域にｐ型不純物をイオン注入する。この領域は、ｐ＋型ボディコンタクト領域３０ａとなる。
【００５０】
次に、熱処理工程（アニール工程）を行う。これにより、イオン注入された不純物が活性化される。また、トレンチ３３の底面に隣接する領域にイオン注入したｎ型不純物３８が広がる。そして、このｎ型領域３８は、図１８に示すように、トレンチ３３の底面部を覆うような形状（即ち、図１２に示す第２実施例のｎ型領域３８の形状）となる。
以上のような製造工程を経て、本発明の実施例の半導体装置が製造される。
【００５１】
この製造方法では、図１６に示すトレンチ３３が形成される前の状態の半導体層を加工する。即ち、ｐ型コラム領域２４とｎ型コラム領域２６上にｐ型半導体領域３０をエピタキシャル成長させた状態の半導体層を加工する。
このように、ｐ型コラム領域２４とｎ型コラム領域２６上に半導体領域３０が形成された半導体層を加工する場合でも、この製造方法によると、ｐ型コラム領域２４とｎ型コラム領域２６の上部（頂部）に効率的な方法でｎ型領域３８を形成できる。また、この製造方法によると、ｎ型領域３８を形成する際には、トレンチ３３の形成の際のマスク４２（図１６，図１７参照）を利用できる。よって、新たにマスクを追加しなくてもよい。このため、製造工程を簡単化できる。
【００５２】
図１９と図２０は、本発明の実施例の半導体装置の第２製造方法の説明図を示す。第１製造方法と同様にしてトレンチ３３等を形成した後、図１９に示すように、熱酸化法やＣＶＤ法等によってトレンチ３３の壁面（側面と底面）に沿って酸化膜４４を形成する。次に、その酸化膜４４を覆うようにＣＶＤ法等によって窒化膜４６を形成する。次に、トレンチ３３の底面部に位置する酸化膜４４と窒化膜４６をＲＩＥ（Reactive Ion Etching）法等でエッチングして除去する。この結果、トレンチ３３の側面部のみに酸化膜４４と窒化膜４６が形成された状態となる。次に、図２０に示すように、第１製造方法の場合と同様にして、ｎ型不純物をイオン注入してｎ型領域３８を形成する。次に、トレンチ３３の側面部の酸化膜４４と窒化膜４６を除去する。次に、第１製造方法の場合と同様に、ゲート絶縁膜の形成等の工程を行う。
【００５３】
ｎ型領域３８を形成するためのｎ型不純物のイオン注入角度がトレンチ３３の底面に垂直な方向からずれて、トレンチ底面に対し斜め方向となる場合がある。この場合、トレンチ３３の側面に隣合うｐ型半導体領域３０が露出した状態であると、その半導体領域３０にｎ型不純物が注入されてしまう場合が生じる。トレンチ３３の側面に隣接するｐ型半導体領域３０にはチャネルが形成される。このチャネルが形成される領域にｎ型不純物が侵入すると、ゲートしきい値電圧の変動等が生じるおそれがある。これに対し、上記製造方法では、トレンチ３３の側面を覆う酸化膜４４と窒化膜４６を形成した後にｎ型不純物のイオン注入を行う。この結果、これらの酸化膜４４と窒化膜４６によって、トレンチ３３の側面に隣合うｐ型半導体領域３０へのｎ型不純物の侵入をほぼ阻止できる。よって、トレンチ３３の側面に隣合う半導体領域３０にｎ型不純物が侵入することで生じるゲートしきい値電圧の変動等を抑制できる。
なお、酸化膜４４と窒化膜４６のどちらか一方のみでトレンチ３３の側面を覆うようにしても、ｎ型不純物の侵入を抑制する効果が得られる。
【００５４】
図２１と図２２は、本発明の実施例の半導体装置の第３製造方法の説明図を示す。図２１に示すように、ｐ型コラム領域２４とｎ型コラム領域２６が交互に繰返された構造（スーパージャンクション構造部）を形成する。次に、ｐ型コラム領域２４とｎ型コラム領域２６上の所定領域にマスク（レジスト）４８を塗布する。次に、トレンチフォト工程とマスクエッチングを行うことで、ｐ型コラム領域２４とｎ型コラム領域２６のうち、これらの領域２４，２６が交互に繰返し形成された方向に伸びる領域をマスク４８から露出させる。次に、この露出した領域から所定深さまでｎ型不純物をイオン注入する。これにより、ｎ型領域３８が形成される。次に、熱処理を行ってｎ型領域３８のｎ型不純物を活性化させる。次に、図２２に示すように、ｐ型コラム領域２４とｎ型コラム領域２６上にｐ型半導体領域３０をエピタキシャル成長させる。次に、第１製造方法と同様にして、トレンチ３３の形成等の工程を経て、本発明の実施例の半導体装置を製造する。
【００５５】
以上、本発明の具体例を詳細に説明したが、これらは例示に過ぎず、特許請求の範囲を限定するものではない。特許請求の範囲に記載の技術には、以上に例示した具体例を様々に変形、変更したものが含まれる。
また、本明細書または図面に説明した技術要素は、単独であるいは各種の組合せによって技術的有用性を発揮するものであり、出願時請求項記載の組合せに限定されるものではない。また、本明細書または図面に例示した技術は複数目的を同時に達成し得るものであり、そのうちの一つの目的を達成すること自体で技術的有用性を持つものである。
【図面の簡単な説明】
【図１】従来の第１の半導体装置の斜視図を示す。
【図２】従来の第２の半導体装置の斜視図を示す。
【図３】第２態様においてトレンチを形成する際のマスクずれが生じなかった場合の説明図を示す。
【図４】第２態様においてトレンチを形成する際のマスクずれが生じた場合の説明図を示す。
【図５】従来の第３の半導体装置の斜視図を示す。
【図６】従来の第４の半導体装置の斜視図を示す。
【図７】従来の第１の半導体装置としてシミュレーションを行った構造の斜視図を示す。
【図８】（Ａ）は図７のＡ−Ａ線断面図のオン時の電流分布を示す。（Ｂ）は図７のＢ−Ｂ線断面図のオン時の電流分布を示す。（Ｃ）は図７のＣ−Ｃ線断面図のオン時の電流分布を示す。
【図９】（Ａ）は図７のＡ−Ａ線断面図の部分拡大図のオン時の電流分布を示す。（Ｂ）は図７のＢ−Ｂ線断面図の部分拡大図のオン時の電流分布を示す。（Ｃ）は図７のＣ−Ｃ線断面図の部分拡大図のオン時の電流分布を示す。
【図１０】図７に示す半導体装置のオン時のゲート電圧（ＶＧ）−ドレイン電流（ＩＤ）特性を示す。
【図１１】本発明の第１実施例の半導体装置の斜視図を示す。
【図１２】本発明の第２実施例の半導体装置の斜視図を示す。
【図１３】本発明の実施例としてシミュレーションを行った構造の斜視図を示す。
【図１４】図１３に示す半導体装置のオン時の電流分布を示す。
【図１５】図１３に示す半導体装置のオン時のゲート電圧（ＶＧ）−ドレイン電流（ＩＤ）特性を示す。
【図１６】本発明の実施例の半導体装置の第１製造方法の説明図を示す（１）。
【図１７】本発明の実施例の半導体装置の第１製造方法の説明図を示す（２）。
【図１８】本発明の実施例の半導体装置の第１製造方法の説明図を示す（３）。
【図１９】本発明の実施例の半導体装置の第２製造方法の説明図を示す（１）。
【図２０】本発明の実施例の半導体装置の第２製造方法の説明図を示す（２）。
【図２１】本発明の実施例の半導体装置の第３製造方法の説明図を示す（１）。
【図２２】本発明の実施例の半導体装置の第３製造方法の説明図を示す（２）。
【符号の説明】
２０：ドレイン電極
２１：半導体部
２２：ｎ＋型ドレイン領域
２３：スーパージャンクション構造部
２４：ｐ型コラム領域（第１領域の一例）
２６：ｎ型コラム領域（第２領域の一例）
２８：ｎ型領域（第３領域の一例）
３０：ｐ型ボディ領域
３２：ｎ＋型ソース領域
３４：ゲート絶縁膜
３６：ゲート電極[0001]
The present invention relates to a semiconductor device and a method for manufacturing the same.
[0002]
[Prior Art and Problems to be Solved by the Invention]
[Patent Document 1]
Japanese Patent Application Laid-Open No. 9-26631 (FIGS. 7 to 9 in the drawings of the publication)
[Patent Document 2]
Japanese Patent Application Laid-Open No. 2000-260984 (FIGS. 1 and 4 in the drawings of the publication)
[0003]
Patent Document 1 discloses a power MOSFET in which a so-called super junction structure 23 is provided in a drift region as shown in FIG. In the super junction structure portion 23, p-type column regions 24 and n-type column regions 26 are formed alternately.
By providing the super junction structure portion 23 in the drift region, the trade-off relationship between the on-resistance and the withstand voltage between the source and the drain can be improved as compared with the case where the drift region is only the n-type region.
[0004]
In the structure of FIG. 1, the p-type column region 24 and the n-type column region 26 extend in a non-parallel direction (in this example, orthogonal direction) with respect to the depth direction of the gate electrode 36 when viewed in plan. In other words, the p-type column regions 24 and the n-type column regions 26 are alternately formed in a non-orthogonal direction (parallel direction in this example) with respect to the depth direction of the gate electrode 36 when viewed in plan. . These embodiments are hereinafter referred to as “first embodiment”.
On the other hand, as shown in FIG. 2, there is a structure in which the p-type column region 24 and the n-type column region 26 extend in a direction parallel to the depth direction of the gate electrode 36 when viewed in plan. In other words, there is a structure in which the p-type column regions 24 and the n-type column regions 26 are alternately formed in a direction orthogonal to the depth direction of the gate electrode when viewed in plan. These embodiments are hereinafter referred to as “second embodiment”.
In the first mode, even when a mask shift occurs when the trench 33 is formed (for example, when the mask shifts in the horizontal direction in the drawing), a change in a region where the gate electrode 36 and the n-type column region 26 overlap is small. Therefore, there is an advantage that the change in the on-resistance is small as compared with the second mode.
[0005]
In the case of the second aspect, when the mask used for forming the trench 33 is shifted in the horizontal direction in the drawing, the on-resistance is likely to increase. In the second embodiment, it is assumed that the trench 33 was originally formed at the position shown in FIG. In the case of FIG. 3, when the semiconductor device is turned on, a channel 30x is formed in the body region 30 adjacent to the gate electrode. On the other hand, in the case of FIG. 4, in addition to the channel 30x, a channel (inversion layer) is formed also in the portion 24x of the p-type region where the channel was not originally planned to be formed. The inversion layer 24x has a higher resistance than the 30x portion. Therefore, the on-resistance increases.
On the other hand, according to the first mode illustrated in FIG. 1, even when the above-described mask shift occurs, the on-resistance does not easily increase.
[0006]
Patent Document 2 discloses that, as shown in FIG. 5, the entire area between the bottom surface of the body region 30 and the top surface of the super junction structure portion 23 has n − The structure provided with the mold region 50 is shown. Such n − Patent Document 2 describes that the provision of the mold region 50 can reduce the on-resistance.
[0007]
However, according to the structure shown in FIG. 5, the p-type column region 24 has a floating potential state. When the p-type column region 24 is in a floating potential state, a sufficient voltage is not applied to the pn junction between the p-type column region 24 and the n-type column region 26 to deplete these regions 24 and 26 during withstand voltage. Occurs. As a result, there is a case where the breakdown voltage characteristics become unstable.
[0008]
In Patent Document 2, as shown in FIG. 6, a p-type connection region 58 for connecting a rear top surface of a p-type column region 54 and a rear surface of a p-type body region 30 is provided at the rear of the semiconductor device. The structure is shown. According to this structure, p-type column region 54 can be prevented from being in a floating potential state.
[0009]
However, when the connection region 58 is provided between the p-type body region 30 and the p-type column region 54 in this manner, the current path between the p-type body region 30 and the p-type column region 54 becomes longer. As a result, the resistance increases as the current path becomes longer. This gives n + Source region 32, p-type body region 30, and n + The base resistance of the npn-structure parasitic transistor formed by the drain region 22 is increased. Therefore, the parasitic transistor is easily turned on.
[0010]
An object of the present invention is to solve the following problems of a semiconductor device.
(1) It is difficult to increase the on-resistance even if a mask shift occurs when forming a trench.
(2) To reduce on-resistance.
(3) To stabilize the breakdown voltage characteristics.
(4) To make it difficult to turn on a parasitic transistor.
[0011]
According to the present invention, there is provided a semiconductor device having a semiconductor portion having a trench, a gate insulating film formed along a wall surface of the trench, and a semiconductor device formed in the trench. A gate electrode is provided. The semiconductor unit has a body region of the first conductivity type, a first region of the first conductivity type, a second region of the second conductivity type, and a third region of the second conductivity type. The body region has a region adjacent to the gate electrode via a gate insulating film. The first region extends in a non-parallel direction with respect to the depth direction of the gate electrode when viewed in plan, and is in contact with the body region. The second region extends in a non-parallel direction with respect to the depth direction of the gate electrode when viewed in plan, and is adjacent to the first region. The third region is formed between the gate electrode and the first region.
Here, the first region and the second region may be in contact with each other, or, for example, an insulating layer may be interposed between the first region and the second region.
[0012]
Another semiconductor device according to the present invention includes a semiconductor portion having a trench, a gate insulating film formed along a wall surface of the trench, and a gate electrode formed in the trench. The semiconductor unit has a body region of the first conductivity type, a first region of the first conductivity type, a second region of the second conductivity type, and a third region of the second conductivity type. The body region has a region adjacent to the gate electrode via a gate insulating film. The first region and the second region are alternately formed in a direction orthogonal to the depth direction of the gate electrode when viewed in a plan view. The third region is formed between the gate electrode and the first region.
[0013]
As a result of the research, the inventor has obtained new findings regarding the embodiment (first embodiment) illustrated in FIG. Specifically, it has been found that when the semiconductor device is turned on, a current flows not only in the n-type column region 26 but also in a region of the p-type column region 24 adjacent to the gate electrode 36 (FIGS. 7 to 10). With reference to the contents described in the Examples section). In the structure shown in FIG. 1, an inversion layer is formed in a region of p-type column region 24 adjacent to gate electrode 36, and a current flows. Since the inversion layer has high resistance, it causes an increase in on-resistance.
From the above findings, the present inventor has provided an n-type region (an example of the third region) instead of the high-resistance inversion layer between the gate electrode 36 and the p-type column region 24 in FIG. It has been found that the on-resistance can be reduced.
In addition, the present inventor has found that the on-resistance can be reduced without providing the n-type region 50 entirely between the p-type body region 30 and the p-type column region 24 as in the structure of FIG. . That is, it has been found that even in a structure in which the p-type column region 24 is in direct contact with the p-type body region 30, the on-resistance can be effectively reduced.
[0014]
(1) In the semiconductor device according to the present invention, the first region and the second region extend in a non-parallel direction to the depth direction of the gate electrode when viewed in plan. Alternatively, the first region and the second region are alternately formed in a direction orthogonal to the depth direction of the gate electrode when viewed in a plan view. Therefore, even when the mask is displaced when forming the trench, the on-resistance hardly increases.
(2) The semiconductor device according to the present invention has a third region formed between the gate electrode and the first region. Therefore, the on-resistance can be further reduced as described above.
(3) In the semiconductor device according to the present invention, the first region of the first conductivity type is in contact with the body region of the first conductivity type. Therefore, it is possible to prevent the first region from being in a floating potential state. Therefore, the breakdown voltage characteristics can be stabilized.
(4) In the semiconductor device according to the present invention, the first region is in contact with the body region. Therefore, the current path between the first region and the body region can be shortened. Therefore, it is possible to make it difficult to turn on the parasitic transistor in the semiconductor device.
[0015]
The first region and the second region preferably extend in a direction substantially orthogonal to the depth direction of the gate electrode when viewed in a plan view. It is preferable that the first region and the second region are alternately formed in a direction substantially parallel to a depth direction of the gate electrode when viewed in plan.
[0016]
Preferably, the first region has a region located below the gate electrode, and the third region has a region formed between a bottom surface of the gate electrode and a top surface of the first region. Further, the third region preferably has a region formed between the side surface of the gate electrode and the first region.
According to this, the on-resistance can be reduced more effectively.
[0017]
It is preferable that the impurity concentration of the third region is higher than the impurity concentration of the first region and / or the second region.
According to this, the on-resistance can be further reduced while suppressing the decrease in the withstand voltage.
[0018]
The semiconductor section preferably has a first conductivity type drain region in contact with the first region and / or the second region. The semiconductor section preferably has a source region of the second conductivity type in contact with the body region.
It is preferable that the first region and the second region are formed between the body region and the drain region. It is preferable that the first region and the second region extend in a stripe shape in substantially the same direction. Preferably, the first region is substantially completely depleted in the off state. It is preferable that a current flows in the second region in the on state and that the second region is substantially completely depleted in the off state.
[0019]
The method of manufacturing a semiconductor device according to the present invention includes the steps of: removing at least a portion of the semiconductor region on the first region of the first conductivity type and the second region of the second conductivity type; Forming a trench extending in a non-parallel direction to a direction in which the second region extends and reaching a depth where the first region and the second region are exposed; and forming a second conductive layer in the first region adjacent to the bottom surface of the trench. A step of adding a mold impurity. This manufacturing method preferably further includes a step of activating the second conductivity type impurity.
Instead of the trench forming step, at least a part of the semiconductor region on the first region of the first conductivity type and the semiconductor region on the second region of the second conductivity type is removed, and the first region and the second region are viewed in plan. May be formed in a non-orthogonal direction to the direction in which the first and second regions are alternately formed.
According to this manufacturing method, even when a semiconductor region exists on the first region and the second region, the second conductivity type impurity can be added to the first region by an efficient method.
[0020]
In the step of forming a trench, a region of the semiconductor region where the trench is not formed is covered with a mask, the region not covered with the mask is removed to form a trench, and in the step of adding a second conductivity type impurity, the semiconductor region is formed. Is preferably added with the second conductivity type while the mask is covered with the mask.
According to this, it is not necessary to add a new mask in order to add the second conductivity type impurity. Therefore, the manufacturing process can be simplified.
[0021]
It is preferable that the method further includes a step of covering the side surface of the trench with a mask for suppressing intrusion of the second conductivity type impurity into the semiconductor region adjacent to the side surface of the trench.
According to this, it is possible to suppress a change in the gate threshold voltage and the like caused by the second conductivity type impurity penetrating into the semiconductor region adjacent to the side surface of the trench.
[0022]
Another method for manufacturing a semiconductor device includes a step of disposing a mask having an opening on a predetermined region including the first region on the first region of the first conductivity type and the second region of the second conductivity type; Adding a second conductivity type impurity to a predetermined region, forming a semiconductor region on the first region and the second region, and removing at least a part of the semiconductor region to form a first region and a second region. Forming a trench extending in a non-parallel direction to the extension direction and reaching a depth at which the region to which the second conductivity type impurity is added is exposed.
Instead of the trench forming step, at least a part of the semiconductor region is removed, and extends in a non-perpendicular direction to a direction in which the first region and the second region are alternately formed when viewed in plan, and A step of forming a trench reaching a depth where the region to which the two-conductivity-type impurity is added is exposed may be employed.
[0023]
DESCRIPTION OF THE PREFERRED EMBODIMENTS Before describing a semiconductor device according to an embodiment of the present invention, the contents and results of a simulation performed on the conventional semiconductor device shown in FIG. 1 will be described.
FIG. 7 is a perspective view of a structure obtained by performing a simulation as a conventional semiconductor device. The simulation was performed in the minimum unit (half cell) of the repetition of the super junction structure portion 23. The substrate 22 is n + A silicon substrate was used. The width of the p-type column region 24 and the n-type column region 26 was 2 μm. The length in the depth direction of the p-type column region 24 is 1.5 μm, and the impurity concentration is 1 × 10 16 cm -3 And The length of the n-type column region 26 in the depth direction is 0.5 μm, and the impurity concentration is 3 × 10 16 cm -3 And The depth of the super junction structure 23 was 12 μm assuming a withstand voltage of 200 V. The p-type body region 30 is 1 × 10 17 cm -3 And a Gaussian distribution up to a depth of 2 μm. n-type source region 32 and p + Both the thickness of the mold body contact region 30a is 0.5 μm and the impurity concentration is 1 × 10 19 cm -3 And The width of the gate electrode 36 was 0.3 μm and the depth was 2.5 μm. The thickness of the gate insulating film 34 was 0.1 μm.
[0024]
FIG. 8A is a sectional view taken along line AA of FIG. 7, that is, a current distribution when the n-type column region 26 is turned on. FIG. 8B is a sectional view taken along line BB of FIG. 7, that is, a current distribution when the p-type column region 24 is turned on. FIG. 8C is a cross-sectional view taken along the line CC of FIG. 7, that is, a current distribution when the p-type column region 24 is turned on. FIGS. 9A to 9C are enlarged views of the vicinity of the gate electrode 36 in FIGS. 8A to 8C, respectively.
The bias condition at this time is that the source voltage (V S ) = 0 V, drain voltage (V D ) = 0.1 V, gate voltage (V G ) = 15V.
[0025]
In FIGS. 8 and 9, a portion where the color is dark is a portion where a current flows. As the color becomes darker (closer to black), the current density becomes higher. However, the portion of the gate insulating film 34 is excluded.
From FIG. 8A, n + The current flowing out of the p-type drain region 22 passes through the n-type column region 26, and further passes through a channel formed in the p-type body region 30 adjacent to the gate electrode 36. + It can be seen that the current flows to the mold source region 32.
From FIGS. 8B and 9C and FIGS. 9B and 9C, the current flowing through the n-type column region 26 is changed to the p-type body region immediately above the n-type column region 26 (provided that the side surface of the gate electrode 36 It can be seen that the current flows not only in the region 30 adjacent to the p-type column region 24 but also in the region 30 adjacent to the side surface of the gate electrode 36 in the p-type body region immediately above the p-type column region 24. From this result, in a structure in which the p-type column region 24 and the n-type column region 26 extend in a direction non-parallel to (in this example, perpendicular to) the depth direction of the gate electrode 36, the p-type body region 30 (the gate electrode 36) It can be seen that a channel is formed in the region adjacent to the side surface of the gate electrode 36 in the p-type body region 30 and current flows regardless of the conductivity type of the super junction structure portion 23 below the super junction structure 23.
Further, as apparent from FIGS. 9B and 9C, an inversion layer is also formed on the top (top) of the p-type column region 24 adjacent to the bottom surface of the gate electrode 36, and a current flows. .
However, comparing the density of the current flowing in the n-type column region 26 with the density of the current flowing in the inversion layer of the p-type column region 24 adjacent to the bottom surface of the gate electrode 36, the inversion layer of the p-type column region 24 is It can be seen that the current density is low. It can be seen that this is the cause of the increase in on-resistance.
[0026]
FIG. 10 shows a gate voltage (V) when the structure shown in FIG. G ) -Drain current (I D ) Shows the characteristics. The bias condition at this time is that the source voltage (V S ) = 0 V, drain voltage (V D ) = 0.1V. From the characteristics shown in FIG. 10, the gate voltage (V G ) = 15V, the standardized on resistance (Ron) is 0.16Ω · mm 2 Met. The withstand voltage was 225V.
[0027]
FIG. 11 is a perspective view of the semiconductor device according to the first embodiment of the present invention. The semiconductor device described in this embodiment is a power MOSFET having a trench gate structure. This semiconductor device includes a semiconductor unit 21. The semiconductor unit 21 has n + Drain region 22, drift region, p-type body region 30, + It has a mold source region 32. The drift region has a super junction structure portion 23 and an n-type region (an example of a third region) 28. The super junction structure 23 has a p-type column region (an example of a first region) 24 and an n-type column region (an example of a second region) 26. A trench 33 is formed in the semiconductor section 21. A gate insulating film 34 is formed along the wall surfaces (bottom and side surfaces) of the trench 33. A gate electrode 36 is formed in the trench 33. The gate electrode 36 is connected to a gate terminal. The shape of the trench 33 may be U-shaped, V-shaped, or another shape.
[0028]
The p-type column region 24 and the n-type column region 26 of the super junction structure 23 + It is located between the p-type body region 30 and the p-type drain region 22. The p-type column region 24 and the n-type column region 26 + In contact with the mold drain region 22. P-type column region 24 and n-type column region 26 are in contact with p-type body region 30. The p-type column region 24 and the n-type column region 26 extend in a non-parallel direction (orthogonal direction in this example) with respect to a depth direction (a longitudinal direction) of the gate electrode 36 when viewed in plan. The p-type column region 24 and the n-type column region 26 extend in a stripe shape in the same direction. In other words, the p-type column regions 24 and the n-type column regions 26 are alternately formed in a non-orthogonal direction (parallel direction in this example) with respect to the depth direction of the gate electrode 36 when viewed in plan. I have.
[0029]
The p-type column region 24 and the n-type column region 26 are in contact. The p-type column region 24 and the n-type column region 26 have regions located below the gate electrode 36. The p-type column region 24 and the n-type column region 26 have regions below the gate electrode 36 that are alternately and repeatedly formed in a direction parallel to the depth direction of the gate electrode 36. The p-type column region 24 is substantially completely depleted in the off state. A drift current flows in the n-type column region 26 in the on state, and is substantially completely depleted in the off state.
The p-type column region 24 and the n-type column region 26 need not be in contact with each other. For example, an insulating layer may be interposed between the p-type column region 24 and the n-type column region 26.
[0030]
The n-type region 28 is formed between the gate electrode 36 and the p-type column region 24. In this example, the n-type region 28 is formed between the bottom surface of the gate electrode 36 and the top surface of the p-type column region 24.
It is preferable that the impurity concentration of n-type region 28 be set higher than that of p-type column region 24. The impurity concentration of the n-type region 28 is 1 × 10 17 cm -3 ~ 1 × 10 19 cm -3 It is preferable that It is preferable that the thickness of the n-type region 28 is set to be equal to or greater than the thickness of the channel. It is preferable that the thickness of the n-type region 28 be 0.1 μm to 0.5 μm.
When the impurity concentration of the n-type region 28 is set higher than the impurity concentration of the p-type column region 24 and / or the n-type column region 26, the on-resistance can be effectively reduced.
[0031]
The p-type body region 30 is + It is in contact with the mold source region 32. The p-type body region 30 has a region adjacent to the gate electrode 36 via the gate insulating film 34. This region is n + It is formed between the mold source region 32 and the super junction structure 23. A channel is formed in this region.
n + The drain electrode 20 is connected to the bottom of the mold drain region 22. The drain electrode 20 is connected to a drain terminal. n + A source electrode (not shown) is connected to the type source region 32 and the p-type body region 30 (body contact region 30a). The source electrode is connected to the source terminal.
[0032]
Next, the operation of the semiconductor device of the first embodiment will be described. n + A positive voltage is applied to the drain region 22 and n + Source region 32 and p-type body region 30 (p + (The body contact region). In this state, a positive voltage is applied to the gate electrode 36. Then, the semiconductor device is turned on and n + Type drain region 22 to n + A current flows through the mold source region 32. More specifically, electrons in p-type body region 30 gather in a region adjacent to gate electrode 36 to form an n-type channel. This gives n + Electrons supplied from the type source region 32 flow in the order of the n-type channel of the p-type body region 30, the n-type column region 26 adjacent to the side surface of the gate electrode 36, the n-type region 28, and the n-type column region 26. + Reaches the mold drain region 22. Where n + The electrons supplied from the type source region 32 include an n-type channel of the p-type body region 30, an inversion layer formed in the p-type column region 24 adjacent to the side surface of the gate electrode 36, an n-type region 28, n Flows in the order of the mold column region 26, and n + Some reach the mold drain region 22.
[0033]
As described above, in the semiconductor device of the first embodiment, the electrons flowing out of the n-type channel of the p-type body region 30 pass through the n-type region 28 and + Reaches the mold drain region 22. In the conventional structure without the n-type region 28, the upper portion (top) of the p-type column region 24 is also formed in the region where the n-type region 28 is located (see FIG. 1). In the structure shown in FIG. 1, an inversion layer is formed above (top) the p-type column region 24 when it is turned on. Since the inversion layer has high resistance, it causes an increase in on-resistance.
On the other hand, in the semiconductor device of the first embodiment, the n-type region 28 is provided in advance as described above instead of the high-resistance inversion layer. Therefore, in the case of the same gate bias, the current flowing through the p-type column region 24 at the time of ON can be increased. Therefore, the on-resistance can be reduced as compared with the case where such n-type region 28 is not provided.
[0034]
On the other hand, n + Type source region 32 and n + When the breakdown voltage between the drain regions 22 is measured, the gate electrode 36 and n + The potential of the mold source region 32 is set to 0V. Also, n + The potential of the mold drain region 22 is gradually increased from 0V. Then, (1) a pn junction between the p-type column region 24 and the n-type column region 26, (2) a pn junction between the p-type column region 24 and the n-type region 28, and (3) a p-type body region 30 and n A depletion layer extends from the pn junction of the mold column region 26 to the regions 24, 26, 28, and 30. However, when the impurity concentration of the n-type region 28 is high, the depletion layer hardly spreads in the n-type region 28. At a desired breakdown voltage, p-type column region 24 and n-type column region 26 are substantially completely depleted. That is, a high breakdown voltage is ensured by the drift region being substantially completely depleted.
[0035]
Further, as described above, p-type column region 24 is in contact with p-type body region 30. The p-type body region 30 (p + The mold body contact region) is connected to the source electrode. Therefore, the p-type column region 24 does not enter a floating potential state. Therefore, the breakdown voltage characteristics can be stabilized.
[0036]
Further, since p-type column region 24 is in contact with p-type body region 30, the current path between p-type body region 30 and p-type column region 24 can be shortened. Therefore, n + Source region 32, p-type body region 30, and n + The base resistance of the parasitic transistor having the npn structure formed by the drain region 22 can be reduced. This makes it difficult to turn on the parasitic transistor.
[0037]
The p-type column region 24 and the n-type column region 26 extend in a direction orthogonal to the depth direction of the gate electrode 36 when viewed in plan. In other words, the p-type column region 24 and the n-type column region 26 are alternately formed in a direction parallel to the depth direction of the gate electrode 36 when viewed in plan. Therefore, even if a mask shift occurs when the trench 33 is formed, the on-resistance hardly increases.
[0038]
FIG. 12 is a perspective view of a semiconductor device according to a second embodiment of the present invention. In this semiconductor device, the n-type region 38 is formed not only between the bottom surface of the gate electrode 36 and the top surface of the p-type column region 24 but also between the side surface of the gate electrode 36 and the side surface of the p-type column region 24. ing. This is different from the semiconductor device of the first embodiment in the above points.
[0039]
In the semiconductor device of the second embodiment, an n-type region 38 is also formed in a region adjacent to the side surface of the gate electrode 36. In the first embodiment, the p-type column region 24 is also formed in a region adjacent to the side surface of the gate electrode 36. When the p-type column region 24 is turned on, an inversion layer is formed in the p-type column region 24, and a current flows. Therefore, by forming the n-type region 28 in the region adjacent to the side surface of the gate electrode 36 instead of the p-type column region 24 as in the second embodiment, the on-resistance can be further reduced.
[0040]
FIG. 13 is a perspective view of a structure simulated as an embodiment of the present invention. The structure shown in FIG. 13 differs from the structure shown in FIG. 7 in that n-type region 28 is interposed between the bottom surface of gate electrode 36 and the top surface of p-type column region 24. The thickness of the n-type region 28 is 0.5 μm and the impurity concentration is 1 × 10 17 cm -3 It is. Other device parameters are the same as in the structure shown in FIG.
[0041]
FIG. 14 shows a current distribution when the semiconductor device shown in FIG. 13 is turned on. As shown in FIG. + N channel region 26, n-type region 28, and p-type body region 30 + It can be seen that current flows to the mold source region 32.
[0042]
FIG. 15 shows the gate voltage (V) when the semiconductor device shown in FIG. 13 is turned on. G ) -Drain current (I D ) Shows the characteristics. The bias condition is the same as in FIG. The normalized on-resistance (Ron) obtained from the characteristics shown in FIG. 2 Met. The on-resistance of the structure shown in FIG. 2 ), The ON resistance is reduced by about 6%. This shows that the structure shown in FIG. 13 is effective.
[0043]
In the structure shown in FIGS. 7 and 13, the depth of the super junction structure 23 is 12 μm. This is a value set assuming a withstand voltage of 200 V as described above. The breakdown voltage is determined by the depth of the super junction structure 23. In the case of the size of the semiconductor device targeted this time, the drift resistance (the resistance component of the n-type column region 26 as the drift region) accounts for about 85% of the on-resistance. N-type region 28 provided between gate electrode 36 and p-type column region 24 having the structure shown in FIG. 13 does not basically contribute to reduction of drift resistance. The n-type region 28 has an effect of reducing a resistance component other than the drift resistance (the resistance component of the p-type column region 24).
[0044]
In a structure having a low withstand voltage, the depth of the super junction structure portion 23 is small. As a result, the proportion of the on-resistance occupied by the drift resistance decreases. In other words, the ratio of resistance components other than the drift resistance in the on-resistance increases. As described above, when the n-type region 28 is provided, a resistance component other than the drift resistance can be reduced. Therefore, in a structure having a low withstand voltage (a structure in which the depth of the super junction structure portion 23 is shallow), the effect of reducing the on-resistance by providing the n-type region 28 becomes more remarkable.
[0045]
Further, the breakdown voltage of the structure shown in FIG. 13 was 221 V, and a breakdown voltage value almost similar to that of the structure shown in FIG.
[0046]
16 to 18 are explanatory views of a first manufacturing method of the semiconductor device according to the embodiment of the present invention. As shown in FIG. + A structure (super junction structure) in which a p-type column region 24 and an n-type column region 26 are alternately repeated is formed on a semiconductor substrate 22 of a type. There are various methods for forming the super junction structure. For example, it can be formed by an oblique ion implantation method (for example, ISPSD2000, p.77-80), a multi-epitaxial method (for example, IEDM98, p683-685), or a buried epitaxial method (for example, ISPSD2001, p.363-366). Next, a p-type semiconductor region 30 is epitaxially grown on the p-type column region 24 and the n-type column region 26.
[0047]
Next, a trench 33 penetrating the p-type semiconductor region 30 formed as described above is formed. Specifically, a mask 42 is formed on the p-type semiconductor region 30 by a CVD (Chemical Vapor Deposition) method. In this embodiment, undoped silicate glass (Undoped Silicate Glass: hereinafter referred to as “USG”) is used as a mask material. Note that an oxide film 40 is formed between the mask 42 and the p-type semiconductor region 30. Further, the p-type semiconductor region 30 extending in a direction orthogonal to the direction in which the p-type column region 24 and the n-type column region 26 extend is exposed from the mask 42 by a trench photo process and mask etching.
Next, the exposed p-type semiconductor region 30 and the like are removed to a predetermined depth by dry etching (anisotropic etching) such as RIE. In this example, the predetermined depth is a depth that penetrates the p-type semiconductor region 30 and reaches the upper portion (top) of the p-type column region 24 and the n-type column region 26. Thus, a trench 33 is formed.
[0048]
Next, as shown in FIG. 17, an n-type impurity (dopant) is ion-implanted to a predetermined depth into the p-type column region 24 and the n-type column region 26 adjacent to the bottom surface of the trench 33. This ion implantation is performed with the mask 42 covering the p-type semiconductor region 30. A region indicated by reference numeral 38 is a region into which an n-type impurity is ion-implanted. This implantation of the n-type impurity is performed in a direction perpendicular to the bottom surface of the trench 33.
[0049]
Next, as shown in FIG. 18, a gate insulating film 34 is formed along the wall surface of the trench 33 by a thermal oxidation method, a CVD method, or the like. Next, an electrode material (polysilicon or the like) 36 is laminated in the trench 33 by a CVD method or the like. Next, an n-type impurity is ion-implanted into a region near the side surface of the trench 33 in the upper portion of the p-type semiconductor region 30. This region is n + This becomes the mold source region 32. In addition, a p-type impurity is ion-implanted into a region adjacent to the region into which the n-type impurity has been ion-implanted, above the p-type semiconductor region 30. This region is p + It becomes the mold body contact region 30a.
[0050]
Next, a heat treatment step (annealing step) is performed. Thereby, the ion-implanted impurities are activated. Further, the n-type impurity 38 implanted in the region adjacent to the bottom surface of the trench 33 spreads. As shown in FIG. 18, the n-type region 38 has a shape covering the bottom of the trench 33 (that is, the shape of the n-type region 38 of the second embodiment shown in FIG. 12).
Through the above manufacturing steps, the semiconductor device according to the embodiment of the present invention is manufactured.
[0051]
In this manufacturing method, the semiconductor layer in a state before the trench 33 shown in FIG. 16 is formed is processed. That is, the semiconductor layer in a state where the p-type semiconductor region 30 is epitaxially grown on the p-type column region 24 and the n-type column region 26 is processed.
As described above, even when a semiconductor layer in which the semiconductor region 30 is formed on the p-type column region 24 and the n-type column region 26 is processed, the p-type column region 24 and the n-type column region 26 The n-type region 38 can be formed on the top (top) in an efficient manner. Also, according to this manufacturing method, when forming the n-type region 38, the mask 42 (see FIGS. 16 and 17) for forming the trench 33 can be used. Therefore, it is not necessary to newly add a mask. For this reason, the manufacturing process can be simplified.
[0052]
19 and 20 are explanatory views of a second method for manufacturing a semiconductor device according to an embodiment of the present invention. After forming the trench 33 and the like in the same manner as in the first manufacturing method, as shown in FIG. 19, an oxide film 44 is formed along the wall surface (side surface and bottom surface) of the trench 33 by a thermal oxidation method, a CVD method, or the like. Next, a nitride film 46 is formed by a CVD method or the like so as to cover the oxide film 44. Next, the oxide film 44 and the nitride film 46 located on the bottom portion of the trench 33 are removed by etching by RIE (Reactive Ion Etching) or the like. As a result, the oxide film 44 and the nitride film 46 are formed only on the side surfaces of the trench 33. Next, as shown in FIG. 20, an n-type impurity is ion-implanted to form an n-type region 38 in the same manner as in the first manufacturing method. Next, the oxide film 44 and the nitride film 46 on the side surfaces of the trench 33 are removed. Next, as in the case of the first manufacturing method, steps such as formation of a gate insulating film are performed.
[0053]
In some cases, the ion implantation angle of the n-type impurity for forming the n-type region 38 is deviated from the direction perpendicular to the bottom surface of the trench 33 and is oblique to the trench bottom surface. In this case, if the p-type semiconductor region 30 adjacent to the side surface of the trench 33 is exposed, an n-type impurity may be implanted into the semiconductor region 30. A channel is formed in the p-type semiconductor region 30 adjacent to the side surface of the trench 33. When an n-type impurity penetrates into a region where the channel is formed, a change in gate threshold voltage or the like may occur. On the other hand, in the above-described manufacturing method, ion implantation of an n-type impurity is performed after forming the oxide film 44 and the nitride film 46 covering the side surfaces of the trench 33. As a result, the oxide film 44 and the nitride film 46 can substantially prevent the intrusion of the n-type impurity into the p-type semiconductor region 30 adjacent to the side surface of the trench 33. Therefore, it is possible to suppress a change in the gate threshold voltage and the like caused by the n-type impurity entering the semiconductor region 30 adjacent to the side surface of the trench 33.
Note that even if only one of the oxide film 44 and the nitride film 46 covers the side surface of the trench 33, the effect of suppressing the intrusion of the n-type impurity can be obtained.
[0054]
FIG. 21 and FIG. 22 are explanatory views of a third method of manufacturing a semiconductor device according to the embodiment of the present invention. As shown in FIG. 21, a structure (super junction structure) in which p-type column regions 24 and n-type column regions 26 are alternately repeated is formed. Next, a mask (resist) 48 is applied to predetermined regions on the p-type column region 24 and the n-type column region 26. Next, by performing a trench photo process and mask etching, a region of the p-type column region 24 and the n-type column region 26 that extends in a direction in which these regions 24 and 26 are alternately and repeatedly formed is exposed from the mask 48. Let it. Next, an n-type impurity is ion-implanted from the exposed region to a predetermined depth. As a result, an n-type region 38 is formed. Next, heat treatment is performed to activate the n-type impurities in the n-type region 38. Next, as shown in FIG. 22, a p-type semiconductor region 30 is epitaxially grown on the p-type column region 24 and the n-type column region 26. Next, in the same manner as in the first manufacturing method, the semiconductor device according to the embodiment of the present invention is manufactured through steps such as formation of the trench 33.
[0055]
As mentioned above, although the specific example of this invention was demonstrated in detail, these are only illustrations and do not limit a claim. The technology described in the claims includes various modifications and alterations of the specific examples illustrated above.
In addition, the technical elements described in the present specification or the drawings exert technical utility singly or in various combinations, and are not limited to the combinations described in the claims at the time of filing. Further, the technology exemplified in the present specification or the drawings can simultaneously achieve a plurality of objects, and has technical utility by achieving one of the objects.
[Brief description of the drawings]
FIG. 1 is a perspective view of a conventional first semiconductor device.
FIG. 2 shows a perspective view of a second conventional semiconductor device.
FIG. 3 is an explanatory view showing a case where no mask shift occurs when forming a trench in the second mode.
FIG. 4 is an explanatory view showing a case where a mask shift occurs when forming a trench in the second mode.
FIG. 5 is a perspective view of a third conventional semiconductor device.
FIG. 6 is a perspective view of a fourth conventional semiconductor device.
FIG. 7 is a perspective view of a structure obtained by performing a simulation as a conventional first semiconductor device.
FIG. 8A shows a current distribution at the time of turning on in a cross-sectional view taken along the line AA of FIG. 7; (B) shows the current distribution at the time of ON in the cross-sectional view taken along the line BB of FIG. 7. (C) shows the current distribution at the time of ON in the cross-sectional view taken along the line CC of FIG. 7.
9A shows a current distribution at the time of ON in a partially enlarged view of a cross-sectional view taken along the line AA of FIG. 7; (B) shows a current distribution at the time of ON in a partially enlarged view of a cross-sectional view taken along the line BB of FIG. 7. (C) shows a current distribution at the time of ON in a partially enlarged view of a cross-sectional view taken along line CC of FIG. 7.
10 shows a gate voltage (V) of the semiconductor device shown in FIG. G ) -Drain current (I D ) Shows the characteristics.
FIG. 11 is a perspective view of the semiconductor device according to the first embodiment of the present invention.
FIG. 12 is a perspective view of a semiconductor device according to a second embodiment of the present invention.
FIG. 13 is a perspective view of a structure simulated as an example of the present invention.
14 shows a current distribution when the semiconductor device shown in FIG. 13 is turned on.
FIG. 15 illustrates a gate voltage (V) of the semiconductor device illustrated in FIG. G ) -Drain current (I D ) Shows the characteristics.
FIG. 16 is an explanatory view of a first method for manufacturing a semiconductor device according to an example of the present invention (1).
FIG. 17 is an explanatory view of a first method for manufacturing a semiconductor device according to an example of the present invention (2).
FIG. 18 is an explanatory view (3) of the first manufacturing method of the semiconductor device according to the embodiment of the present invention;
FIG. 19 is an explanatory view of a second method for manufacturing a semiconductor device according to an example of the present invention (1).
FIG. 20 is an explanatory view (2) of a second method for manufacturing a semiconductor device according to an example of the present invention.
FIG. 21 is an explanatory view of a third method of manufacturing the semiconductor device according to the example of the present invention (1).
FIG. 22 is an explanatory view of a third method of manufacturing a semiconductor device according to an example of the present invention (2).
[Explanation of symbols]
20: drain electrode
21: Semiconductor section
22: n + Drain region
23: Super junction structure
24: p-type column region (an example of a first region)
26: n-type column region (an example of the second region)
28: n-type region (an example of a third region)
30: p-type body region
32: n + Type source area
34: Gate insulating film
36: Gate electrode

Claims (9)

トレンチが形成された半導体部と、トレンチの壁面に沿って形成されたゲート絶縁膜と、トレンチ内に形成されたゲート電極を備え、
半導体部は、第１導電型のボディ領域と、第１導電型の第１領域と、第２導電型の第２領域と、第２導電型の第３領域を有し、
ボディ領域は、ゲート電極にゲート絶縁膜を介して隣合う領域を有し、
第１領域は、平面視したときにゲート電極の奥行方向に対して非平行方向に伸びているとともにボディ領域に接しており、
第２領域は、平面視したときにゲート電極の奥行方向に対して非平行方向に伸びているとともに第１領域と隣合っており、
第３領域は、ゲート電極と第１領域の間に形成されている半導体装置。A semiconductor portion in which the trench is formed, a gate insulating film formed along the wall surface of the trench, and a gate electrode formed in the trench;
The semiconductor unit has a body region of the first conductivity type, a first region of the first conductivity type, a second region of the second conductivity type, and a third region of the second conductivity type,
The body region has a region adjacent to the gate electrode via a gate insulating film,
The first region extends in a non-parallel direction with respect to the depth direction of the gate electrode when viewed in plan, and is in contact with the body region,
The second region extends in a non-parallel direction with respect to the depth direction of the gate electrode when viewed in plan and is adjacent to the first region,
A semiconductor device in which the third region is formed between the gate electrode and the first region. 第１領域と第２領域は、平面視したときにゲート電極の奥行方向に対してほぼ直交方向に伸びている請求項１に記載の半導体装置。2. The semiconductor device according to claim 1, wherein the first region and the second region extend in a direction substantially orthogonal to a depth direction of the gate electrode when viewed in a plan view. トレンチが形成された半導体部と、トレンチの壁面に沿って形成されたゲート絶縁膜と、トレンチ内に形成されたゲート電極を備え、
半導体部は、第１導電型のボディ領域と、第１導電型の第１領域と、第２導電型の第２領域と、第２導電型の第３領域を有し、
ボディ領域は、ゲート電極にゲート絶縁膜を介して隣合う領域を有し、
第１領域と第２領域は、平面視したときにゲート電極の奥行方向に対して非直交方向に交互に形成されており、
第３領域は、ゲート電極と第１領域の間に形成されている半導体装置。A semiconductor portion in which the trench is formed, a gate insulating film formed along the wall surface of the trench, and a gate electrode formed in the trench;
The semiconductor unit has a body region of the first conductivity type, a first region of the first conductivity type, a second region of the second conductivity type, and a third region of the second conductivity type,
The body region has a region adjacent to the gate electrode via a gate insulating film,
The first region and the second region are alternately formed in a non-orthogonal direction with respect to the depth direction of the gate electrode when viewed in plan,
A semiconductor device in which the third region is formed between the gate electrode and the first region. 第１領域と第２領域は、平面視したときにゲート電極の奥行方向に対してほぼ平行方向に交互に形成されている請求項３に記載の半導体装置。4. The semiconductor device according to claim 3, wherein the first region and the second region are alternately formed in a direction substantially parallel to a depth direction of the gate electrode when viewed in a plan view. 第１領域は、ゲート電極の下方に位置する領域を有し、
第３領域は、ゲート電極の底面と第１領域の頂面の間に形成された領域を有する請求項１〜４のいずれかに記載の半導体装置。The first region has a region located below the gate electrode,
The semiconductor device according to claim 1, wherein the third region has a region formed between a bottom surface of the gate electrode and a top surface of the first region. 第３領域の不純物濃度は、第１領域及び／又は第２領域の不純物濃度よりも高い請求項１〜５のいずれかに記載の半導体装置。The semiconductor device according to claim 1, wherein an impurity concentration of the third region is higher than an impurity concentration of the first region and / or the second region. 第１導電型の第１領域と第２導電型の第２領域上の半導体領域の一部を少なくとも除去して、平面視したときに第１領域と第２領域が伸びる方向に対して非平行方向に伸び、かつ、第１領域と第２領域が露出する深さまで達するトレンチを形成する工程と、
トレンチの底面に隣接する第１領域に第２導電型不純物を添加する工程を有する半導体装置の製造方法。At least a part of the semiconductor region on the first region of the first conductivity type and the semiconductor region on the second region of the second conductivity type is removed, and is non-parallel to the direction in which the first region and the second region extend in plan view. Forming a trench extending in the direction and reaching a depth where the first region and the second region are exposed;
A method for manufacturing a semiconductor device, comprising: adding a second conductivity type impurity to a first region adjacent to a bottom surface of a trench. トレンチを形成する工程では、半導体領域のうちトレンチを形成しない領域上をマスクで覆い、マスクで覆っていない領域を除去してトレンチを形成し、
第２導電型不純物を添加する工程では、半導体領域を前記マスクで覆ったままの状態で第２導電型不純物を添加する請求項７に記載の半導体装置の製造方法。In the step of forming a trench, a region of the semiconductor region where the trench is not formed is covered with a mask, and the region not covered with the mask is removed to form a trench.
8. The method of manufacturing a semiconductor device according to claim 7, wherein in the step of adding the second conductivity type impurity, the second conductivity type impurity is added while the semiconductor region is covered with the mask. トレンチの側面に隣合う半導体領域への第２導電型不純物の侵入を抑制するマスクでトレンチの側面を覆う工程を有する請求項７又は８に記載の半導体装置の製造方法。9. The method of manufacturing a semiconductor device according to claim 7, further comprising a step of covering the side surface of the trench with a mask that suppresses penetration of a second conductivity type impurity into a semiconductor region adjacent to the side surface of the trench. 10.
JP2002367716A 2002-12-19 2002-12-19 Semiconductor device and its manufacturing method Pending JP2004200441A (en)

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