JP4735067B2 - Insulated gate semiconductor device - Google Patents

Insulated gate semiconductor device Download PDF

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JP4735067B2
JP4735067B2 JP2005174026A JP2005174026A JP4735067B2 JP 4735067 B2 JP4735067 B2 JP 4735067B2 JP 2005174026 A JP2005174026 A JP 2005174026A JP 2005174026 A JP2005174026 A JP 2005174026A JP 4735067 B2 JP4735067 B2 JP 4735067B2
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semiconductor
column
semiconductor device
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JP2006351713A (en
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秀史 高谷
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トヨタ自動車株式会社
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  The present invention relates to an insulated gate semiconductor device. More specifically, the present invention relates to an insulated gate semiconductor device having a super junction structure and improved recovery characteristics.

  Conventionally, a trench gate type semiconductor device having a trench gate structure has been proposed as an insulated gate type semiconductor device for power devices. In a vertical semiconductor device such as a trench gate type semiconductor device, there is generally a trade-off relationship between high breakdown voltage and low on-resistance.

  As a vertical insulated gate semiconductor device for solving this problem, there is one in which impurity regions are formed in a sandwich shape in the width direction in the order of pnpn. Such a structure is called a super junction structure, and the drift region can be completely depleted when the gate voltage is switched off, so that a higher breakdown voltage can be achieved compared to the conventional structure. It is also known that the impurity concentration can be made higher than that of the conventional structure, and the on-resistance can be reduced.

Further, Patent Document 1 discloses a semiconductor device in which a low on-resistance can be achieved while maintaining a breakdown voltage by adjusting the concentration of a region constituting a super junction.
JP 2002-289868 A

  However, the semiconductor device with the super junction structure has the following problems. That is, in a MOSFET having a super junction structure, DC characteristics such as switching characteristics, AC characteristics indicating recoverability during reverse recovery, and on-resistance are important factors. In particular, a reverse recovery characteristic (recovery characteristic) of a MOSFET having a super junction structure that shifts from an on state to an off state is an important characteristic because it affects the generation of a surge.

  That is, the PN junction area is large and the amount of reverse polarity carriers generated in the drift region is large. Therefore, the current waveform at the time of reverse recovery of the MOSFET becomes a hard recovery waveform as compared with a normal MOSFET.

  That is, a MOSFET having a super junction structure has poor recovery characteristics and generates a large surge. Therefore, it causes noise. In addition, the device may be destroyed due to the surge. Therefore, a breakdown voltage corresponding to this surge is required in the end, and it is difficult to reduce the on-resistance.

  The present invention has been made to solve the problems of the conventional insulated gate semiconductor device described above. That is, an object of the present invention is to provide an insulated gate semiconductor device in which a high breakdown voltage and a low on-resistance are simultaneously achieved by a super junction structure, and a deterioration in recoverability is suppressed.

In order to solve this problem, a semiconductor device includes an insulating gate having a source region which is a first conductivity type semiconductor located on the main surface side and a drain region which is located on the back side and which is a first conductivity type semiconductor. A first column group comprising a plurality of column regions being a first conductivity type semiconductor, a second column group comprising a plurality of column regions being a second conductivity type semiconductor, and a second conductivity type semiconductor in it and a relay column region joining each column region of the second column group, column region of the first column group and a column region of the second column regions are alternately arranged in the width direction, on the drain region A first semiconductor layer positioned; a drift region which is a first conductivity type semiconductor; a floating region which is surrounded by the drift region and which is a second conductivity type semiconductor; A semiconductor region, a second semiconductor layer located on the first semiconductor layer, a gate electrode layer facing the insulating film, and a body region that is a second conductivity type semiconductor, the source region being And a third semiconductor layer located on the second semiconductor layer, the upper surface of the relay semiconductor region of the second semiconductor layer is connected to the body region of the third semiconductor layer, and the lower surface is the first semiconductor layer. It is characterized in that it is connected to at least one of the column region or the relay column region of the second column group of one semiconductor layer.

  That is, the semiconductor device of the present invention includes a vertical semiconductor element and has a multilayer structure of a first semiconductor layer, a second semiconductor layer, and a third semiconductor layer. Specifically, the third semiconductor layer includes a source region and a body region facing the gate electrode layer, and a channel region is formed in the body region by turning on and off the control voltage to the gate electrode layer. That is, the region having the switching function of the element together with the gate electrode layer. Further, the second semiconductor layer includes a floating region that is electrically floating in the drift region. The first semiconductor layer has a so-called super junction structure in which column regions of different conductivity types are alternately arranged in the width direction. A current flows in the column region of the first column group having the same conductivity type as the drift region. In addition, each column region of the second column group is connected by a relay column region and is integrated.

  A relay region that penetrates the drift region is provided in the second semiconductor layer. The relay region is connected to the body region of the first semiconductor layer, and is also connected to at least one of the column region and the relay column region of the second column group of the first semiconductor layer. Therefore, these areas are united. That is, the body region of the third semiconductor layer and the column region of the second column group of the first semiconductor layer are regions having the same potential.

  The semiconductor device of the present invention has good recoverability by including the second semiconductor layer having the floating region above the first semiconductor layer having the super junction structure. In other words, in the semiconductor device of the present invention, many of the reverse polarity carriers flowing in the drift region during reverse recovery pass through the floating region having the same polarity as that carrier. As a result, a large amount of reverse polarity carriers are prevented from flowing at a time, and the current flow becomes gentle. Therefore, the recovery waveform at the time of reverse recovery becomes soft and the occurrence of surge is suppressed.

  In the semiconductor device of the present invention, an opening is provided in the main surface, and the bottom of the semiconductor device includes a trench portion that penetrates the first semiconductor layer and is located in the floating region of the second semiconductor layer. Good.

  In the semiconductor device of the present invention, the impurity can be implanted from the bottom of the trench by providing the trench that penetrates the first semiconductor layer. That is, the floating region can be formed after the epitaxial layer is formed. Therefore, it is not necessary to repeat the epitaxial growth process, and the manufacturing process is simple.

  Further, the trench portion of the semiconductor device penetrates the source region, in which a deposited insulating layer formed by depositing an insulator and a gate electrode layer located on the deposited insulating layer are disposed. It is better that the upper end of the deposited insulating layer is located below the lower end of the body region of the third semiconductor layer. In other words, the trench for forming the floating region and the trench for incorporating the gate electrode may be used together.

  According to the present invention, by providing the floating region above the super junction structure, the current flow can be moderated and the occurrence of surge can be suppressed. Therefore, an insulated gate semiconductor device in which high breakdown voltage and low on-resistance are both achieved by the super junction structure and deterioration in recoverability is suppressed is realized.

  DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments embodying the present invention will be described below in detail with reference to the accompanying drawings. In the present embodiment, the present invention is applied to a power MOS that controls conduction between a drain and a source (hereinafter referred to as “between DS”) by applying a voltage to an insulated gate.

The semiconductor device 100 according to this embodiment has a structure shown in the cross-sectional view of FIG. The semiconductor device 100 is located on an N + substrate 11 (drain region), a super junction layer 1 constituting a super junction structure, and a floating layer located on the super junction layer 1 and incorporating a P-type floating region. 2 and an element layer 3 which is located on the floating layer 2 and in which a channel region is formed. That is, the element layer 3, the floating layer 2, and the super junction layer 1 are stacked on the N + substrate region 11 in order from the upper surface side in FIG.

Further, the element layer 3 in the semiconductor device 100, P - body region 41, P - High body region 41 - and N + source region 31 formed within the body region 41, P to reduce contact resistance And a contact P + region 32 formed at a concentration. In the element layer 3, a trench 21 penetrating the N + source region 31 and the P body region 41 is formed by digging a part on the upper surface side. A deposited insulating layer 23 is formed at the bottom of the trench 21 by depositing an insulator. Specifically, the deposited insulating layer 23 is formed by depositing silicon oxide. Further, a gate electrode 22 made of polysilicon doped with phosphorus is formed on the deposited insulating layer 23. The lower end of gate electrode 22 is located below the lower surface of P body region 41. The gate electrode 22 faces the N + source region 31 and the P body region 41 via the gate insulating film 24 formed on the wall surface of the trench. That is, the gate electrode 22 is insulated from the N + source region 31 and the P body region 41 by the gate insulating film 24.

In the semiconductor device 100, a channel effect is generated in the P body region 41 by applying a voltage to the gate electrode 22, thereby controlling conduction between the N + source region 31 and the N + substrate region (drain region) 11. Yes.

The floating layer 2 in the semiconductor device 100 includes an N drift region 12, a P floating region 51 surrounded by the N drift region 12 and surrounding the bottom of the trench 21, and an element penetrating the N drift region 12. A P + relay region 13 that connects the P body region 41 of the layer 3 and the P-type region 61 of the super junction layer 1 is formed.

  The cross section of the P floating region 51 has a substantially circular shape as shown in the cross sectional view of FIG. In addition, there is sufficient space between adjacent P floating regions. Therefore, in the on state, the presence of the P floating region 51 does not hinder the drain current. Further, the radius of the P floating region 51 is equal to or less than the thickness of the deposited insulating layer 23. Therefore, the upper end of the deposited insulating layer 23 is located above the upper end of the P floating region 51. Therefore, the gate electrode 22 deposited on the deposited insulating layer 23 and the P floating region 51 do not face each other.

  Since the deposited insulating layer 23 is provided at the bottom of the trench 21, the gate insulating film 24 and the gate electrode 22 are not affected by damage in trench etching. Therefore, deterioration of element characteristics and deterioration of reliability are suppressed. Further, the facing of the gate electrode 22 and the P floating region 51 is suppressed, and an increase in on-resistance can be avoided. Further, since the oxide film 23 at the bottom of the trench 21 is thicker than when the deposited insulating layer 23 is not provided, the gate-drain capacitance Cgd is small and the switching speed is fast.

In the super junction layer 1 in the semiconductor device 100, P-type column regions 61 and N-type column regions 62 are alternately formed in the width direction. As shown in the cross-sectional view of FIG. 2, each P-type column region 61 is an integrated region by a P-type relay region 63 that connects adjacent P-type column regions 61. Further, the P-type column region 61 is connected to the P relay region 13 of the floating layer 2 and is also an integral region with the P body region 41. That is, the P-type column region 61 and the P body region 41 are regions having the same potential.

The semiconductor device 100 of this embodiment has the following structure, unlike a semiconductor device having a normal super junction structure. That is, the floating layer 2 is provided between the element layer 3 and the super junction layer 1. Due to the presence of the P floating region 51 of the floating layer 2, most of the holes present in a large amount in the N drift region 12 during reverse recovery are attracted to the low potential P floating region 51. Therefore, many holes go to the P body region 41 via the P floating region 51. That is, the P floating region acts as a hole current resistance. For this reason, it is avoided that a large number of holes flow at one time, and the flow of holes becomes gentle. Therefore, the recoverability can be improved.

  Next, simulation and experimental results regarding the recoverability of the semiconductor device 100 will be described. Specifically, in this simulation, a semiconductor device A (FIG. 3) which is a normal trench gate type power MOS and a semiconductor device B (FIG. 4) which is a trench gate type power MOS having a floating region in the drift region are prepared. Then, simulations and experiments were performed on each semiconductor device, and the recovery waveform was obtained.

  FIG. 5 shows a simulation result of the semiconductor device A. FIG. 6 shows a simulation result of the semiconductor device B. In order to suppress noise, it is necessary to reduce the amount of change in current (di / dt) during reverse recovery. In this simulation, the current change amount (di / dt) of the semiconductor device A was 160 A / μs, whereas the current change amount (di / dt) of the semiconductor device B was 70 A / μs. That is, the semiconductor device B having the floating region has a smaller current change amount (di / dt) during reverse recovery and a softer recovery waveform. Therefore, it can be seen that providing the floating structure improves the recovery characteristics compared to the conventional structure.

  Next, FIG. 7 shows an experimental result of the semiconductor device A. FIG. 8 shows the experimental results of the semiconductor device B. In this experiment, the current change amount (di / dt) of the semiconductor device A was 380 A / μs, whereas the current change amount (di / dt) of the semiconductor device B was 175 A / μs. Also through this experiment, it can be seen that the semiconductor device B has a softer recovery waveform and improved recovery characteristics than the semiconductor device A.

  FIG. 9 shows the movement of holes in the semiconductor device B during the simulation. The arrows in FIG. 9 indicate the direction of hole flow during reverse recovery. As shown in FIG. 9, the holes in the drift region flow toward the floating region. That is, since the majority of holes flow through the floating region, the amount of holes flowing per unit time is reduced. That is, the current change amount (di / dt) is reduced. As a result, the flow of Hall current becomes gentle.

Next, a manufacturing process of the semiconductor device 100 of this embodiment will be described. First, the super junction layer 1 in which the P-type column regions 61 and the N-type column regions 62 are alternately arranged is formed on the N + substrate region 11. For example, the following two methods are conceivable as a method of forming the super junction layer 1.

  The first method (first method) is a method of repeating ion implantation and formation of an epitaxial layer. That is, as shown in FIG. 10, after the pattern layer is formed, ion implantation is performed (a). Then, after performing diffusion treatment, an epitaxial layer is formed (b). Then, after forming the pattern layer again, ion implantation is performed (c). Then, after performing diffusion treatment again, an epitaxial layer is formed (d). The super junction layer 1 is formed by repeating the formation of the diffusion layer and the epitaxial layer to a desired thickness.

The second method (second method) is a method of filling a trench by epitaxial growth after the trench is formed. That is, as shown in FIG. 11, an N type epitaxial layer is formed on the N + substrate region 11 (a). Thereafter, the portion that becomes the P-type column region 61 is removed by dry etching to form a trench (b). Thereafter, a P-type epitaxial layer is formed to serve as both the formation of the body region and the filling in the trench (c). Thereafter, the super junction layer 1 is formed by etching and removing the P type epitaxial layer located on the N type epitaxial layer.

Next, the floating layer 2 and the element layer 3 are formed on the super junction layer 1. First, as shown in FIG. 12, an N -type epitaxial layer is formed on the super junction layer 1. This epitaxial layer is a portion that becomes the floating layer 2. Next, a P-type column region to be the P relay region 13 is formed (a). This column region is created by a method similar to the second method (see FIG. 11) for forming the super junction layer. Therefore, the P body region 41 is formed together with the P relay region 13. Then, an N + source region 31 is formed by subsequent ion implantation or the like (b).

Next, a trench 21 is formed which penetrates the P body region 41 and whose bottom reaches the N drift region 12 (c). Next, ion implantation is performed from the bottom surface of the trench 21 (d). Next, as shown in FIG. 13, an insulator (silicon oxide or the like) 23 is deposited in the trench 21 by CVD (e). Thereafter, a thermal diffusion process is performed for both the baking of the insulator and the formation of the P floating region 51. Thereby, the P floating region 51 is formed (f). Next, a part of the insulator is removed by etching the semiconductor substrate on which the insulator is deposited (g). Thereby, a space for forming the gate electrode 22 is secured.

  Next, an oxide film is formed on the upper surface of the semiconductor substrate and the wall surface of the trench 21 by thermal oxidation. This becomes the gate oxide film 24. Then, a gate electrode 22 is formed by depositing a conductor (such as polysilicon doped with phosphorus) in the space secured in the previous step (h). Finally, the semiconductor device 100 is manufactured by forming the source electrode and the drain electrode.

  When forming the P-type column region to be the P relay region 13, it may be formed by the same method as the first method (see FIG. 10) for forming the super junction layer. In that case, the P floating region can be formed in the process of stacking the epitaxial layers. Therefore, the P floating region can be formed without forming a trench penetrating the body region.

As described above in detail, the semiconductor device 100 of this embodiment is a vertical MOSFET having the N + source region 31 on the main surface side and the N + drain region 11 on the back surface side, and has a super junction structure. It is said. In the semiconductor device 100, the floating layer 2 is provided between the element layer 3 and the super junction layer 1. Due to the P floating region 51 in the floating layer 2, many holes flowing in the N drift region 12 pass through the P floating region 51. Therefore, a large number of holes can be prevented from flowing at a time, and the hole current flow becomes gentle. Therefore, a soft recovery waveform is obtained, and the occurrence of surge is suppressed. Therefore, an insulated gate semiconductor device in which high breakdown voltage and low on-resistance are both achieved by the super junction structure and deterioration in recoverability is suppressed is realized.

In the semiconductor device 100 of this embodiment, a trench 21 penetrating the element layer 3 is provided, and ion implantation is performed from the bottom of the trench 21 to form a P floating region surrounded by the N drift region 12. Yes. That is, after the N drift region 12 is formed by an epitaxial growth process, the P floating region 51 is formed by one ion implantation. Therefore, the repetition of the epitaxial growth process and the ion implantation / thermal diffusion process can be avoided, and the manufacturing process is simple.

  Note that this embodiment is merely an example, and does not limit the present invention. Therefore, the present invention can naturally be improved and modified in various ways without departing from the gist thereof. For example, the gate insulating film 24 is not limited to an oxide film, and may be another type of insulating film such as a nitride film or a composite film. Also, the semiconductor is not limited to silicon, but may be other types of semiconductors (SiC, GaN, GaAs, etc.).

  In the semiconductor device of the embodiment, the trench for forming the floating region and the trench for incorporating the gate electrode are combined, but the present invention is not limited to this. That is, each may be provided exclusively.

  The semiconductor device of the embodiment is an n-channel transistor, but may be a p-channel transistor. That is, for each semiconductor region, the P type and the N type may be interchanged.

It is sectional drawing which shows the structure of the semiconductor device which concerns on embodiment. It is a figure which shows the AA cross section of the semiconductor device shown in FIG. It is sectional drawing which shows the structure of the semiconductor device A which concerns on simulation. It is sectional drawing which shows the structure of the semiconductor device B which concerns on simulation. 10 is a graph of a recovery waveform showing a simulation result of the semiconductor device A. 10 is a graph of a recovery waveform showing a simulation result of the semiconductor device B. 10 is a graph of a recovery waveform showing an experimental result of the semiconductor device A. 10 is a graph of a recovery waveform showing an experimental result of the semiconductor device B. It is a figure which shows the motion of the hole of the semiconductor device B which concerns on simulation. It is a figure (1st method) which shows the manufacturing process of a super junction layer. It is a figure (2nd method) which shows the manufacturing process of a super junction layer. It is a figure (ad) which shows the manufacturing process of a floating layer and an element layer. It is a figure (eh) showing a manufacturing process of a floating layer and an element layer.

Explanation of symbols

1 Super junction layer (first semiconductor layer)
2 Floating layer (second semiconductor layer)
3 Element layer (third semiconductor layer)
11 N + drain region (drain region)
12 N - drift region (drift region)
13P relay area (relay semiconductor area)
21 trench (trench part)
22 Gate electrode (gate electrode layer)
23 Deposition insulation layer (Deposition insulation layer)
31 N + source region (source region)
41 P - body region (body region)
51 P floating area (floating area)
61 P-type column region (column region of the second column group)
62 N-type column region (column region of the first column group)
63 P-type relay area (relay column area)
100 Semiconductor device (insulated gate type semiconductor device)

Claims (3)

  1. In an insulated gate semiconductor device including a source region that is a first conductivity type semiconductor located on a main surface side and a drain region that is a first conductivity type semiconductor located on a back surface side,
    A first column group composed of a plurality of column regions which are first conductive type semiconductors; a second column group composed of a plurality of column regions which are second conductive type semiconductors; and a second column group which is a second conductive type semiconductors. and a relay column region joining each column regions of the first column group of the column region and the column region of the second column regions are alternately arranged in the width direction, the position on the drain region One semiconductor layer;
    A drift region which is a first conductivity type semiconductor; a floating region which is surrounded by the drift region and which is a second conductivity type semiconductor; and a relay semiconductor region which is a second conductivity type semiconductor and penetrates the drift region; A second semiconductor layer located on the first semiconductor layer;
    A third semiconductor layer facing the gate electrode layer with an insulating film in between, having a body region that is a second conductivity type semiconductor, the source region being disposed in the body region, and located on the second semiconductor layer And
    The relay semiconductor region of the second semiconductor layer has an upper surface connected to the body region of the third semiconductor layer, and a lower surface connected to at least one of the column region or the relay column region of the second column group of the first semiconductor layer. An insulated gate semiconductor device characterized by comprising:
  2. The insulated gate semiconductor device according to claim 1,
    An insulated gate semiconductor device comprising: an opening provided on a main surface; and a trench part penetrating the first semiconductor layer and having a bottom part located in a floating region of the second semiconductor layer.
  3. In the insulated gate semiconductor device according to claim 2,
    The trench portion penetrates the source region,
    In the trench part,
    A deposited insulating layer formed by depositing an insulator;
    A gate electrode layer located on the deposited insulating layer is disposed;
    An insulated gate semiconductor device, wherein an upper end of the deposited insulating layer is located below a lower end of a body region of the third semiconductor layer.
JP2005174026A 2005-06-14 2005-06-14 Insulated gate semiconductor device Expired - Fee Related JP4735067B2 (en)

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Publication number Priority date Publication date Assignee Title
JP5423882B2 (en) 2009-07-15 2014-02-19 富士電機株式会社 Super junction semiconductor device
JP5812029B2 (en) 2012-06-13 2015-11-11 株式会社デンソー Silicon carbide semiconductor device and manufacturing method thereof
WO2014207793A1 (en) * 2013-06-24 2014-12-31 株式会社日立製作所 Semiconductor device, and method for manufacturing same
CN108074963B (en) * 2016-11-16 2020-04-24 深圳尚阳通科技有限公司 Super junction device and manufacturing method thereof

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004200441A (en) * 2002-12-19 2004-07-15 Toyota Central Res & Dev Lab Inc Semiconductor device and its manufacturing method
JP2004311716A (en) * 2003-04-07 2004-11-04 Toshiba Corp Insulated gate type semiconductor device
JP2005101560A (en) * 2003-08-20 2005-04-14 Denso Corp Vertical semiconductor device

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004200441A (en) * 2002-12-19 2004-07-15 Toyota Central Res & Dev Lab Inc Semiconductor device and its manufacturing method
JP2004311716A (en) * 2003-04-07 2004-11-04 Toshiba Corp Insulated gate type semiconductor device
JP2005101560A (en) * 2003-08-20 2005-04-14 Denso Corp Vertical semiconductor device

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