JP4738562B2 - Manufacturing method of semiconductor device - Google Patents

Manufacturing method of semiconductor device Download PDF

Info

Publication number
JP4738562B2
JP4738562B2 JP2000072298A JP2000072298A JP4738562B2 JP 4738562 B2 JP4738562 B2 JP 4738562B2 JP 2000072298 A JP2000072298 A JP 2000072298A JP 2000072298 A JP2000072298 A JP 2000072298A JP 4738562 B2 JP4738562 B2 JP 4738562B2
Authority
JP
Japan
Prior art keywords
type
region
forming
layer
electric field
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP2000072298A
Other languages
Japanese (ja)
Other versions
JP2001267570A (en
Inventor
博司 杉本
昌之 今泉
陽一郎 樽井
健一 大塚
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP2000072298A priority Critical patent/JP4738562B2/en
Publication of JP2001267570A publication Critical patent/JP2001267570A/en
Application granted granted Critical
Publication of JP4738562B2 publication Critical patent/JP4738562B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
    • H01L29/0623—Buried supplementary region, e.g. buried guard ring
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices
    • H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • H01L29/0852—Source or drain regions of field-effect devices of field-effect transistors with insulated gate of DMOS transistors
    • H01L29/0873—Drain regions
    • H01L29/0878—Impurity concentration or distribution
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1095—Body region, i.e. base region, of DMOS transistors or IGBTs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66053—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide
    • H01L29/66068—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
    • H01L29/1608—Silicon carbide

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Manufacturing & Machinery (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Description

【０００１】
【発明の属する技術分野】
本発明は半導体装置の製造方法に関し、特に、トレンチゲート型のＳｉＣ（炭化珪素）半導体を用いたＭＯＳ電界効果パワートランジスタとして用いる半導体装置の製造方法に関するものである。
【０００２】
【従来の技術】
トレンチゲート型のＳｉＣ半導体を用いた従来のＭＯＳ電界効果パワートランジスタは、例えば、電子情報通信学会論文誌Ｃ−ＩＩ Vol．Ｊ８１−Ｃ−ＩＩ、Ｎｏ．１の１３５ページの図２に示されるような構造であり、トレンチ側壁に設けたＭＯＳ構造のゲート部分で電流を制御し、高電圧のスイッチングを行う。
【０００３】
図６は、従来のこのようなトレンチゲート型のＳｉＣ半導体を用いたＭＯＳ電界効果パワートランジスタ半導体装置の概念図である。図において、１０１はｎ型のＳｉＣ基板、１０２はエピ成長で形成した低不純物のｎ型の導電性を持つＳｉＣのドリフト領域、１０３はエピ成長もしくはイオン注入により形成したｐ型導電性ベース領域、１０４はエピ成長もしくはイオン注入により形成したｎ型導電性のｎコンタクト領域、１０５はエピ成長もしくはイオン注入により形成したｐ型導電性のｐコンタクト領域、１０６はエッチングにより形成したトレンチ部、１０７はゲート酸化膜、１０８はゲート酸化膜１０７上に形成されたゲート電極、１０９はゲート電極１０８に印加した電圧で形成されるチャネル部、１１０はソース電極、１１１はドレイン電極を示している。
【０００４】
動作について説明する。ソース電極１１０とドレイン電極１１１間に高電圧を印加した状態で、ゲート電極１０８に電圧を印加することにより、ｐ型導電性ベース領域１０３のチャネル部１０９にｎ型反転層が形成され、ｎ型導電性コンタクト領域１０４とドリフト領域１０２間に電流が導通し、ドリフト領域１０２を経てドレイン電極１１１に電流が流れる。ゲート電極１０８に電圧が印加されないオフ状態では、チャネル部１０９にｎ型反転層が形成されないので、この時、ソース電極１１０とドレイン電極１１１間に印加された高電圧は、ドリフト領域１０２並びにｐベース領域１０３に延びた空乏層で遮断される。
【０００５】
次に、製造方法について説明する。従来のトレンチゲート型のＳｉＣ半導体ＭＯＳ電界効果パワートランジスタは、次のようにして作製する。ＳｉＣ基板１０１上に、エピ成長により、ドリフト領域１０２のための低不純物ｎ型層を成長させ、次に、ｐ型導電性のベース領域１０３のためのｐ型層を成長させ、次に、ｎコンタクト領域１０４のため高不純物のｎ型層を順次成長させる。次に例えばマスキングを行ってエッチングを行い、トレンチ部６を形成する。次に、別のマスキングを行い、ｐコンタクト領域１０５部に、選択的に、表面にｐコンタクト用にイオン注入を行って、その後、注入された不純物を電気的に活性化し、アクセプタとして活性化させるため、例えば、Ａｒ雰囲気中で、１５００°Ｃで１時間程度のアニールを行って、ｐコンタクト領域１０５を形成する。次に、水蒸気分圧を含んだ、酸素雰囲気でＳｉＣ表面の熱酸化を行い、ゲート酸化膜７を形成した後、ゲート電極８、ソース電極１０、ドレイン電極１１を形成する。
【０００６】
なお、ここでは、ｐコンタクト領域１０５をイオン注入により形成する例について説明したが、その場合に限らず、逆に例えば、ｐコンタクト領域１０５に相当する層をエピ成長で形成し、領域１０５以外の領域に窒素のイオン注入を行い、その後に、注入された不純物を電気的に活性化し、ドナーとして活性化させるため、例えば、Ａｒ雰囲気中で、１５００°Ｃで１時間程度のアニールを行って、ｎコンタクト領域１０４を形成するようにしてもよい。
【０００７】
図７は、例えば、電子情報通信学会論文誌Ｃ-ＩＩ，Vol.J81-Ｃ-ＩＩ，No.1の１３５ページに示されるような構造であり、従来型のウエハー表面にＭＯＳチャネルを持つ構造のＳｉＣ半導体を用いたＭＯＳ電界効果パワートランジスタ半導体装置の概念図である。２０１はｎ型のＳｉＣ基板、２０２はエピ成長で形成した低不純物のｎ型の導電性を持つＳｉＣのドリフト領域、２０３はイオン注入により形成したｐ型導電性ベース領域、２０４はイオン注入により形成したｎ型導電性のｎコンタクト領域、２０７はゲート酸化膜、２０８はゲート電極、２０９はゲート電極に印加した電圧で形成されるチャネル部、２１０はソース電極、２１１はドレイン電極を示している。図６と同様にゲート電極２０８に電圧を印加することにより、ｐ型導電性ベース領域２０３の表面のチャネル部２０９にｎ型反転層が形成され、ｎ型導電性コンタクト領域２０４とドリフト領域２０２間に電流が導通し、ドリフト領域２０２を経てドレイン電極２１１に電流が流れる。
【０００８】
【発明が解決しようとする課題】
ＳｉＣはＳｉに比較し絶縁破壊電界強度が１０倍大きい。この特長を利用して、素子特性の向上を図る様に素子の構造を最適化すると、ＳｉＣ中にはＳｉの絶縁破壊電界強度の十倍に近い電界が存在する。このため、上述したような図６の従来のトレンチゲート型のＳｉＣ半導体を用いたＭＯＳ電界効果パワートランジスタでは、絶縁破壊電界強度に近い電界が発生するＳｉＣ部分に接したゲート酸化膜中においても、両者の誘電率比によって定まる電界が発生し、その強度は酸化膜の絶縁破壊電界強度を越えることから、酸化膜中で絶縁破壊が生じる。またトレンチゲート構造では、特にトレンチ下部の角部分で電界集中が起こり、酸化膜中の電界強度が大きくなり、上記理由と相まって、ゲート酸化膜に絶縁破壊が生じ易い。このような結果、従来のトレンチゲート型のＳｉＣ半導体を用いたＭＯＳ電界効果パワートランジスタでは、ＳｉＣの材料特性から期待される素子耐圧が得られないという問題点があった。
【０００９】
一方、図７に示した、従来の基板表面にＭＯＳチャネルを持つ構造のＭＯＳパワートランジスタでは、不純物を注入後、不純物を電気的に活性化させる工程で、例えば、Ａｒ雰囲気中で、１５００°Ｃで１時間のアニールを行う必要がある。この時、表面のＳｉが選択的に離脱したり、表面で部分的に不均一に成長やエッチングが生じることにより、ＳｉＣの表面に荒れが生じたり、階段状のステップ構造が形成される問題があった。基板表面にＭＯＳチャネルを持つ構造のＭＯＳパワートランジスタでは、この荒れもしくはステップの生じた面が、ＭＯＳチャネルの界面となる構造のため、ＭＯＳ界面の劣化により、十分なチャネル特性が得られない問題があった。
【００１０】
また、基板表面にＭＯＳチャネルを持つ構造では、チャネル移動度が大きい１１２バー０面を、ＭＯＳチャネルの界面として用いるためには、入手が困難な１１２バー０面ウエハーを作製し、さらにそれに伴い従来基板面のプロセスとは異なった、エピ成長、注入、電極等の作製条件が必要であるという問題点があった。
【００１１】
本発明は、かかる問題点を解決するために成されたもので、ＳｉＣ中の電界分布の強い箇所がゲート酸化膜から離れた所になるような構造を備え、ゲート酸化膜が破壊されない特長をもち、ＳｉＣの材料特性に対応した素子耐圧を持つ半導体装置の製造方法を提供することを目的とする。
【００１２】
【課題を解決するための手段】
この発明は、炭化珪素半導体からなる基板上に、低不純物のｎ型の導電性を有する炭化珪素半導体からなるｎ型層を形成する工程と、上記ｎ型層上に、ｐ型の導電性を有する炭化珪素半導体からなるｐ型ベース層を形成する工程と、上記ｐ型ベース層上に、高不純物のｎ型の導電性を有する炭化珪素半導体からなるｎ型コンタクト層を形成する工程と、上記ｐ型ベース層上の上記ｎ型コンタクト層が設けられていない領域に炭化珪素半導体からなるｐ型コンタクト領域を形成する工程と、マスクを用いイオン注入を行うことにより、上記ｎ型層内に、高電圧遮断時の上記ｎ型層からのゲート酸化膜への電界の侵入をシールドさせるための溝下部電界シールド手段をｐ型領域によって形成する工程と、上記溝下部電界シールド手段を形成した後に活性化アニールを行なう活性化アニール工程と、上記活性化アニール工程後に、上記マスクを用いエッチングを行うことにより、上記ｎ型コンタクト層及び上記ｐ型ベース層を貫通して上記ｎ型層内の上記溝下部電界シールド手段に達する深さを有する溝を形成する工程と、上記溝の底面及び側壁上にゲート酸化膜を形成する工程と、上記ゲート酸化膜を介在させて上記溝の側壁上にゲート電極を形成する工程と、上記ｎ型コンタクト層及び上記ｐ型コンタクト領域に接触させてソース電極を形成する工程と、上記基板の下面にドレイン電極を形成する工程とを備えた半導体装置の製造方法である。
【００２６】
【発明の実施の形態】
実施の形態１．
図１は本発明の一実施の形態を示すもので、トレンチゲート型のＳｉＣ半導体ＭＯＳ電界効果パワートランジスタ半導体装置の断面図である。１はｎ型のＳｉＣ基板、２は低不純物のｎ型の導電性を有するドリフト領域、３はドレイン電流制御用のＭＯＳチャネルを形成するためのｐ型導電性のベース領域、４はｎ型導電性のｎコンタクト領域、５はｐ型導電性のｐコンタクト領域、６はエッチングにより形成したトレンチ部、７はトレンチ部６の底面および側壁に設けられたゲート酸化膜、８はゲート電極、９はゲート電極に印加した電圧で形成されるチャネル部、１０はソース電極、１１はドレイン電極、１２はゲート酸化膜７部の電界強度を緩和するために、トレンチ部６の下部にエピ成長もしくはイオン注入により形成した、ｐ型導電性のトレンチ下部電界シールド領域、１３はｐ型のベース領域３下部にエピ成長もしくはイオン注入により形成した、ｐ型導電性のベース領域下部電界シールド領域である。
【００２７】
動作について説明する。ゲート電極８に電圧を印加することにより、チャネル部９にｎ型反転層が形成され、ｎ型導電性のｎコンタクト領域４とドリフト領域２間に電流が導通し、ドリフト領域２を経てドレイン電極１１に電流が流れる。ゲート電極８に電圧が印加されないオフ状態では、チャネル部９にｎ型反転層が形成されない。この時ソース電極１０とドレイン電極１１間に印加された高電圧は、ドリフト領域２、トレンチ下部電界シールド領域１２、ベース領域下部電界シールド領域１３に延びた空乏層で遮断される。ここで、本実施の形態においては、トレンチ部６の下部にトレンチ下部電界シールド１２を備えているので、それによって電界侵入が阻まれ、ゲート酸化膜７部分、特に、電界集中が起こるトレンチ部６下部の角部分の電界強度が緩和され、ゲート酸化膜７の絶縁破壊が生じない。また、ｐベース領域３下にもベース領域下部電界シールド領域１３が備えられているため、ｐベース領域下からの電界の浸入がシールドされるため、ゲート酸化膜７の電界強度が緩和される。このような構造により、逆高電圧遮断時の電界強度の最強な箇所は、シールド領域１３の下端になり、電界強度の強い部分とゲート酸化膜７に接する部分が接触せずに分離されることにより、酸化膜の絶縁破壊が生じない。
【００２８】
次に、製造方法について説明する。本実施の形態に示したトレンチゲート型のＳｉＣ半導体ＭＯＳ電界効果パワートランジスタは例えば、次のように作製できる。ＳｉＣ基板１上に、ＣＶＤエピ成長により、ドリフト領域２のための低不純物ｎ型層を成長させ、次に、ｐ型導電性のベース領域３のためのｐ型層を成長させ、次に、ｎコンタクト領域４のため高不純物のｎ型層を順次成長させる。次に、マスキングを行い、ｐコンタクト領域５部に、選択的に、表面にｐコンタクト用に高濃度のＡｌのイオン注入を行って、ｐコンタクト領域５を形成し、次に、例えば、同じマスクを用い、トレンチ部６の下部（底面）の深さより深い領域まで垂直方向に（すなわち、深さ方向に）Ａｌのイオン注入を行い、ベース領域下部電界シールド領域１３を形成する。また、次に例えば別のマスキングを行いトレンチ部６に選択的に、トレンチ部６下部（底面）の深さより深い領域にＡｌ（アクセプタ）のイオン注入を行い、トレンチ下部電界シールド領域１２を形成する。このとき、トレンチ下部電界シールド領域１２の厚さが、ドリフト領域２からの酸化ゲート膜７への電界の侵入を妨げるに十分な所定の厚さになるようにする。次に例えば同じマスクを用い、エッチングを行いトレンチ部６を形成する。次に例えば、水蒸気分圧を含んだ、酸素雰囲気でＳｉＣ表面の熱酸化を行い、ゲート酸化膜７を形成した後、ゲート電極８、ソース電極１０、ドレイン電極１１を形成する。
【００２９】
この例では、ｎコンタクト領域４のための高不純物のエピ成長したｎ型層にイオン注入により、ｐコンタクト領域５を形成する例を示したが、逆に、ｐコンタクト領域５のためのｐ層を成長により形成し、そこに窒素のイオン注入により、ｎコンタクト領域４を形成しても作製可能である。また、ここでは、ｐベース領域３のためのｐ型層を、エピ成長で形成する例を示したが、イオン注入によっても可能である。
【００３０】
以上のように、本実施の形態が示す半導体装置では、トレンチ部６の下部にトレンチ下部電界シールド領域１２があるため、ゲート酸化膜７の電界強度が緩和される。また、ｐベース領域３下にもベース領域下部電界シールド領域１３が備えられているため、ｐベース領域下からの電界の浸入がシールドされるため、ゲート酸化膜７の電界強度が緩和される。このような構造により、逆高電圧遮断時の電界強度の最強な箇所は、ｐシールド領域の下端になり、電界強度の強い部分と、ゲート酸化膜７に接する部分が接触せずに分離されることにより、酸化膜の絶縁破壊が生じない。この結果、高電圧遮断時の、ゲート酸化膜７の電界強度を低減し、ゲート酸化膜７の絶縁破壊が防がれ、ＳｉＣ材料の絶縁特性に対応した、素子耐圧を得ることができる。
【００３１】
また、本実施の形態が示す製造方法に於いては、トレンチ部６を形成する前の工程で、イオン注入と活性化アニールを行い、その後に、トレンチ部６を形成し、その側壁をチャネルとして用いるので、チャネルが形成されるトレンチ部６の側壁に生じる注入の損傷、及び、アニールによる表面の荒れを低減することができ、高移動度で信頼性の高いチャネルを形成することができる効果があり、素子特性を向上できる。
【００３２】
実施の形態２．
図２は本発明の別の一実施の形態を示すもので、トレンチゲート型のＳｉＣ半導体ＭＯＳ電界効果パワートランジスタ半導体装置の断面図である。１はｎ型のＳｉＣ基板、２はドリフト領域、３はベース領域、４はｎコンタクト領域、５はｐコンタクト領域、６はトレンチ部、７はゲート酸化膜、８はゲート電極、９はチャネル部、１０はソース電極、１１はドレイン電極、１２はトレンチ下部電界シールド領域、１３はｐ型導電性のベース領域下部電界シールド領域、１４はトレンチ下部電界シールド領域１２とベース領域下部電界シールド領域１３を電気的に結合する、電界シールド結合領域をしめしている。ゲート電極８への電圧の印加による、高電圧の遮断、導通の切り替えの原理及び電界シールド領域による、酸化膜における電界緩和の原理は実施の形態１と同様である。
【００３３】
次に製造方法について説明する。本実施の形態に示したトレンチゲート型のＳｉＣ半導体ＭＯＳ電界効果パワートランジスタは、例えば、次のように作製できる。ＳｉＣ基板１上に、ドリフト領域２のための低不純物ｎ型層を、ｐベース領域３のためのｐ型層を、ｎコンタクト領域４のため高不純物のｎ型層を順次成長する。次にマスキングを行いｐコンタクト領域５部に選択的に、表面にコンタクト用に高濃度のＡｌのイオン注入を行い、次に例えば同じマスクを用い、トレンチ下部の深さより深い領域までＡｌのイオン注入を行い、ベース領域下部電界シールド領域１３を形成する。また次に例えば別のマスキングを行いトレンチ部６と電界シールド結合領域１４に選択的に、トレンチ下部の深さより深い領域にＡｌのイオン注入を行い、トレンチ下部電界シールド領域１２と電界シールド結合領域１４を形成する。次に例えば別のマスクを用い、エッチングを行いトレンチ部６を形成する。次ゲート酸化膜７を形成した後、ゲート電極８、ソース電極１０、ドレイン電極１１を形成する。
【００３４】
この例では、ドリフト領域にイオン注入により、トレンチ下部電界シールド領域１２、ベース領域下部電界シールド領域１３並びに電界シールド結合領域１４を形成する作製方法を示したが、逆に例えば上記３領域に相当する層をエピ成長で形成し、３領域以外の領域に窒素のイオン注入を行いｎ型導電領域を作製することも可能である。
【００３５】
以上のように、本実施の形態における半導体装置において、トレンチ下部電界シールド領域１２とベース領域下部電界シールド領域１３によりゲート酸化膜７部の電界強度が緩和され酸化膜の絶縁破壊が軽減される原理は実施の形態１と同様である。さらに本実施の形態では、ｐベース領域とｐシールド領域を電気的に結合する構造を備えているので、電位的に浮遊した領域が生じず、電荷の蓄積の片寄も生じないため、より安定なスイッチング動作と酸化膜の高い信頼性が得られる。
【００３６】
また、本実施の形態における製造方法においても、上述の実施の形態１と同様に、トレンチ部６を形成する前の工程で、イオン注入と、活性化アニールを行うことができるので、チャネルが形成されるトレンチ部６の側壁に生じる注入の損傷、アニールによる表面の荒れを低減することができ、高移動度で信頼性の高いチャネルを形成することができる効果があり、素子特性を向上できる。
【００３７】
実施の形態３．
図３は本発明の別の一実施の形態を示すもので、トレンチゲート型のＳｉＣ半導体ＭＯＳ電界効果パワートランジスタ半導体装置の断面図である。１はｎ型のＳｉＣ基板、２はドリフト領域、３はベース領域、４はｎコンタクト領域、５はｐコンタクト領域、６はトレンチ部、７はゲート酸化膜、８はゲート電極、９はチャネル部、１０はソース電極、１１はドレイン電極、１２はトレンチ下部電界シールド領域、１３はベース領域下部電界シールド領域、１４は電界シールド結合領域、１５は導通時の抵抗を低減するためにｐベース領域の下部に設けた、ドリフト領域２より導電性の高い（すなわち、キャリア濃度の高い）ｎ型の電流拡散層である。ゲート電極８への電圧を印加による、高電圧の遮断、導通の切り替え、及び電界シールド領域の効果による、酸化膜における電界緩和の原理は実施の形態１及び２と同様である。
【００３８】
次に製造方法について説明する。本実施の形態に示したトレンチゲート型のＳｉＣ半導体ＭＯＳ電界効果パワートランジスタは例えば、次のように作製できる。ＳｉＣ基板１上に、ドリフト領域２のための低不純物ｎ型層を、次に電流拡散層１５のための、ドリフト領域２より導電率の高いｎ型層を、次にｐベース領域３のためのｐ型層を、次にｎコンタクト領域４のための高不純物のｎ型層を順次成長する。実施の形態２と同様に選択的に、ｐコンタクト領域５、ベース領域下部電界シールド領域１３、トレンチ下部電界シールド領域１２並びに電界シールド結合領域１４をＡｌのイオン注入により形成する。また次に例えば別のマスキングによるドナーのイオン注入によりｎコンタクト領域４を形成する。次に例えば別のマスクを用い、エッチングを行いトレンチ部６を形成する。次にゲート酸化膜７を形成した後、ゲート電極８、ソース電極１０、ドレイン電極１１を形成する。この例では、エピ成長により電流拡散層を形成する作製例を示したが、ドナーのイオン注入により電流拡散層を形成する作製例も可能である。
【００３９】
以上のように、本実施の形態に示した半導体装置は、上述の実施の形態１及び２と同様の効果が得られるとともに、さらに、ｐベース領域３の下部に、ドリフト領域２より導電性の高いｎ型の電流拡散層１５そなえているので、導通時には、電流経路は、ゲート電圧印加により反転して形成されたチャネル９近傍からのみではなく、ｎ型の電流拡散層１５全体から、ｎ型ドリフト領域２を経て流れるので、その抵抗は、電流拡散層１５がないときに比べ低減される効果がある。
【００４０】
また、本実施の形態における製造方法においても、上述の実施の形態１と同様に、トレンチ部６を形成する前の工程で、イオン注入と、活性化アニールを行うことができるので、チャネルが形成されるトレンチ部６の側壁に生じる注入の損傷、アニールによる表面の荒れを低減することができ、高移動度で信頼性の高いチャネルを形成することができる効果があり、素子特性を向上できる。
【００４１】
実施の形態４．
図４は本発明の別の一実施の形態を示すもので、トレンチゲート型のＳｉＣ半導体ＭＯＳ電界効果パワートランジスタ半導体装置の断面図である。１はｎ型のＳｉＣ基板、２はドリフト領域、３はベース領域、４はｎコンタクト領域、５はｐコンタクト領域、６はトレンチ部、７はゲート酸化膜、８はゲート電極、９はチャネル部、１０はソース電極、１１はドレイン電極、１２Ａはトレンチ部６の幅より広い幅を持ち、トレンチ部６のない領域まで横に延びた構造を有したトレンチ下部電界シールド領域、１３はベース領域下部電界シールド領域、１５は電流拡散層である。ゲート電極８への電圧を印加による、高電圧の遮断と導通の切り替え、及び、電界シールド領域１２、１３の効果による、ゲート酸化膜７における電界緩和、電流拡散層１５による抵抗の低減の原理は実施の形態１から３と同様である。
【００４２】
次に製造方法について説明する。本実施の形態に示したトレンチゲート型のＳｉＣ半導体ＭＯＳ電界効果パワートランジスタは例えば、次のように作製できる。ＳｉＣ基板１上に、ドリフト領域２のための低不純物ｎ型層を、次に電流拡散層１５のためのｎ型層を、次にｐベース領域３のためのｐ型層を、次にｎコンタクト領域４のための高不純物のｎ型層を順次成長する。実施の形態３と同様に選択的に、ｐコンタクト領域５、ベース領域下部電界シールド領域１３、トレンチ下部電界シールド領域１２並びに電界シールド結合領域１４をＡｌのイオン注入により形成する。この時、トレンチ下部電界シールド領域１２注入のためのマスクパターンを、トレンチ部６の幅より広くすることにより上部にトレンチ部６のない横の領域まで延びた注入領域を形成できる。また次にドナーのイオン注入によりｎコンタクト領域４を形成する。次トレンチ部６を形成し、ゲート酸化膜７を形成した後、ゲート電極８、ソース電極１０、ドレイン電極１１を形成する。この例では、エピ成長により電流拡散層を形成する作製例を示したが、ドナーのイオン注入により電流拡散層を形成する作製例も可能である。
【００４３】
以上のように、本実施の形態に示した半導体装置は、上述の実施の形態１〜３と同様の効果が得られるとともに、さらに、トレンチ下部シールド領域１２の幅が、溝の幅より広く、上部のトレンチ部６のない領域まで延びた構造であり、特にトレンチ下部の角の部分と電界強度の大きい箇所とが、平面位置的にも分離されるので、特にトレンチ下部の角の酸化膜に印加される電界強度の緩和効果が大きく、酸化膜の絶縁破壊が生じない特長がある。
【００４４】
また、本実施の形態における製造方法においても、上述の実施の形態１と同様に、トレンチ部６を形成する前の工程で、イオン注入と、活性化アニールを行うことができるので、チャネルが形成されるトレンチ部６の側壁に生じる注入の損傷、アニールによる表面の荒れを低減することができ、高移動度で信頼性の高いチャネルを形成することができる効果があり、素子特性を向上できる。
【００４５】
なお、図５は同じく実施の形態４の他の構成を示すもので、トレンチ下部電界シールド領域１２の幅が広く、ベース領域下部電界シールド領域１３がない例をしめす。図４と同様に作製でき、また、同様な酸化膜の絶縁破壊を抑制する効果がある。
【００４６】
実施の形態５．
つぎに、本発明の別の一実施の形態を示す。本実施の形態に示す半導体装置は、素子構造、作製方法は、上記実施の形態１から４と同様であり、電界シールド効果により、ゲート酸化膜７の絶縁破壊を抑制する効果をもっている。本実施の形態では、チャネル９は、エッチングにより形成したＳｉＣ結晶の１、１、２バー、０面のトレンチ部６の側壁に形成されている。チャネル移動度の結晶方位依存性より、基板表面に形成されたチャネルより大きな移動度が得られ、チャネル抵抗を低減できる。また同時に、電界シールドのためのｐ領域を備えているので、酸化膜の絶縁破壊が起こりにくい。
【００４７】
【発明の効果】
この発明は、炭化珪素半導体からなる基板上に、低不純物のｎ型の導電性を有する炭化珪素半導体からなるｎ型層を形成する工程と、上記ｎ型層上に、ｐ型の導電性を有する炭化珪素半導体からなるｐ型ベース層を形成する工程と、上記ｐ型ベース層上に、高不純物のｎ型の導電性を有する炭化珪素半導体からなるｎ型コンタクト層を形成する工程と、上記ｐ型ベース層上の上記ｎ型コンタクト層が設けられていない領域に炭化珪素半導体からなるｐ型コンタクト領域を形成する工程と、マスクを用いイオン注入を行うことにより、上記ｎ型層内に、高電圧遮断時の上記ｎ型層からのゲート酸化膜への電界の侵入をシールドさせるための溝下部電界シールド手段をｐ型領域によって形成する工程と、上記溝下部電界シールド手段を形成した後に活性化アニールを行なう活性化アニール工程と、上記活性化アニール工程後に、上記マスクを用いエッチングを行うことにより、上記ｎ型コンタクト層及び上記ｐ型ベース層を貫通して上記ｎ型層内の上記溝下部電界シールド手段に達する深さを有する溝を形成する工程と、上記溝の底面及び側壁上にゲート酸化膜を形成する工程と、上記ゲート酸化膜を介在させて上記溝の側壁上にゲート電極を形成する工程と、上記ｎ型コンタクト層及び上記ｐ型コンタクト領域に接触させてソース電極を形成する工程と、上記基板の下面にドレイン電極を形成する工程とを備えた半導体装置の製造方法であり、溝の下部に電界シールドのためのｐ型領域を備えているので、ゲート酸化膜部、特に、電界集中の起こりやすい溝下部の角のゲート酸化膜の電界強度が緩和されるため、ゲート酸化膜の絶縁破壊が生じないので、ＳｉＣ材料の絶縁特性に対応した、素子耐圧を得ることができる。
【図面の簡単な説明】
【図１】 本発明の実施の形態１によるトレンチゲート型のＳｉＣ半導体ＭＯＳ電界効果パワートランジスタ半導体装置の断面図である。
【図２】 本発明の実施の形態２によるトレンチゲート型のＳｉＣ半導体ＭＯＳ電界効果パワートランジスタ半導体装置の断面図である。
【図３】 本発明の実施の形態３によるトレンチゲート型のＳｉＣ半導体ＭＯＳ電界効果パワートランジスタ半導体装置の断面図である。
【図４】 本発明の実施の形態４によるトレンチゲート型のＳｉＣ半導体ＭＯＳ電界効果パワートランジスタ半導体装置の断面図である。
【図５】 本発明の実施の形態４による他のトレンチゲート型のＳｉＣ半導体ＭＯＳ電界効果パワートランジスタ半導体装置の断面図である。
【図６】 従来のトレンチゲート型のＳｉＣ半導体ＭＯＳ電界効果パワートランジスタ半導体装置の断面図である。
【図７】 従来のウエハー表面にＭＯＳチャネルを持つ構造のＳｉＣ半導体ＭＯＳ電界効果パワートランジスタ半導体装置の断面図である。
【符号の説明】
１ ｎ型のＳｉＣ基板、２ ドリフト領域、３ ベース領域、４ ｎコンタクト領域、５ ｐコンタクト領域、６ トレンチ部、７ ゲート酸化膜、８ ゲート電極、９ チャネル部、１０ ソース電極、１１ ドレイン電極、１２ トレンチ下部電界シールド領域、１３ ベース領域下部電界シールド領域、１４ 電界シールド結合領域、１５ 電流拡散層。[0001]
BACKGROUND OF THE INVENTION
  The present inventionHalfBACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a conductor device, and in particular, a semiconductor device used as a MOS field effect power transistor using a trench gate type SiC (silicon carbide) semiconductor.SetIt relates to a manufacturing method.
[0002]
[Prior art]
A conventional MOS field effect power transistor using a trench gate type SiC semiconductor is disclosed in, for example, the IEICE Transactions C-II Vol. J81-C-II, no. 1 on page 135 of FIG. 1, and the current is controlled by the gate portion of the MOS structure provided on the sidewall of the trench to perform high voltage switching.
[0003]
FIG. 6 is a conceptual diagram of a conventional MOS field effect power transistor semiconductor device using such a trench gate type SiC semiconductor. In the figure, 101 is an n-type SiC substrate, 102 is a low impurity n-type conductivity SiC drift region formed by epi-growth, 103 is a p-type conductive base region formed by epi-growth or ion implantation, 104 is an n-type conductive n-contact region formed by epi-growth or ion implantation, 105 is a p-type conductive p-contact region formed by epi-growth or ion implantation, 106 is a trench formed by etching, 107 is a gate An oxide film 108 is a gate electrode formed on the gate oxide film 107, 109 is a channel portion formed by a voltage applied to the gate electrode 108, 110 is a source electrode, and 111 is a drain electrode.
[0004]
The operation will be described. By applying a voltage to the gate electrode 108 with a high voltage applied between the source electrode 110 and the drain electrode 111, an n-type inversion layer is formed in the channel portion 109 of the p-type conductive base region 103, and the n-type inversion layer is formed. A current is conducted between the conductive contact region 104 and the drift region 102, and a current flows to the drain electrode 111 through the drift region 102. In the off state where no voltage is applied to the gate electrode 108, the n-type inversion layer is not formed in the channel portion 109. At this time, the high voltage applied between the source electrode 110 and the drain electrode 111 is applied to the drift region 102 and the p base. It is blocked by a depletion layer extending to the region 103.
[0005]
Next, a manufacturing method will be described. A conventional trench gate type SiC semiconductor MOS field effect power transistor is manufactured as follows. A low impurity n-type layer for the drift region 102 is grown on the SiC substrate 101 by epi growth, and then a p-type layer for the p-type conductive base region 103 is grown, and then n High-impurity n-type layers are sequentially grown for the contact region 104. Next, for example, masking is performed and etching is performed to form the trench portion 6. Next, another masking is performed, and ion implantation for p-contact is selectively performed on the surface of the p-contact region 105, and then the implanted impurity is electrically activated and activated as an acceptor. Therefore, for example, annealing is performed at 1500 ° C. for about 1 hour in an Ar atmosphere to form the p contact region 105. Next, thermal oxidation of the SiC surface is performed in an oxygen atmosphere containing a water vapor partial pressure to form the gate oxide film 7, and then the gate electrode 8, the source electrode 10, and the drain electrode 11 are formed.
[0006]
Here, an example in which the p contact region 105 is formed by ion implantation has been described. However, the present invention is not limited to this, and conversely, for example, a layer corresponding to the p contact region 105 is formed by epi growth, Nitrogen ions are implanted into the region, and then the implanted impurities are electrically activated and activated as donors. For example, annealing is performed at 1500 ° C. for about 1 hour in an Ar atmosphere. The n contact region 104 may be formed.
[0007]
FIG. 7 shows a structure as shown on page 135 of, for example, IEICE Transactions C-II, Vol. J81-C-II, No. 1, which has a MOS channel on a conventional wafer surface. It is a conceptual diagram of the MOS field effect power transistor semiconductor device using this SiC semiconductor. 201 is an n-type SiC substrate, 202 is a low-impurity n-type conductivity SiC drift region formed by epi growth, 203 is a p-type conductive base region formed by ion implantation, and 204 is formed by ion implantation. N-type conductive n contact region, 207 is a gate oxide film, 208 is a gate electrode, 209 is a channel portion formed by a voltage applied to the gate electrode, 210 is a source electrode, and 211 is a drain electrode. As in FIG. 6, by applying a voltage to the gate electrode 208, an n-type inversion layer is formed in the channel portion 209 on the surface of the p-type conductive base region 203, and between the n-type conductive contact region 204 and the drift region 202. , And the current flows through the drift region 202 to the drain electrode 211.
[0008]
[Problems to be solved by the invention]
SiC has a dielectric breakdown electric field strength 10 times larger than Si. When the structure of the element is optimized so as to improve the element characteristics by utilizing this feature, an electric field close to ten times the dielectric breakdown electric field strength of Si exists in SiC. For this reason, in the MOS field effect power transistor using the conventional trench gate type SiC semiconductor of FIG. 6 as described above, even in the gate oxide film in contact with the SiC portion where the electric field close to the breakdown electric field strength is generated, An electric field determined by the dielectric constant ratio of the two is generated, and its strength exceeds the dielectric breakdown electric field strength of the oxide film, so that dielectric breakdown occurs in the oxide film. Further, in the trench gate structure, electric field concentration occurs particularly at the corner portion of the lower portion of the trench, and the electric field strength in the oxide film increases, and coupled with the above reason, dielectric breakdown is likely to occur in the gate oxide film. As a result, the conventional MOS field effect power transistor using the trench gate type SiC semiconductor has a problem that the element breakdown voltage expected from the material characteristics of SiC cannot be obtained.
[0009]
On the other hand, in the conventional MOS power transistor having a MOS channel structure on the surface of the substrate shown in FIG. 7, the impurity is electrically activated after the impurity is implanted. It is necessary to perform annealing for 1 hour. At this time, Si on the surface is selectively detached, or the surface is partially unevenly grown or etched, resulting in a rough surface on the SiC surface or a stepped step structure being formed. there were. In a MOS power transistor having a MOS channel structure on the surface of the substrate, the roughened or stepped surface becomes the MOS channel interface, so that sufficient channel characteristics cannot be obtained due to deterioration of the MOS interface. there were.
[0010]
In addition, in a structure having a MOS channel on the substrate surface, a 112 bar 0 plane wafer having a high channel mobility is used to manufacture a 112 bar 0 plane wafer which is difficult to obtain in order to use it as an interface of the MOS channel. Unlike the process of the substrate surface, there is a problem that manufacturing conditions such as epi-growth, implantation, and electrodes are necessary.
[0011]
  The present invention has been made to solve such problems, and has a structure in which a portion with a strong electric field distribution in SiC is located away from the gate oxide film, and the gate oxide film is not destroyed. In addition, a semiconductor device having an element breakdown voltage corresponding to the material characteristics of SiC.SetAn object is to provide a manufacturing method.
[0012]
[Means for Solving the Problems]
  This inventionForming an n-type layer made of a low-impurity n-type conductive silicon carbide semiconductor on a substrate made of a silicon carbide semiconductor; and a p-type conductive silicon carbide semiconductor on the n-type layer A step of forming a p-type base layer comprising: a step of forming an n-type contact layer made of a silicon carbide semiconductor having high impurity n-type conductivity on the p-type base layer; and the p-type base layer A step of forming a p-type contact region made of a silicon carbide semiconductor in a region where the n-type contact layer is not provided above, and ion implantation using a mask are performed in the n-type layer when a high voltage is cut off. Forming a groove lower field shield means for shielding the invasion of an electric field from the n-type layer into the gate oxide film by the p-type region, and forming an activation anion after forming the groove lower field shield means. An activation annealing step for performing etching, and after the activation annealing step, etching is performed using the mask, thereby penetrating the n-type contact layer and the p-type base layer and lowering the groove in the n-type layer. A step of forming a groove having a depth reaching the electric field shielding means, a step of forming a gate oxide film on the bottom and side walls of the groove, and a gate electrode on the side wall of the groove with the gate oxide film interposed therebetween. A method of manufacturing a semiconductor device, comprising: a step of forming; a step of forming a source electrode in contact with the n-type contact layer and the p-type contact region; and a step of forming a drain electrode on the lower surface of the substrate. .
[0026]
DETAILED DESCRIPTION OF THE INVENTION
Embodiment 1 FIG.
FIG. 1 shows an embodiment of the present invention, and is a cross-sectional view of a trench gate type SiC semiconductor MOS field effect power transistor semiconductor device. Reference numeral 1 denotes an n-type SiC substrate, 2 denotes a drift region having low impurity n-type conductivity, 3 denotes a p-type conductive base region for forming a drain current control MOS channel, and 4 denotes n-type conductivity N contact region 5, p contact region 5 of p-type conductivity, 6 a trench portion formed by etching, 7 a gate oxide film provided on the bottom and side walls of trench portion 6, 8 a gate electrode, 9 A channel portion formed by a voltage applied to the gate electrode, 10 is a source electrode, 11 is a drain electrode, 12 is an epitaxial growth or ion implantation under the trench portion 6 in order to relax the electric field strength of the gate oxide film 7 portion. A p-type conductive trench lower field shield region formed by the above-described process, and a p-type conductive base region 13 formed by epi-growth or ion implantation under the p-type base region 3. Which is the lower electric field shield region.
[0027]
The operation will be described. By applying a voltage to the gate electrode 8, an n-type inversion layer is formed in the channel portion 9, a current is conducted between the n-type conductive n-contact region 4 and the drift region 2, and the drain electrode passes through the drift region 2. A current flows through 11. In the off state where no voltage is applied to the gate electrode 8, the n-type inversion layer is not formed in the channel portion 9. At this time, the high voltage applied between the source electrode 10 and the drain electrode 11 is blocked by the depletion layer extending to the drift region 2, the trench lower field shield region 12, and the base region lower field shield region 13. Here, in the present embodiment, since the trench lower field shield 12 is provided below the trench portion 6, the electric field penetration is prevented thereby, and the gate oxide film 7 portion, particularly, the trench portion 6 where electric field concentration occurs. The electric field strength at the lower corner is relaxed, and the dielectric breakdown of the gate oxide film 7 does not occur. Further, since the base region lower electric field shield region 13 is also provided under the p base region 3, the electric field intrusion from below the p base region is shielded, so that the electric field strength of the gate oxide film 7 is relaxed. With such a structure, the strongest portion of the electric field strength at the time of reverse high voltage interruption is the lower end of the shield region 13, and the portion where the electric field strength is strong and the portion contacting the gate oxide film 7 are separated without contact. Therefore, the dielectric breakdown of the oxide film does not occur.
[0028]
Next, a manufacturing method will be described. The trench gate type SiC semiconductor MOS field effect power transistor shown in the present embodiment can be manufactured as follows, for example. On the SiC substrate 1, a low impurity n-type layer for the drift region 2 is grown by CVD epi growth, then a p-type layer for the p-type conductive base region 3 is grown, and then High impurity n-type layers are sequentially grown for the n contact region 4. Next, masking is performed, and a p-contact region 5 is selectively implanted into the surface of the p-contact region 5 to form a p-contact region 5, and then, for example, the same mask is used. The base region lower electric field shield region 13 is formed by performing Al ion implantation in the vertical direction (that is, in the depth direction) to a region deeper than the depth of the lower portion (bottom surface) of the trench portion 6. Next, for example, another masking is performed, and Al (acceptor) is ion-implanted in a region deeper than the depth (bottom surface) of the trench portion 6 to form the trench lower electric field shield region 12. . At this time, the thickness of the trench lower electric field shield region 12 is set to a predetermined thickness sufficient to prevent the electric field from entering the oxide gate film 7 from the drift region 2. Next, for example, using the same mask, etching is performed to form the trench portion 6. Next, for example, thermal oxidation of the SiC surface is performed in an oxygen atmosphere including a water vapor partial pressure to form the gate oxide film 7, and then the gate electrode 8, the source electrode 10, and the drain electrode 11 are formed.
[0029]
In this example, an example in which the p contact region 5 is formed by ion implantation in an n-type layer that is epitaxially grown with a high impurity for the n contact region 4 is shown, but conversely, a p layer for the p contact region 5 is formed. Can also be formed by forming the n contact region 4 by ion implantation of nitrogen therein. Although an example in which the p-type layer for the p base region 3 is formed by epi-growth is shown here, ion implantation is also possible.
[0030]
As described above, in the semiconductor device shown in the present embodiment, since the trench lower electric field shield region 12 is provided below the trench portion 6, the electric field strength of the gate oxide film 7 is relaxed. Further, since the base region lower electric field shield region 13 is also provided under the p base region 3, the electric field intrusion from below the p base region is shielded, so that the electric field strength of the gate oxide film 7 is relaxed. With such a structure, the strongest portion of the electric field strength at the time of reverse high voltage interruption is the lower end of the p shield region, and the portion having the strong electric field strength and the portion in contact with the gate oxide film 7 are separated without contact. As a result, dielectric breakdown of the oxide film does not occur. As a result, the electric field strength of the gate oxide film 7 at the time of high voltage interruption is reduced, the dielectric breakdown of the gate oxide film 7 is prevented, and the device breakdown voltage corresponding to the insulation characteristics of the SiC material can be obtained.
[0031]
Further, in the manufacturing method shown in the present embodiment, ion implantation and activation annealing are performed in a step before forming the trench portion 6, and then the trench portion 6 is formed and its side wall is used as a channel. Therefore, it is possible to reduce the damage of implantation caused on the side wall of the trench portion 6 where the channel is formed and the roughness of the surface due to annealing, and the effect of being able to form a channel with high mobility and high reliability. Yes, device characteristics can be improved.
[0032]
Embodiment 2. FIG.
FIG. 2 shows another embodiment of the present invention and is a sectional view of a trench gate type SiC semiconductor MOS field effect power transistor semiconductor device. 1 is an n-type SiC substrate, 2 is a drift region, 3 is a base region, 4 is an n contact region, 5 is a p contact region, 6 is a trench portion, 7 is a gate oxide film, 8 is a gate electrode, and 9 is a channel portion. 10 is a source electrode, 11 is a drain electrode, 12 is a trench lower electric field shield region, 13 is a p-type conductive base region lower electric field shield region, and 14 is a trench lower electric field shield region 12 and a base region lower electric field shield region 13. An electric field shield coupling region for electrical coupling is shown. The principle of high voltage cutoff and conduction switching by applying voltage to the gate electrode 8 and the principle of electric field relaxation in the oxide film by the electric field shield region are the same as in the first embodiment.
[0033]
Next, a manufacturing method will be described. The trench gate type SiC semiconductor MOS field effect power transistor shown in the present embodiment can be manufactured as follows, for example. On the SiC substrate 1, a low impurity n-type layer for the drift region 2, a p-type layer for the p base region 3, and a high impurity n-type layer for the n contact region 4 are sequentially grown. Next, masking is performed, and ion implantation of high-concentration Al for contact is selectively performed on the surface of the p-contact region 5 part, and then Al ion implantation is performed to a region deeper than the depth below the trench using, for example, the same mask. The base region lower electric field shield region 13 is formed. Next, for example, another masking is performed to selectively implant the trench portion 6 and the electric field shield coupling region 14 into a region deeper than the depth below the trench, thereby forming the lower trench electric field shield region 12 and the electric field shield coupling region 14. Form. Next, for example, using another mask, etching is performed to form the trench portion 6. After forming the next gate oxide film 7, a gate electrode 8, a source electrode 10, and a drain electrode 11 are formed.
[0034]
In this example, a manufacturing method is shown in which the trench lower field shield region 12, the base region lower field shield region 13, and the field shield coupling region 14 are formed by ion implantation in the drift region. It is also possible to form an n-type conductive region by forming the layer by epi-growth and implanting nitrogen ions into regions other than the three regions.
[0035]
As described above, in the semiconductor device according to the present embodiment, the electric field strength of the gate oxide film 7 is relaxed by the trench lower electric field shield region 12 and the base region lower electric field shield region 13, and the dielectric breakdown of the oxide film is reduced. Is the same as in the first embodiment. Further, in this embodiment, since the p base region and the p shield region are electrically coupled, there is no potential floating region, and no charge accumulation occurs. High reliability of switching operation and oxide film can be obtained.
[0036]
Also in the manufacturing method in the present embodiment, as in the first embodiment, since the ion implantation and the activation annealing can be performed in the process before the trench portion 6 is formed, a channel is formed. Implant damage generated on the side wall of the trench 6 to be formed and surface roughness due to annealing can be reduced, and a channel having high mobility and high reliability can be formed, and the device characteristics can be improved.
[0037]
Embodiment 3 FIG.
FIG. 3 shows another embodiment of the present invention, and is a cross-sectional view of a trench gate type SiC semiconductor MOS field effect power transistor semiconductor device. 1 is an n-type SiC substrate, 2 is a drift region, 3 is a base region, 4 is an n contact region, 5 is a p contact region, 6 is a trench portion, 7 is a gate oxide film, 8 is a gate electrode, and 9 is a channel portion. 10 is a source electrode, 11 is a drain electrode, 12 is a trench lower electric field shield region, 13 is a base region lower electric field shield region, 14 is an electric field shield coupling region, and 15 is a p base region for reducing resistance during conduction. This is an n-type current diffusion layer provided in the lower part and having higher conductivity (ie, higher carrier concentration) than the drift region 2. The principle of electric field relaxation in the oxide film by applying a voltage to the gate electrode 8 to cut off high voltage, switching conduction, and effect of the electric field shield region is the same as in the first and second embodiments.
[0038]
Next, a manufacturing method will be described. The trench gate type SiC semiconductor MOS field effect power transistor shown in the present embodiment can be manufactured as follows, for example. On SiC substrate 1, a low impurity n-type layer for drift region 2, then an n-type layer having higher conductivity than drift region 2 for current diffusion layer 15, and then for p base region 3 Next, a high impurity n-type layer for the n-contact region 4 is successively grown. Similarly to the second embodiment, the p contact region 5, the base region lower electric field shield region 13, the trench lower electric field shield region 12, and the electric field shield coupling region 14 are formed by ion implantation of Al. Next, the n contact region 4 is formed by, for example, donor ion implantation using another masking. Next, for example, using another mask, etching is performed to form the trench portion 6. Next, after forming the gate oxide film 7, the gate electrode 8, the source electrode 10, and the drain electrode 11 are formed. In this example, a manufacturing example in which a current diffusion layer is formed by epi-growth is shown, but a manufacturing example in which a current diffusion layer is formed by ion implantation of a donor is also possible.
[0039]
As described above, the semiconductor device described in the present embodiment can obtain the same effects as those of the first and second embodiments described above, and is more conductive than the drift region 2 below the p base region 3. Since the high n-type current diffusion layer 15 is provided, when conducting, the current path is not only from the vicinity of the channel 9 formed by reversal by application of the gate voltage, but from the entire n-type current diffusion layer 15 to the n-type. Since the current flows through the drift region 2, the resistance is effectively reduced as compared with the case where the current diffusion layer 15 is not provided.
[0040]
Also in the manufacturing method in the present embodiment, as in the first embodiment, since the ion implantation and the activation annealing can be performed in the process before the trench portion 6 is formed, a channel is formed. Implant damage generated on the side wall of the trench 6 to be formed and surface roughness due to annealing can be reduced, and a channel having high mobility and high reliability can be formed, and the device characteristics can be improved.
[0041]
Embodiment 4 FIG.
FIG. 4 shows another embodiment of the present invention and is a sectional view of a trench gate type SiC semiconductor MOS field effect power transistor semiconductor device. 1 is an n-type SiC substrate, 2 is a drift region, 3 is a base region, 4 is an n contact region, 5 is a p contact region, 6 is a trench portion, 7 is a gate oxide film, 8 is a gate electrode, and 9 is a channel portion. 10 is a source electrode, 11 is a drain electrode, 12A is wider than the width of the trench portion 6, and has a structure extending laterally to a region without the trench portion 6, and 13 is a lower portion of the base region. The electric field shield region 15 is a current diffusion layer. The principles of high voltage cutoff and conduction switching by applying a voltage to the gate electrode 8, and electric field relaxation in the gate oxide film 7 and resistance reduction by the current diffusion layer 15 due to the effects of the electric field shield regions 12 and 13 are as follows. This is the same as in the first to third embodiments.
[0042]
Next, a manufacturing method will be described. The trench gate type SiC semiconductor MOS field effect power transistor shown in the present embodiment can be manufactured as follows, for example. On SiC substrate 1, a low impurity n-type layer for drift region 2, then an n-type layer for current diffusion layer 15, then a p-type layer for p base region 3, and then n A high impurity n-type layer for the contact region 4 is sequentially grown. Similarly to the third embodiment, the p contact region 5, the base region lower electric field shield region 13, the trench lower electric field shield region 12, and the electric field shield coupling region 14 are formed by ion implantation of Al. At this time, by making the mask pattern for implanting the trench lower electric field shield region 12 wider than the width of the trench portion 6, it is possible to form an implantation region extending to a lateral region without the trench portion 6 on the upper portion. Next, an n-contact region 4 is formed by donor ion implantation. After the next trench portion 6 is formed and the gate oxide film 7 is formed, the gate electrode 8, the source electrode 10, and the drain electrode 11 are formed. In this example, a manufacturing example in which a current diffusion layer is formed by epi-growth is shown, but a manufacturing example in which a current diffusion layer is formed by ion implantation of a donor is also possible.
[0043]
As described above, the semiconductor device shown in the present embodiment can obtain the same effects as those of the first to third embodiments, and the width of the trench lower shield region 12 is wider than the width of the groove. The structure extends to a region without the upper trench portion 6, and in particular, the corner portion at the lower portion of the trench and the portion having a high electric field strength are separated from each other even in a planar position. The effect of relaxing the applied electric field strength is great, and there is a feature that dielectric breakdown of the oxide film does not occur.
[0044]
Also in the manufacturing method in the present embodiment, as in the first embodiment, since the ion implantation and the activation annealing can be performed in the process before the trench portion 6 is formed, a channel is formed. Implant damage generated on the side wall of the trench 6 to be formed and surface roughness due to annealing can be reduced, and a channel having high mobility and high reliability can be formed, and the device characteristics can be improved.
[0045]
FIG. 5 shows another configuration of the fourth embodiment, and shows an example in which the trench lower electric field shield region 12 is wide and the base region lower electric field shield region 13 is not provided. It can be produced in the same manner as in FIG. 4 and has the same effect of suppressing dielectric breakdown of the oxide film.
[0046]
Embodiment 5 FIG.
Next, another embodiment of the present invention will be described. The semiconductor device described in this embodiment has the same element structure and manufacturing method as those in Embodiments 1 to 4, and has an effect of suppressing the dielectric breakdown of the gate oxide film 7 by the electric field shielding effect. In the present embodiment, the channel 9 is formed on the side wall of the trench portion 6 on the 1st, 2nd, and 0th planes of SiC crystal formed by etching. Due to the crystal orientation dependence of the channel mobility, a larger mobility than the channel formed on the substrate surface can be obtained, and the channel resistance can be reduced. At the same time, since the p region for electric field shielding is provided, the dielectric breakdown of the oxide film hardly occurs.
[0047]
【The invention's effect】
  This inventionForming an n-type layer made of a low-impurity n-type conductive silicon carbide semiconductor on a substrate made of a silicon carbide semiconductor; and a p-type conductive silicon carbide semiconductor on the n-type layer A step of forming a p-type base layer comprising: a step of forming an n-type contact layer made of a silicon carbide semiconductor having high impurity n-type conductivity on the p-type base layer; and the p-type base layer A step of forming a p-type contact region made of a silicon carbide semiconductor in a region where the n-type contact layer is not provided above, and ion implantation using a mask are performed in the n-type layer when a high voltage is cut off. Forming a groove lower field shield means for shielding the invasion of an electric field from the n-type layer into the gate oxide film by the p-type region, and forming an activation anion after forming the groove lower field shield means. An activation annealing step for performing etching, and after the activation annealing step, etching is performed using the mask, thereby penetrating the n-type contact layer and the p-type base layer and lowering the groove in the n-type layer. A step of forming a groove having a depth reaching the electric field shielding means, a step of forming a gate oxide film on the bottom and side walls of the groove, and a gate electrode on the side wall of the groove with the gate oxide film interposed therebetween. A method of manufacturing a semiconductor device, comprising: a step of forming a source electrode in contact with the n-type contact layer and the p-type contact region; and a step of forming a drain electrode on the lower surface of the substrateSince the p-type region for electric field shielding is provided at the lower part of the groove, the electric field strength of the gate oxide film part, particularly, the gate oxide film at the corner of the lower part of the groove where electric field concentration is likely to occur is relaxed. Since breakdown of the gate oxide film does not occur, an element withstand voltage corresponding to the insulation characteristics of the SiC material can be obtained.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view of a trench gate type SiC semiconductor MOS field effect power transistor semiconductor device according to a first embodiment of the present invention.
FIG. 2 is a cross-sectional view of a trench gate type SiC semiconductor MOS field effect power transistor semiconductor device according to a second embodiment of the present invention.
FIG. 3 is a cross-sectional view of a trench gate type SiC semiconductor MOS field effect power transistor semiconductor device according to a third embodiment of the present invention.
FIG. 4 is a sectional view of a trench gate type SiC semiconductor MOS field effect power transistor semiconductor device according to a fourth embodiment of the present invention.
FIG. 5 is a cross-sectional view of another trench gate type SiC semiconductor MOS field effect power transistor semiconductor device according to Embodiment 4 of the present invention;
FIG. 6 is a cross-sectional view of a conventional trench gate type SiC semiconductor MOS field effect power transistor semiconductor device.
FIG. 7 is a cross-sectional view of a conventional SiC semiconductor MOS field effect power transistor semiconductor device having a MOS channel structure on the wafer surface.
[Explanation of symbols]
1 n-type SiC substrate, 2 drift region, 3 base region, 4 n contact region, 5 p contact region, 6 trench portion, 7 gate oxide film, 8 gate electrode, 9 channel portion, 10 source electrode, 11 drain electrode, 12 trench lower electric field shield region, 13 base region lower electric field shield region, 14 electric field shield coupling region, 15 current diffusion layer.

Claims (1)

炭化珪素半導体からなる基板上に、低不純物のｎ型の導電性を有する炭化珪素半導体からなるｎ型層を形成する工程と、
上記ｎ型層上に、ｐ型の導電性を有する炭化珪素半導体からなるｐ型ベース層を形成する工程と、
上記ｐ型ベース層上に、高不純物のｎ型の導電性を有する炭化珪素半導体からなるｎ型コンタクト層を形成する工程と、
上記ｐ型ベース層上の上記ｎ型コンタクト層が設けられていない領域に炭化珪素半導体からなるｐ型コンタクト領域を形成する工程と、
マスクを用いイオン注入を行うことにより、上記ｎ型層内に、高電圧遮断時の上記ｎ型層からのゲート酸化膜への電界の侵入をシールドさせるための溝下部電界シールド手段をｐ型領域によって形成する工程と、
上記溝下部電界シールド手段を形成した後に活性化アニールを行なう活性化アニール工程と、
上記活性化アニール工程後に、上記マスクを用いエッチングを行うことにより、上記ｎ型コンタクト層及び上記ｐ型ベース層を貫通して上記ｎ型層内の上記溝下部電界シールド手段に達する深さを有する溝を形成する工程と、
上記溝の底面及び側壁上にゲート酸化膜を形成する工程と、
上記ゲート酸化膜を介在させて上記溝の側壁上にゲート電極を形成する工程と、
上記ｎ型コンタクト層及び上記ｐ型コンタクト領域に接触させてソース電極を形成する工程と、
上記基板の下面にドレイン電極を形成する工程と、
を備えたことを特徴とする半導体装置の製造方法。Forming an n-type layer made of a low-impurity n-type conductive silicon carbide semiconductor on a substrate made of a silicon carbide semiconductor;
Forming a p-type base layer made of a silicon carbide semiconductor having p-type conductivity on the n-type layer;
Forming an n-type contact layer made of a high-impurity n-type conductive silicon carbide semiconductor on the p-type base layer;
Forming a p-type contact region made of a silicon carbide semiconductor in a region where the n-type contact layer is not provided on the p-type base layer;
By ion implantation using a mask on the n-type layer, p-type region a groove bottom field shielding means for shielding the electric field from entering the gate oxide film from the n-type layer at a high voltage blocking A step of forming by:
An activation annealing step of performing activation annealing after forming the groove lower field shielding means;
Etching using the mask after the activation annealing step has a depth that penetrates the n-type contact layer and the p-type base layer and reaches the groove lower field shield means in the n-type layer. Forming a groove;
Forming a gate oxide film on the bottom and side walls of the trench;
Forming a gate electrode on the sidewall of the groove with the gate oxide film interposed therebetween;
Forming a source electrode in contact with the n-type contact layer and the p-type contact region;
Forming a drain electrode on the lower surface of the substrate;
A method for manufacturing a semiconductor device, comprising:
JP2000072298A 2000-03-15 2000-03-15 Manufacturing method of semiconductor device Expired - Lifetime JP4738562B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2000072298A JP4738562B2 (en) 2000-03-15 2000-03-15 Manufacturing method of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2000072298A JP4738562B2 (en) 2000-03-15 2000-03-15 Manufacturing method of semiconductor device

Publications (2)

Publication Number Publication Date
JP2001267570A JP2001267570A (en) 2001-09-28
JP4738562B2 true JP4738562B2 (en) 2011-08-03

Family

ID=18590734

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2000072298A Expired - Lifetime JP4738562B2 (en) 2000-03-15 2000-03-15 Manufacturing method of semiconductor device

Country Status (1)

Country Link
JP (1) JP4738562B2 (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10164021B2 (en) 2017-05-26 2018-12-25 Fuji Electric Co., Ltd. Silicon carbide semiconductor device
US10468509B2 (en) 2017-06-07 2019-11-05 Fuji Electric Co., Ltd. Semiconductor device and method of manufacturing semiconductor device
US11205719B2 (en) 2019-03-22 2021-12-21 Fuji Electric Co., Ltd. Insulated-gate semiconductor device

Families Citing this family (59)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3434278B2 (en) * 2000-04-06 2003-08-04 松下電器産業株式会社 Field effect transistor and method of manufacturing the same
US6853033B2 (en) * 2001-06-05 2005-02-08 National University Of Singapore Power MOSFET having enhanced breakdown voltage
KR100479426B1 (en) * 2002-08-27 2005-03-30 학교법인 한양학원 High-Voltage Device Structure and It's Fabrication Process
KR100958561B1 (en) 2002-10-04 2010-05-17 신덴겐코교 가부시키가이샤 Semiconductor device and process for fabricating the same
JP4538211B2 (en) * 2003-10-08 2010-09-08 トヨタ自動車株式会社 Insulated gate semiconductor device and manufacturing method thereof
KR100767078B1 (en) 2003-10-08 2007-10-15 도요다 지도샤 가부시끼가이샤 Insulated gate type semiconductor device and manufacturing method thereof
JP3689419B1 (en) * 2004-03-29 2005-08-31 新電元工業株式会社 Semiconductor device and method for manufacturing semiconductor device
JP2008071896A (en) * 2006-09-13 2008-03-27 Nippon Steel Corp Metal-insulating film-silicon carbide semiconductor structure
JP5261907B2 (en) * 2006-09-19 2013-08-14 富士電機株式会社 Trench gate type silicon carbide semiconductor device
JP5037103B2 (en) * 2006-12-06 2012-09-26 三菱電機株式会社 Silicon carbide semiconductor device
JP4450241B2 (en) * 2007-03-20 2010-04-14 株式会社デンソー Method for manufacturing silicon carbide semiconductor device
JP4798119B2 (en) * 2007-11-06 2011-10-19 株式会社デンソー Silicon carbide semiconductor device and manufacturing method thereof
JP5444608B2 (en) * 2007-11-07 2014-03-19 富士電機株式会社 Semiconductor device
US7989882B2 (en) * 2007-12-07 2011-08-02 Cree, Inc. Transistor with A-face conductive channel and trench protecting well region
JP4577355B2 (en) 2007-12-26 2010-11-10 株式会社デンソー Silicon carbide semiconductor device and manufacturing method thereof
EP2091083A3 (en) * 2008-02-13 2009-10-14 Denso Corporation Silicon carbide semiconductor device including a deep layer
JP4793390B2 (en) * 2008-02-13 2011-10-12 株式会社デンソー Silicon carbide semiconductor device and manufacturing method thereof
JP5721308B2 (en) * 2008-03-26 2015-05-20 ローム株式会社 Semiconductor device
JP4640436B2 (en) * 2008-04-14 2011-03-02 株式会社デンソー Method for manufacturing silicon carbide semiconductor device
JP5353190B2 (en) * 2008-11-04 2013-11-27 トヨタ自動車株式会社 Semiconductor device and manufacturing method of semiconductor device
JP5613995B2 (en) * 2009-04-28 2014-10-29 富士電機株式会社 Silicon carbide semiconductor device and manufacturing method thereof
JP5531787B2 (en) * 2010-05-31 2014-06-25 株式会社デンソー Silicon carbide semiconductor device and manufacturing method thereof
JP5110153B2 (en) 2010-11-08 2012-12-26 住友電気工業株式会社 Semiconductor device and manufacturing method thereof
JP5745997B2 (en) * 2011-10-31 2015-07-08 トヨタ自動車株式会社 Switching element and manufacturing method thereof
EP2602829A1 (en) 2011-12-07 2013-06-12 Nxp B.V. Trench-gate resurf semiconductor device and manufacturing method
JP5685736B2 (en) 2012-02-10 2015-03-18 パナソニックＩｐマネジメント株式会社 Semiconductor device and manufacturing method thereof
JP5884617B2 (en) 2012-04-19 2016-03-15 株式会社デンソー Silicon carbide semiconductor device and manufacturing method thereof
JP5751213B2 (en) 2012-06-14 2015-07-22 株式会社デンソー Silicon carbide semiconductor device and manufacturing method thereof
JP6177812B2 (en) 2013-02-05 2017-08-09 三菱電機株式会社 Insulated gate type silicon carbide semiconductor device and method of manufacturing the same
US9142668B2 (en) 2013-03-13 2015-09-22 Cree, Inc. Field effect transistor devices with buried well protection regions
US9306061B2 (en) * 2013-03-13 2016-04-05 Cree, Inc. Field effect transistor devices with protective regions
US9349856B2 (en) 2013-03-26 2016-05-24 Toyoda Gosei Co., Ltd. Semiconductor device including first interface and second interface as an upper surface of a convex protruded from first interface and manufacturing device thereof
JP5834179B2 (en) * 2013-04-16 2015-12-16 パナソニックＩｐマネジメント株式会社 Method for manufacturing silicon carbide semiconductor device
JP2014241368A (en) * 2013-06-12 2014-12-25 住友電気工業株式会社 Silicon carbide semiconductor device
JP6135364B2 (en) 2013-07-26 2017-05-31 住友電気工業株式会社 Silicon carbide semiconductor device and manufacturing method thereof
US9825164B2 (en) 2013-08-01 2017-11-21 Mitsubishi Electric Corporation Silicon carbide semiconductor device and manufacturing method for same
JP2015072999A (en) * 2013-10-02 2015-04-16 株式会社デンソー Silicon carbide semiconductor device
JP6215647B2 (en) * 2013-10-22 2017-10-18 ルネサスエレクトロニクス株式会社 Semiconductor device and manufacturing method of semiconductor device
JP6199755B2 (en) * 2014-01-27 2017-09-20 トヨタ自動車株式会社 Semiconductor device
WO2015177914A1 (en) * 2014-05-23 2015-11-26 株式会社日立製作所 Semiconductor device, semiconductor device manufacturing method, power conversion device, three-phase motor system, automobile, and train car
US9954054B2 (en) * 2014-06-30 2018-04-24 Sumitomo Electric Industries, Ltd. Silicon carbide semiconductor device and method for manufacturing the same
US9960259B2 (en) * 2015-01-19 2018-05-01 Hitachi, Ltd. Semiconductor device, method for manufacturing same, power conversion device, three-phase motor system, automobile, and railway carriage
DE102015103072B4 (en) 2015-03-03 2021-08-12 Infineon Technologies Ag SEMI-CONDUCTOR DEVICE WITH A DITCH STRUCTURE INCLUDING A GATE ELECTRODE AND A CONTACT STRUCTURE FOR A DIODE AREA
JP6266166B2 (en) * 2015-03-30 2018-01-24 三菱電機株式会社 Silicon carbide semiconductor device and manufacturing method thereof
DE112016003510B4 (en) * 2015-10-16 2023-11-16 Fuji Electric Co., Ltd. SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCING A SEMICONDUCTOR DEVICE
JP6485382B2 (en) * 2016-02-23 2019-03-20 株式会社デンソー Method of manufacturing compound semiconductor device and compound semiconductor device
JP6531691B2 (en) 2016-03-24 2019-06-19 豊田合成株式会社 Method of manufacturing vertical trench MOSFET
JP6520785B2 (en) 2016-03-24 2019-05-29 豊田合成株式会社 Semiconductor device manufacturing method
JP6693020B2 (en) 2017-03-28 2020-05-13 豊田合成株式会社 Method of manufacturing semiconductor device
JP6809330B2 (en) 2017-03-28 2021-01-06 豊田合成株式会社 Manufacturing method of semiconductor devices
JP2019016668A (en) 2017-07-05 2019-01-31 三菱電機株式会社 Silicon carbide semiconductor device and manufacturing method of the same, and power conversion device
JP6847007B2 (en) * 2017-09-13 2021-03-24 株式会社日立製作所 Semiconductor devices and their manufacturing methods
JP7006280B2 (en) 2018-01-09 2022-01-24 富士電機株式会社 Semiconductor device
JP7076222B2 (en) 2018-02-21 2022-05-27 三菱電機株式会社 Semiconductor devices and their manufacturing methods, power conversion devices
JP7151363B2 (en) * 2018-10-16 2022-10-12 富士電機株式会社 Silicon carbide semiconductor device and method for manufacturing silicon carbide semiconductor device
US10903322B2 (en) * 2018-11-16 2021-01-26 Infineon Technologies Ag SiC power semiconductor device with integrated body diode
JP7242467B2 (en) 2019-08-02 2023-03-20 株式会社東芝 Semiconductor devices, inverter circuits, drive devices, vehicles, and elevators
JP7337469B1 (en) * 2022-03-03 2023-09-04 三菱電機株式会社 Semiconductor equipment and power conversion equipment
CN116469923B (en) * 2023-04-25 2023-10-20 南京第三代半导体技术创新中心有限公司 High-reliability trench silicon carbide MOSFET device and manufacturing method thereof

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05506335A (en) * 1991-01-31 1993-09-16 シリコニックス・インコーポレイテッド Power MOS field effect transistor
JPH06224437A (en) * 1992-07-24 1994-08-12 Siliconix Inc Field-effect transistor and manufacture thereof
JPH07131016A (en) * 1993-09-10 1995-05-19 Hitachi Ltd Fet transistor and fabrication thereof
JPH1098188A (en) * 1996-08-01 1998-04-14 Kansai Electric Power Co Inc:The Insulated gate semiconductor device
JPH10209432A (en) * 1997-01-21 1998-08-07 Mitel Semiconductor Ltd Improvement in semiconductor device
WO1998035390A1 (en) * 1997-02-07 1998-08-13 Cooper James Albert Jr Structure for increasing the maximum voltage of silicon carbide power transistors
JPH10308512A (en) * 1997-03-05 1998-11-17 Denso Corp Silicon carbide semiconductor device

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5658267A (en) * 1979-10-17 1981-05-21 Nippon Telegr & Teleph Corp <Ntt> Insulated gate type field-effect transistor
JP3288218B2 (en) * 1995-03-14 2002-06-04 三菱電機株式会社 Insulated gate semiconductor device and method of manufacturing the same
JP3409244B2 (en) * 1998-02-26 2003-05-26 株式会社豊田中央研究所 Semiconductor device

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05506335A (en) * 1991-01-31 1993-09-16 シリコニックス・インコーポレイテッド Power MOS field effect transistor
JPH06224437A (en) * 1992-07-24 1994-08-12 Siliconix Inc Field-effect transistor and manufacture thereof
JPH07131016A (en) * 1993-09-10 1995-05-19 Hitachi Ltd Fet transistor and fabrication thereof
JPH1098188A (en) * 1996-08-01 1998-04-14 Kansai Electric Power Co Inc:The Insulated gate semiconductor device
JPH10209432A (en) * 1997-01-21 1998-08-07 Mitel Semiconductor Ltd Improvement in semiconductor device
WO1998035390A1 (en) * 1997-02-07 1998-08-13 Cooper James Albert Jr Structure for increasing the maximum voltage of silicon carbide power transistors
JPH10308512A (en) * 1997-03-05 1998-11-17 Denso Corp Silicon carbide semiconductor device

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10164021B2 (en) 2017-05-26 2018-12-25 Fuji Electric Co., Ltd. Silicon carbide semiconductor device
US10468509B2 (en) 2017-06-07 2019-11-05 Fuji Electric Co., Ltd. Semiconductor device and method of manufacturing semiconductor device
US11205719B2 (en) 2019-03-22 2021-12-21 Fuji Electric Co., Ltd. Insulated-gate semiconductor device

Also Published As

Publication number Publication date
JP2001267570A (en) 2001-09-28

Similar Documents

Publication Publication Date Title
JP4738562B2 (en) Manufacturing method of semiconductor device
JP4744958B2 (en) Semiconductor device and manufacturing method thereof
US8748977B2 (en) Semiconductor device and method for producing same
US9490338B2 (en) Silicon carbide semiconductor apparatus and method of manufacturing same
KR100859701B1 (en) High voltage LDMOS transistor and method for fabricating the same
KR101613930B1 (en) Silicon carbide semiconductor device and method for manufacturing the same
JP4192281B2 (en) Silicon carbide semiconductor device
KR910000929B1 (en) Graded extended drain concept for reduced hot electron effect
KR100731141B1 (en) Semiconductor device and method for fabricating the same
TWI358835B (en) Schottky device and method of forming
CN102770960A (en) Semiconductor device and manufacturing method therefor
US11961904B2 (en) Semiconductor device including trench gate structure and buried shielding region and method of manufacturing
JP2000332239A (en) Field effect transistor
WO2003003452A2 (en) Field-effect transistor and method of making the same
KR20230059176A (en) Trench Semiconductor Devices Having Trench Bottom Shield Structures
JP2003224277A (en) Silicon carbide semiconductor device and its manufacturing method
CN114497201A (en) Field effect transistor of integrated body relay diode, preparation method thereof and power device
JP2001127285A (en) Vertical field-effect transistor
JP5037103B2 (en) Silicon carbide semiconductor device
JP3642768B2 (en) Horizontal high voltage semiconductor device
JP2018206872A (en) Semiconductor device
JP3496509B2 (en) Method for manufacturing silicon carbide semiconductor device
TWI829085B (en) Sic mosfet with reduced channel length and high vth
JP2004200441A (en) Semiconductor device and its manufacturing method
US11769828B2 (en) Gate trench power semiconductor devices having improved deep shield connection patterns

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20061030

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20100906

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20100921

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20101118

A02 Decision of refusal

Free format text: JAPANESE INTERMEDIATE CODE: A02

Effective date: 20101214

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20110311

A911 Transfer to examiner for re-examination before appeal (zenchi)

Free format text: JAPANESE INTERMEDIATE CODE: A911

Effective date: 20110318

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20110426

A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20110427

R150 Certificate of patent or registration of utility model

Ref document number: 4738562

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150

Free format text: JAPANESE INTERMEDIATE CODE: R150

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20140513

Year of fee payment: 3

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

EXPY Cancellation because of completion of term