JP4738562B2 - Manufacturing method of semiconductor device - Google Patents

Manufacturing method of semiconductor device Download PDF

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JP4738562B2
JP4738562B2 JP2000072298A JP2000072298A JP4738562B2 JP 4738562 B2 JP4738562 B2 JP 4738562B2 JP 2000072298 A JP2000072298 A JP 2000072298A JP 2000072298 A JP2000072298 A JP 2000072298A JP 4738562 B2 JP4738562 B2 JP 4738562B2
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JP2001267570A (en
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昌之 今泉
健一 大塚
博司 杉本
陽一郎 樽井
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三菱電機株式会社
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    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7813Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/0619Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
    • H01L29/0623Buried supplementary region, e.g. buried guard ring
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1095Body region, i.e. base region, of DMOS transistors or IGBTs
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843Source or drain regions of field-effect devices
    • H01L29/0847Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • H01L29/0852Source or drain regions of field-effect devices of field-effect transistors with insulated gate of DMOS transistors
    • H01L29/0873Drain regions
    • H01L29/0878Impurity concentration or distribution
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System
    • H01L29/1608Silicon carbide

Description

【0001】
【発明の属する技術分野】
本発明は半導体装置の製造方法に関し、特に、トレンチゲート型のSiC(炭化珪素)半導体を用いたMOS電界効果パワートランジスタとして用いる半導体装置の製造方法に関するものである。
【0002】
【従来の技術】
トレンチゲート型のSiC半導体を用いた従来のMOS電界効果パワートランジスタは、例えば、電子情報通信学会論文誌C−II Vol.J81−C−II、No.1の135ページの図2に示されるような構造であり、トレンチ側壁に設けたMOS構造のゲート部分で電流を制御し、高電圧のスイッチングを行う。
【0003】
図6は、従来のこのようなトレンチゲート型のSiC半導体を用いたMOS電界効果パワートランジスタ半導体装置の概念図である。図において、101はn型のSiC基板、102はエピ成長で形成した低不純物のn型の導電性を持つSiCのドリフト領域、103はエピ成長もしくはイオン注入により形成したp型導電性ベース領域、104はエピ成長もしくはイオン注入により形成したn型導電性のnコンタクト領域、105はエピ成長もしくはイオン注入により形成したp型導電性のpコンタクト領域、106はエッチングにより形成したトレンチ部、107はゲート酸化膜、108はゲート酸化膜107上に形成されたゲート電極、109はゲート電極108に印加した電圧で形成されるチャネル部、110はソース電極、111はドレイン電極を示している。
【0004】
動作について説明する。ソース電極110とドレイン電極111間に高電圧を印加した状態で、ゲート電極108に電圧を印加することにより、p型導電性ベース領域103のチャネル部109にn型反転層が形成され、n型導電性コンタクト領域104とドリフト領域102間に電流が導通し、ドリフト領域102を経てドレイン電極111に電流が流れる。ゲート電極108に電圧が印加されないオフ状態では、チャネル部109にn型反転層が形成されないので、この時、ソース電極110とドレイン電極111間に印加された高電圧は、ドリフト領域102並びにpベース領域103に延びた空乏層で遮断される。
【0005】
次に、製造方法について説明する。従来のトレンチゲート型のSiC半導体MOS電界効果パワートランジスタは、次のようにして作製する。SiC基板101上に、エピ成長により、ドリフト領域102のための低不純物n型層を成長させ、次に、p型導電性のベース領域103のためのp型層を成長させ、次に、nコンタクト領域104のため高不純物のn型層を順次成長させる。次に例えばマスキングを行ってエッチングを行い、トレンチ部6を形成する。次に、別のマスキングを行い、pコンタクト領域105部に、選択的に、表面にpコンタクト用にイオン注入を行って、その後、注入された不純物を電気的に活性化し、アクセプタとして活性化させるため、例えば、Ar雰囲気中で、1500°Cで1時間程度のアニールを行って、pコンタクト領域105を形成する。次に、水蒸気分圧を含んだ、酸素雰囲気でSiC表面の熱酸化を行い、ゲート酸化膜7を形成した後、ゲート電極8、ソース電極10、ドレイン電極11を形成する。
【0006】
なお、ここでは、pコンタクト領域105をイオン注入により形成する例について説明したが、その場合に限らず、逆に例えば、pコンタクト領域105に相当する層をエピ成長で形成し、領域105以外の領域に窒素のイオン注入を行い、その後に、注入された不純物を電気的に活性化し、ドナーとして活性化させるため、例えば、Ar雰囲気中で、1500°Cで1時間程度のアニールを行って、nコンタクト領域104を形成するようにしてもよい。
【0007】
図7は、例えば、電子情報通信学会論文誌C-II,Vol.J81-C-II,No.1の135ページに示されるような構造であり、従来型のウエハー表面にMOSチャネルを持つ構造のSiC半導体を用いたMOS電界効果パワートランジスタ半導体装置の概念図である。201はn型のSiC基板、202はエピ成長で形成した低不純物のn型の導電性を持つSiCのドリフト領域、203はイオン注入により形成したp型導電性ベース領域、204はイオン注入により形成したn型導電性のnコンタクト領域、207はゲート酸化膜、208はゲート電極、209はゲート電極に印加した電圧で形成されるチャネル部、210はソース電極、211はドレイン電極を示している。図6と同様にゲート電極208に電圧を印加することにより、p型導電性ベース領域203の表面のチャネル部209にn型反転層が形成され、n型導電性コンタクト領域204とドリフト領域202間に電流が導通し、ドリフト領域202を経てドレイン電極211に電流が流れる。
【0008】
【発明が解決しようとする課題】
SiCはSiに比較し絶縁破壊電界強度が10倍大きい。この特長を利用して、素子特性の向上を図る様に素子の構造を最適化すると、SiC中にはSiの絶縁破壊電界強度の十倍に近い電界が存在する。このため、上述したような図6の従来のトレンチゲート型のSiC半導体を用いたMOS電界効果パワートランジスタでは、絶縁破壊電界強度に近い電界が発生するSiC部分に接したゲート酸化膜中においても、両者の誘電率比によって定まる電界が発生し、その強度は酸化膜の絶縁破壊電界強度を越えることから、酸化膜中で絶縁破壊が生じる。またトレンチゲート構造では、特にトレンチ下部の角部分で電界集中が起こり、酸化膜中の電界強度が大きくなり、上記理由と相まって、ゲート酸化膜に絶縁破壊が生じ易い。このような結果、従来のトレンチゲート型のSiC半導体を用いたMOS電界効果パワートランジスタでは、SiCの材料特性から期待される素子耐圧が得られないという問題点があった。
【0009】
一方、図7に示した、従来の基板表面にMOSチャネルを持つ構造のMOSパワートランジスタでは、不純物を注入後、不純物を電気的に活性化させる工程で、例えば、Ar雰囲気中で、1500°Cで1時間のアニールを行う必要がある。この時、表面のSiが選択的に離脱したり、表面で部分的に不均一に成長やエッチングが生じることにより、SiCの表面に荒れが生じたり、階段状のステップ構造が形成される問題があった。基板表面にMOSチャネルを持つ構造のMOSパワートランジスタでは、この荒れもしくはステップの生じた面が、MOSチャネルの界面となる構造のため、MOS界面の劣化により、十分なチャネル特性が得られない問題があった。
【0010】
また、基板表面にMOSチャネルを持つ構造では、チャネル移動度が大きい112バー0面を、MOSチャネルの界面として用いるためには、入手が困難な112バー0面ウエハーを作製し、さらにそれに伴い従来基板面のプロセスとは異なった、エピ成長、注入、電極等の作製条件が必要であるという問題点があった。
【0011】
本発明は、かかる問題点を解決するために成されたもので、SiC中の電界分布の強い箇所がゲート酸化膜から離れた所になるような構造を備え、ゲート酸化膜が破壊されない特長をもち、SiCの材料特性に対応した素子耐圧を持つ半導体装置の製造方法を提供することを目的とする。
【0012】
【課題を解決するための手段】
この発明は、炭化珪素半導体からなる基板上に、低不純物のn型の導電性を有する炭化珪素半導体からなるn型層を形成する工程と、上記n型層上に、p型の導電性を有する炭化珪素半導体からなるp型ベース層を形成する工程と、上記p型ベース層上に、高不純物のn型の導電性を有する炭化珪素半導体からなるn型コンタクト層を形成する工程と、上記p型ベース層上の上記n型コンタクト層が設けられていない領域に炭化珪素半導体からなるp型コンタクト領域を形成する工程と、マスクを用いイオン注入を行うことにより、上記n型層内に、高電圧遮断時の上記n型層からのゲート酸化膜への電界の侵入をシールドさせるための溝下部電界シールド手段をp型領域によって形成する工程と、上記溝下部電界シールド手段を形成した後に活性化アニールを行なう活性化アニール工程と、上記活性化アニール工程後に、上記マスクを用いエッチングを行うことにより、上記n型コンタクト層及び上記p型ベース層を貫通して上記n型層内の上記溝下部電界シールド手段に達する深さを有する溝を形成する工程と、上記溝の底面及び側壁上にゲート酸化膜を形成する工程と、上記ゲート酸化膜を介在させて上記溝の側壁上にゲート電極を形成する工程と、上記n型コンタクト層及び上記p型コンタクト領域に接触させてソース電極を形成する工程と、上記基板の下面にドレイン電極を形成する工程とを備えた半導体装置の製造方法である。
【0026】
【発明の実施の形態】
実施の形態1.
図1は本発明の一実施の形態を示すもので、トレンチゲート型のSiC半導体MOS電界効果パワートランジスタ半導体装置の断面図である。1はn型のSiC基板、2は低不純物のn型の導電性を有するドリフト領域、3はドレイン電流制御用のMOSチャネルを形成するためのp型導電性のベース領域、4はn型導電性のnコンタクト領域、5はp型導電性のpコンタクト領域、6はエッチングにより形成したトレンチ部、7はトレンチ部6の底面および側壁に設けられたゲート酸化膜、8はゲート電極、9はゲート電極に印加した電圧で形成されるチャネル部、10はソース電極、11はドレイン電極、12はゲート酸化膜7部の電界強度を緩和するために、トレンチ部6の下部にエピ成長もしくはイオン注入により形成した、p型導電性のトレンチ下部電界シールド領域、13はp型のベース領域3下部にエピ成長もしくはイオン注入により形成した、p型導電性のベース領域下部電界シールド領域である。
【0027】
動作について説明する。ゲート電極8に電圧を印加することにより、チャネル部9にn型反転層が形成され、n型導電性のnコンタクト領域4とドリフト領域2間に電流が導通し、ドリフト領域2を経てドレイン電極11に電流が流れる。ゲート電極8に電圧が印加されないオフ状態では、チャネル部9にn型反転層が形成されない。この時ソース電極10とドレイン電極11間に印加された高電圧は、ドリフト領域2、トレンチ下部電界シールド領域12、ベース領域下部電界シールド領域13に延びた空乏層で遮断される。ここで、本実施の形態においては、トレンチ部6の下部にトレンチ下部電界シールド12を備えているので、それによって電界侵入が阻まれ、ゲート酸化膜7部分、特に、電界集中が起こるトレンチ部6下部の角部分の電界強度が緩和され、ゲート酸化膜7の絶縁破壊が生じない。また、pベース領域3下にもベース領域下部電界シールド領域13が備えられているため、pベース領域下からの電界の浸入がシールドされるため、ゲート酸化膜7の電界強度が緩和される。このような構造により、逆高電圧遮断時の電界強度の最強な箇所は、シールド領域13の下端になり、電界強度の強い部分とゲート酸化膜7に接する部分が接触せずに分離されることにより、酸化膜の絶縁破壊が生じない。
【0028】
次に、製造方法について説明する。本実施の形態に示したトレンチゲート型のSiC半導体MOS電界効果パワートランジスタは例えば、次のように作製できる。SiC基板1上に、CVDエピ成長により、ドリフト領域2のための低不純物n型層を成長させ、次に、p型導電性のベース領域3のためのp型層を成長させ、次に、nコンタクト領域4のため高不純物のn型層を順次成長させる。次に、マスキングを行い、pコンタクト領域5部に、選択的に、表面にpコンタクト用に高濃度のAlのイオン注入を行って、pコンタクト領域5を形成し、次に、例えば、同じマスクを用い、トレンチ部6の下部(底面)の深さより深い領域まで垂直方向に(すなわち、深さ方向に)Alのイオン注入を行い、ベース領域下部電界シールド領域13を形成する。また、次に例えば別のマスキングを行いトレンチ部6に選択的に、トレンチ部6下部(底面)の深さより深い領域にAl(アクセプタ)のイオン注入を行い、トレンチ下部電界シールド領域12を形成する。このとき、トレンチ下部電界シールド領域12の厚さが、ドリフト領域2からの酸化ゲート膜7への電界の侵入を妨げるに十分な所定の厚さになるようにする。次に例えば同じマスクを用い、エッチングを行いトレンチ部6を形成する。次に例えば、水蒸気分圧を含んだ、酸素雰囲気でSiC表面の熱酸化を行い、ゲート酸化膜7を形成した後、ゲート電極8、ソース電極10、ドレイン電極11を形成する。
【0029】
この例では、nコンタクト領域4のための高不純物のエピ成長したn型層にイオン注入により、pコンタクト領域5を形成する例を示したが、逆に、pコンタクト領域5のためのp層を成長により形成し、そこに窒素のイオン注入により、nコンタクト領域4を形成しても作製可能である。また、ここでは、pベース領域3のためのp型層を、エピ成長で形成する例を示したが、イオン注入によっても可能である。
【0030】
以上のように、本実施の形態が示す半導体装置では、トレンチ部6の下部にトレンチ下部電界シールド領域12があるため、ゲート酸化膜7の電界強度が緩和される。また、pベース領域3下にもベース領域下部電界シールド領域13が備えられているため、pベース領域下からの電界の浸入がシールドされるため、ゲート酸化膜7の電界強度が緩和される。このような構造により、逆高電圧遮断時の電界強度の最強な箇所は、pシールド領域の下端になり、電界強度の強い部分と、ゲート酸化膜7に接する部分が接触せずに分離されることにより、酸化膜の絶縁破壊が生じない。この結果、高電圧遮断時の、ゲート酸化膜7の電界強度を低減し、ゲート酸化膜7の絶縁破壊が防がれ、SiC材料の絶縁特性に対応した、素子耐圧を得ることができる。
【0031】
また、本実施の形態が示す製造方法に於いては、トレンチ部6を形成する前の工程で、イオン注入と活性化アニールを行い、その後に、トレンチ部6を形成し、その側壁をチャネルとして用いるので、チャネルが形成されるトレンチ部6の側壁に生じる注入の損傷、及び、アニールによる表面の荒れを低減することができ、高移動度で信頼性の高いチャネルを形成することができる効果があり、素子特性を向上できる。
【0032】
実施の形態2.
図2は本発明の別の一実施の形態を示すもので、トレンチゲート型のSiC半導体MOS電界効果パワートランジスタ半導体装置の断面図である。1はn型のSiC基板、2はドリフト領域、3はベース領域、4はnコンタクト領域、5はpコンタクト領域、6はトレンチ部、7はゲート酸化膜、8はゲート電極、9はチャネル部、10はソース電極、11はドレイン電極、12はトレンチ下部電界シールド領域、13はp型導電性のベース領域下部電界シールド領域、14はトレンチ下部電界シールド領域12とベース領域下部電界シールド領域13を電気的に結合する、電界シールド結合領域をしめしている。ゲート電極8への電圧の印加による、高電圧の遮断、導通の切り替えの原理及び電界シールド領域による、酸化膜における電界緩和の原理は実施の形態1と同様である。
【0033】
次に製造方法について説明する。本実施の形態に示したトレンチゲート型のSiC半導体MOS電界効果パワートランジスタは、例えば、次のように作製できる。SiC基板1上に、ドリフト領域2のための低不純物n型層を、pベース領域3のためのp型層を、nコンタクト領域4のため高不純物のn型層を順次成長する。次にマスキングを行いpコンタクト領域5部に選択的に、表面にコンタクト用に高濃度のAlのイオン注入を行い、次に例えば同じマスクを用い、トレンチ下部の深さより深い領域までAlのイオン注入を行い、ベース領域下部電界シールド領域13を形成する。また次に例えば別のマスキングを行いトレンチ部6と電界シールド結合領域14に選択的に、トレンチ下部の深さより深い領域にAlのイオン注入を行い、トレンチ下部電界シールド領域12と電界シールド結合領域14を形成する。次に例えば別のマスクを用い、エッチングを行いトレンチ部6を形成する。次ゲート酸化膜7を形成した後、ゲート電極8、ソース電極10、ドレイン電極11を形成する。
【0034】
この例では、ドリフト領域にイオン注入により、トレンチ下部電界シールド領域12、ベース領域下部電界シールド領域13並びに電界シールド結合領域14を形成する作製方法を示したが、逆に例えば上記3領域に相当する層をエピ成長で形成し、3領域以外の領域に窒素のイオン注入を行いn型導電領域を作製することも可能である。
【0035】
以上のように、本実施の形態における半導体装置において、トレンチ下部電界シールド領域12とベース領域下部電界シールド領域13によりゲート酸化膜7部の電界強度が緩和され酸化膜の絶縁破壊が軽減される原理は実施の形態1と同様である。さらに本実施の形態では、pベース領域とpシールド領域を電気的に結合する構造を備えているので、電位的に浮遊した領域が生じず、電荷の蓄積の片寄も生じないため、より安定なスイッチング動作と酸化膜の高い信頼性が得られる。
【0036】
また、本実施の形態における製造方法においても、上述の実施の形態1と同様に、トレンチ部6を形成する前の工程で、イオン注入と、活性化アニールを行うことができるので、チャネルが形成されるトレンチ部6の側壁に生じる注入の損傷、アニールによる表面の荒れを低減することができ、高移動度で信頼性の高いチャネルを形成することができる効果があり、素子特性を向上できる。
【0037】
実施の形態3.
図3は本発明の別の一実施の形態を示すもので、トレンチゲート型のSiC半導体MOS電界効果パワートランジスタ半導体装置の断面図である。1はn型のSiC基板、2はドリフト領域、3はベース領域、4はnコンタクト領域、5はpコンタクト領域、6はトレンチ部、7はゲート酸化膜、8はゲート電極、9はチャネル部、10はソース電極、11はドレイン電極、12はトレンチ下部電界シールド領域、13はベース領域下部電界シールド領域、14は電界シールド結合領域、15は導通時の抵抗を低減するためにpベース領域の下部に設けた、ドリフト領域2より導電性の高い(すなわち、キャリア濃度の高い)n型の電流拡散層である。ゲート電極8への電圧を印加による、高電圧の遮断、導通の切り替え、及び電界シールド領域の効果による、酸化膜における電界緩和の原理は実施の形態1及び2と同様である。
【0038】
次に製造方法について説明する。本実施の形態に示したトレンチゲート型のSiC半導体MOS電界効果パワートランジスタは例えば、次のように作製できる。SiC基板1上に、ドリフト領域2のための低不純物n型層を、次に電流拡散層15のための、ドリフト領域2より導電率の高いn型層を、次にpベース領域3のためのp型層を、次にnコンタクト領域4のための高不純物のn型層を順次成長する。実施の形態2と同様に選択的に、pコンタクト領域5、ベース領域下部電界シールド領域13、トレンチ下部電界シールド領域12並びに電界シールド結合領域14をAlのイオン注入により形成する。また次に例えば別のマスキングによるドナーのイオン注入によりnコンタクト領域4を形成する。次に例えば別のマスクを用い、エッチングを行いトレンチ部6を形成する。次にゲート酸化膜7を形成した後、ゲート電極8、ソース電極10、ドレイン電極11を形成する。この例では、エピ成長により電流拡散層を形成する作製例を示したが、ドナーのイオン注入により電流拡散層を形成する作製例も可能である。
【0039】
以上のように、本実施の形態に示した半導体装置は、上述の実施の形態1及び2と同様の効果が得られるとともに、さらに、pベース領域3の下部に、ドリフト領域2より導電性の高いn型の電流拡散層15そなえているので、導通時には、電流経路は、ゲート電圧印加により反転して形成されたチャネル9近傍からのみではなく、n型の電流拡散層15全体から、n型ドリフト領域2を経て流れるので、その抵抗は、電流拡散層15がないときに比べ低減される効果がある。
【0040】
また、本実施の形態における製造方法においても、上述の実施の形態1と同様に、トレンチ部6を形成する前の工程で、イオン注入と、活性化アニールを行うことができるので、チャネルが形成されるトレンチ部6の側壁に生じる注入の損傷、アニールによる表面の荒れを低減することができ、高移動度で信頼性の高いチャネルを形成することができる効果があり、素子特性を向上できる。
【0041】
実施の形態4.
図4は本発明の別の一実施の形態を示すもので、トレンチゲート型のSiC半導体MOS電界効果パワートランジスタ半導体装置の断面図である。1はn型のSiC基板、2はドリフト領域、3はベース領域、4はnコンタクト領域、5はpコンタクト領域、6はトレンチ部、7はゲート酸化膜、8はゲート電極、9はチャネル部、10はソース電極、11はドレイン電極、12Aはトレンチ部6の幅より広い幅を持ち、トレンチ部6のない領域まで横に延びた構造を有したトレンチ下部電界シールド領域、13はベース領域下部電界シールド領域、15は電流拡散層である。ゲート電極8への電圧を印加による、高電圧の遮断と導通の切り替え、及び、電界シールド領域12、13の効果による、ゲート酸化膜7における電界緩和、電流拡散層15による抵抗の低減の原理は実施の形態1から3と同様である。
【0042】
次に製造方法について説明する。本実施の形態に示したトレンチゲート型のSiC半導体MOS電界効果パワートランジスタは例えば、次のように作製できる。SiC基板1上に、ドリフト領域2のための低不純物n型層を、次に電流拡散層15のためのn型層を、次にpベース領域3のためのp型層を、次にnコンタクト領域4のための高不純物のn型層を順次成長する。実施の形態3と同様に選択的に、pコンタクト領域5、ベース領域下部電界シールド領域13、トレンチ下部電界シールド領域12並びに電界シールド結合領域14をAlのイオン注入により形成する。この時、トレンチ下部電界シールド領域12注入のためのマスクパターンを、トレンチ部6の幅より広くすることにより上部にトレンチ部6のない横の領域まで延びた注入領域を形成できる。また次にドナーのイオン注入によりnコンタクト領域4を形成する。次トレンチ部6を形成し、ゲート酸化膜7を形成した後、ゲート電極8、ソース電極10、ドレイン電極11を形成する。この例では、エピ成長により電流拡散層を形成する作製例を示したが、ドナーのイオン注入により電流拡散層を形成する作製例も可能である。
【0043】
以上のように、本実施の形態に示した半導体装置は、上述の実施の形態1〜3と同様の効果が得られるとともに、さらに、トレンチ下部シールド領域12の幅が、溝の幅より広く、上部のトレンチ部6のない領域まで延びた構造であり、特にトレンチ下部の角の部分と電界強度の大きい箇所とが、平面位置的にも分離されるので、特にトレンチ下部の角の酸化膜に印加される電界強度の緩和効果が大きく、酸化膜の絶縁破壊が生じない特長がある。
【0044】
また、本実施の形態における製造方法においても、上述の実施の形態1と同様に、トレンチ部6を形成する前の工程で、イオン注入と、活性化アニールを行うことができるので、チャネルが形成されるトレンチ部6の側壁に生じる注入の損傷、アニールによる表面の荒れを低減することができ、高移動度で信頼性の高いチャネルを形成することができる効果があり、素子特性を向上できる。
【0045】
なお、図5は同じく実施の形態4の他の構成を示すもので、トレンチ下部電界シールド領域12の幅が広く、ベース領域下部電界シールド領域13がない例をしめす。図4と同様に作製でき、また、同様な酸化膜の絶縁破壊を抑制する効果がある。
【0046】
実施の形態5.
つぎに、本発明の別の一実施の形態を示す。本実施の形態に示す半導体装置は、素子構造、作製方法は、上記実施の形態1から4と同様であり、電界シールド効果により、ゲート酸化膜7の絶縁破壊を抑制する効果をもっている。本実施の形態では、チャネル9は、エッチングにより形成したSiC結晶の1、1、2バー、0面のトレンチ部6の側壁に形成されている。チャネル移動度の結晶方位依存性より、基板表面に形成されたチャネルより大きな移動度が得られ、チャネル抵抗を低減できる。また同時に、電界シールドのためのp領域を備えているので、酸化膜の絶縁破壊が起こりにくい。
【0047】
【発明の効果】
この発明は、炭化珪素半導体からなる基板上に、低不純物のn型の導電性を有する炭化珪素半導体からなるn型層を形成する工程と、上記n型層上に、p型の導電性を有する炭化珪素半導体からなるp型ベース層を形成する工程と、上記p型ベース層上に、高不純物のn型の導電性を有する炭化珪素半導体からなるn型コンタクト層を形成する工程と、上記p型ベース層上の上記n型コンタクト層が設けられていない領域に炭化珪素半導体からなるp型コンタクト領域を形成する工程と、マスクを用いイオン注入を行うことにより、上記n型層内に、高電圧遮断時の上記n型層からのゲート酸化膜への電界の侵入をシールドさせるための溝下部電界シールド手段をp型領域によって形成する工程と、上記溝下部電界シールド手段を形成した後に活性化アニールを行なう活性化アニール工程と、上記活性化アニール工程後に、上記マスクを用いエッチングを行うことにより、上記n型コンタクト層及び上記p型ベース層を貫通して上記n型層内の上記溝下部電界シールド手段に達する深さを有する溝を形成する工程と、上記溝の底面及び側壁上にゲート酸化膜を形成する工程と、上記ゲート酸化膜を介在させて上記溝の側壁上にゲート電極を形成する工程と、上記n型コンタクト層及び上記p型コンタクト領域に接触させてソース電極を形成する工程と、上記基板の下面にドレイン電極を形成する工程とを備えた半導体装置の製造方法であり、溝の下部に電界シールドのためのp型領域を備えているので、ゲート酸化膜部、特に、電界集中の起こりやすい溝下部の角のゲート酸化膜の電界強度が緩和されるため、ゲート酸化膜の絶縁破壊が生じないので、SiC材料の絶縁特性に対応した、素子耐圧を得ることができる。
【図面の簡単な説明】
【図1】 本発明の実施の形態1によるトレンチゲート型のSiC半導体MOS電界効果パワートランジスタ半導体装置の断面図である。
【図2】 本発明の実施の形態2によるトレンチゲート型のSiC半導体MOS電界効果パワートランジスタ半導体装置の断面図である。
【図3】 本発明の実施の形態3によるトレンチゲート型のSiC半導体MOS電界効果パワートランジスタ半導体装置の断面図である。
【図4】 本発明の実施の形態4によるトレンチゲート型のSiC半導体MOS電界効果パワートランジスタ半導体装置の断面図である。
【図5】 本発明の実施の形態4による他のトレンチゲート型のSiC半導体MOS電界効果パワートランジスタ半導体装置の断面図である。
【図6】 従来のトレンチゲート型のSiC半導体MOS電界効果パワートランジスタ半導体装置の断面図である。
【図7】 従来のウエハー表面にMOSチャネルを持つ構造のSiC半導体MOS電界効果パワートランジスタ半導体装置の断面図である。
【符号の説明】
1 n型のSiC基板、2 ドリフト領域、3 ベース領域、4 nコンタクト領域、5 pコンタクト領域、6 トレンチ部、7 ゲート酸化膜、8 ゲート電極、9 チャネル部、10 ソース電極、11 ドレイン電極、12 トレンチ下部電界シールド領域、13 ベース領域下部電界シールド領域、14 電界シールド結合領域、15 電流拡散層。
[0001]
BACKGROUND OF THE INVENTION
  The present inventionHalfBACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a conductor device, and in particular, a semiconductor device used as a MOS field effect power transistor using a trench gate type SiC (silicon carbide) semiconductor.SetIt relates to a manufacturing method.
[0002]
[Prior art]
A conventional MOS field effect power transistor using a trench gate type SiC semiconductor is disclosed in, for example, the IEICE Transactions C-II Vol. J81-C-II, no. 1 on page 135 of FIG. 1, and the current is controlled by the gate portion of the MOS structure provided on the sidewall of the trench to perform high voltage switching.
[0003]
FIG. 6 is a conceptual diagram of a conventional MOS field effect power transistor semiconductor device using such a trench gate type SiC semiconductor. In the figure, 101 is an n-type SiC substrate, 102 is a low impurity n-type conductivity SiC drift region formed by epi-growth, 103 is a p-type conductive base region formed by epi-growth or ion implantation, 104 is an n-type conductive n-contact region formed by epi-growth or ion implantation, 105 is a p-type conductive p-contact region formed by epi-growth or ion implantation, 106 is a trench formed by etching, 107 is a gate An oxide film 108 is a gate electrode formed on the gate oxide film 107, 109 is a channel portion formed by a voltage applied to the gate electrode 108, 110 is a source electrode, and 111 is a drain electrode.
[0004]
The operation will be described. By applying a voltage to the gate electrode 108 with a high voltage applied between the source electrode 110 and the drain electrode 111, an n-type inversion layer is formed in the channel portion 109 of the p-type conductive base region 103, and the n-type inversion layer is formed. A current is conducted between the conductive contact region 104 and the drift region 102, and a current flows to the drain electrode 111 through the drift region 102. In the off state where no voltage is applied to the gate electrode 108, the n-type inversion layer is not formed in the channel portion 109. At this time, the high voltage applied between the source electrode 110 and the drain electrode 111 is applied to the drift region 102 and the p base. It is blocked by a depletion layer extending to the region 103.
[0005]
Next, a manufacturing method will be described. A conventional trench gate type SiC semiconductor MOS field effect power transistor is manufactured as follows. A low impurity n-type layer for the drift region 102 is grown on the SiC substrate 101 by epi growth, and then a p-type layer for the p-type conductive base region 103 is grown, and then n High-impurity n-type layers are sequentially grown for the contact region 104. Next, for example, masking is performed and etching is performed to form the trench portion 6. Next, another masking is performed, and ion implantation for p-contact is selectively performed on the surface of the p-contact region 105, and then the implanted impurity is electrically activated and activated as an acceptor. Therefore, for example, annealing is performed at 1500 ° C. for about 1 hour in an Ar atmosphere to form the p contact region 105. Next, thermal oxidation of the SiC surface is performed in an oxygen atmosphere containing a water vapor partial pressure to form the gate oxide film 7, and then the gate electrode 8, the source electrode 10, and the drain electrode 11 are formed.
[0006]
Here, an example in which the p contact region 105 is formed by ion implantation has been described. However, the present invention is not limited to this, and conversely, for example, a layer corresponding to the p contact region 105 is formed by epi growth, Nitrogen ions are implanted into the region, and then the implanted impurities are electrically activated and activated as donors. For example, annealing is performed at 1500 ° C. for about 1 hour in an Ar atmosphere. The n contact region 104 may be formed.
[0007]
FIG. 7 shows a structure as shown on page 135 of, for example, IEICE Transactions C-II, Vol. J81-C-II, No. 1, which has a MOS channel on a conventional wafer surface. It is a conceptual diagram of the MOS field effect power transistor semiconductor device using this SiC semiconductor. 201 is an n-type SiC substrate, 202 is a low-impurity n-type conductivity SiC drift region formed by epi growth, 203 is a p-type conductive base region formed by ion implantation, and 204 is formed by ion implantation. N-type conductive n contact region, 207 is a gate oxide film, 208 is a gate electrode, 209 is a channel portion formed by a voltage applied to the gate electrode, 210 is a source electrode, and 211 is a drain electrode. As in FIG. 6, by applying a voltage to the gate electrode 208, an n-type inversion layer is formed in the channel portion 209 on the surface of the p-type conductive base region 203, and between the n-type conductive contact region 204 and the drift region 202. , And the current flows through the drift region 202 to the drain electrode 211.
[0008]
[Problems to be solved by the invention]
SiC has a dielectric breakdown electric field strength 10 times larger than Si. When the structure of the element is optimized so as to improve the element characteristics by utilizing this feature, an electric field close to ten times the dielectric breakdown electric field strength of Si exists in SiC. For this reason, in the MOS field effect power transistor using the conventional trench gate type SiC semiconductor of FIG. 6 as described above, even in the gate oxide film in contact with the SiC portion where the electric field close to the breakdown electric field strength is generated, An electric field determined by the dielectric constant ratio of the two is generated, and its strength exceeds the dielectric breakdown electric field strength of the oxide film, so that dielectric breakdown occurs in the oxide film. Further, in the trench gate structure, electric field concentration occurs particularly at the corner portion of the lower portion of the trench, and the electric field strength in the oxide film increases, and coupled with the above reason, dielectric breakdown is likely to occur in the gate oxide film. As a result, the conventional MOS field effect power transistor using the trench gate type SiC semiconductor has a problem that the element breakdown voltage expected from the material characteristics of SiC cannot be obtained.
[0009]
On the other hand, in the conventional MOS power transistor having a MOS channel structure on the surface of the substrate shown in FIG. 7, the impurity is electrically activated after the impurity is implanted. It is necessary to perform annealing for 1 hour. At this time, Si on the surface is selectively detached, or the surface is partially unevenly grown or etched, resulting in a rough surface on the SiC surface or a stepped step structure being formed. there were. In a MOS power transistor having a MOS channel structure on the surface of the substrate, the roughened or stepped surface becomes the MOS channel interface, so that sufficient channel characteristics cannot be obtained due to deterioration of the MOS interface. there were.
[0010]
In addition, in a structure having a MOS channel on the substrate surface, a 112 bar 0 plane wafer having a high channel mobility is used to manufacture a 112 bar 0 plane wafer which is difficult to obtain in order to use it as an interface of the MOS channel. Unlike the process of the substrate surface, there is a problem that manufacturing conditions such as epi-growth, implantation, and electrodes are necessary.
[0011]
  The present invention has been made to solve such problems, and has a structure in which a portion with a strong electric field distribution in SiC is located away from the gate oxide film, and the gate oxide film is not destroyed. In addition, a semiconductor device having an element breakdown voltage corresponding to the material characteristics of SiC.SetAn object is to provide a manufacturing method.
[0012]
[Means for Solving the Problems]
  This inventionForming an n-type layer made of a low-impurity n-type conductive silicon carbide semiconductor on a substrate made of a silicon carbide semiconductor; and a p-type conductive silicon carbide semiconductor on the n-type layer A step of forming a p-type base layer comprising: a step of forming an n-type contact layer made of a silicon carbide semiconductor having high impurity n-type conductivity on the p-type base layer; and the p-type base layer A step of forming a p-type contact region made of a silicon carbide semiconductor in a region where the n-type contact layer is not provided above, and ion implantation using a mask are performed in the n-type layer when a high voltage is cut off. Forming a groove lower field shield means for shielding the invasion of an electric field from the n-type layer into the gate oxide film by the p-type region, and forming an activation anion after forming the groove lower field shield means. An activation annealing step for performing etching, and after the activation annealing step, etching is performed using the mask, thereby penetrating the n-type contact layer and the p-type base layer and lowering the groove in the n-type layer. A step of forming a groove having a depth reaching the electric field shielding means, a step of forming a gate oxide film on the bottom and side walls of the groove, and a gate electrode on the side wall of the groove with the gate oxide film interposed therebetween. A method of manufacturing a semiconductor device, comprising: a step of forming; a step of forming a source electrode in contact with the n-type contact layer and the p-type contact region; and a step of forming a drain electrode on the lower surface of the substrate. .
[0026]
DETAILED DESCRIPTION OF THE INVENTION
Embodiment 1 FIG.
FIG. 1 shows an embodiment of the present invention, and is a cross-sectional view of a trench gate type SiC semiconductor MOS field effect power transistor semiconductor device. Reference numeral 1 denotes an n-type SiC substrate, 2 denotes a drift region having low impurity n-type conductivity, 3 denotes a p-type conductive base region for forming a drain current control MOS channel, and 4 denotes n-type conductivity N contact region 5, p contact region 5 of p-type conductivity, 6 a trench portion formed by etching, 7 a gate oxide film provided on the bottom and side walls of trench portion 6, 8 a gate electrode, 9 A channel portion formed by a voltage applied to the gate electrode, 10 is a source electrode, 11 is a drain electrode, 12 is an epitaxial growth or ion implantation under the trench portion 6 in order to relax the electric field strength of the gate oxide film 7 portion. A p-type conductive trench lower field shield region formed by the above-described process, and a p-type conductive base region 13 formed by epi-growth or ion implantation under the p-type base region 3. Which is the lower electric field shield region.
[0027]
The operation will be described. By applying a voltage to the gate electrode 8, an n-type inversion layer is formed in the channel portion 9, a current is conducted between the n-type conductive n-contact region 4 and the drift region 2, and the drain electrode passes through the drift region 2. A current flows through 11. In the off state where no voltage is applied to the gate electrode 8, the n-type inversion layer is not formed in the channel portion 9. At this time, the high voltage applied between the source electrode 10 and the drain electrode 11 is blocked by the depletion layer extending to the drift region 2, the trench lower field shield region 12, and the base region lower field shield region 13. Here, in the present embodiment, since the trench lower field shield 12 is provided below the trench portion 6, the electric field penetration is prevented thereby, and the gate oxide film 7 portion, particularly, the trench portion 6 where electric field concentration occurs. The electric field strength at the lower corner is relaxed, and the dielectric breakdown of the gate oxide film 7 does not occur. Further, since the base region lower electric field shield region 13 is also provided under the p base region 3, the electric field intrusion from below the p base region is shielded, so that the electric field strength of the gate oxide film 7 is relaxed. With such a structure, the strongest portion of the electric field strength at the time of reverse high voltage interruption is the lower end of the shield region 13, and the portion where the electric field strength is strong and the portion contacting the gate oxide film 7 are separated without contact. Therefore, the dielectric breakdown of the oxide film does not occur.
[0028]
Next, a manufacturing method will be described. The trench gate type SiC semiconductor MOS field effect power transistor shown in the present embodiment can be manufactured as follows, for example. On the SiC substrate 1, a low impurity n-type layer for the drift region 2 is grown by CVD epi growth, then a p-type layer for the p-type conductive base region 3 is grown, and then High impurity n-type layers are sequentially grown for the n contact region 4. Next, masking is performed, and a p-contact region 5 is selectively implanted into the surface of the p-contact region 5 to form a p-contact region 5, and then, for example, the same mask is used. The base region lower electric field shield region 13 is formed by performing Al ion implantation in the vertical direction (that is, in the depth direction) to a region deeper than the depth of the lower portion (bottom surface) of the trench portion 6. Next, for example, another masking is performed, and Al (acceptor) is ion-implanted in a region deeper than the depth (bottom surface) of the trench portion 6 to form the trench lower electric field shield region 12. . At this time, the thickness of the trench lower electric field shield region 12 is set to a predetermined thickness sufficient to prevent the electric field from entering the oxide gate film 7 from the drift region 2. Next, for example, using the same mask, etching is performed to form the trench portion 6. Next, for example, thermal oxidation of the SiC surface is performed in an oxygen atmosphere including a water vapor partial pressure to form the gate oxide film 7, and then the gate electrode 8, the source electrode 10, and the drain electrode 11 are formed.
[0029]
In this example, an example in which the p contact region 5 is formed by ion implantation in an n-type layer that is epitaxially grown with a high impurity for the n contact region 4 is shown, but conversely, a p layer for the p contact region 5 is formed. Can also be formed by forming the n contact region 4 by ion implantation of nitrogen therein. Although an example in which the p-type layer for the p base region 3 is formed by epi-growth is shown here, ion implantation is also possible.
[0030]
As described above, in the semiconductor device shown in the present embodiment, since the trench lower electric field shield region 12 is provided below the trench portion 6, the electric field strength of the gate oxide film 7 is relaxed. Further, since the base region lower electric field shield region 13 is also provided under the p base region 3, the electric field intrusion from below the p base region is shielded, so that the electric field strength of the gate oxide film 7 is relaxed. With such a structure, the strongest portion of the electric field strength at the time of reverse high voltage interruption is the lower end of the p shield region, and the portion having the strong electric field strength and the portion in contact with the gate oxide film 7 are separated without contact. As a result, dielectric breakdown of the oxide film does not occur. As a result, the electric field strength of the gate oxide film 7 at the time of high voltage interruption is reduced, the dielectric breakdown of the gate oxide film 7 is prevented, and the device breakdown voltage corresponding to the insulation characteristics of the SiC material can be obtained.
[0031]
Further, in the manufacturing method shown in the present embodiment, ion implantation and activation annealing are performed in a step before forming the trench portion 6, and then the trench portion 6 is formed and its side wall is used as a channel. Therefore, it is possible to reduce the damage of implantation caused on the side wall of the trench portion 6 where the channel is formed and the roughness of the surface due to annealing, and the effect of being able to form a channel with high mobility and high reliability. Yes, device characteristics can be improved.
[0032]
Embodiment 2. FIG.
FIG. 2 shows another embodiment of the present invention and is a sectional view of a trench gate type SiC semiconductor MOS field effect power transistor semiconductor device. 1 is an n-type SiC substrate, 2 is a drift region, 3 is a base region, 4 is an n contact region, 5 is a p contact region, 6 is a trench portion, 7 is a gate oxide film, 8 is a gate electrode, and 9 is a channel portion. 10 is a source electrode, 11 is a drain electrode, 12 is a trench lower electric field shield region, 13 is a p-type conductive base region lower electric field shield region, and 14 is a trench lower electric field shield region 12 and a base region lower electric field shield region 13. An electric field shield coupling region for electrical coupling is shown. The principle of high voltage cutoff and conduction switching by applying voltage to the gate electrode 8 and the principle of electric field relaxation in the oxide film by the electric field shield region are the same as in the first embodiment.
[0033]
Next, a manufacturing method will be described. The trench gate type SiC semiconductor MOS field effect power transistor shown in the present embodiment can be manufactured as follows, for example. On the SiC substrate 1, a low impurity n-type layer for the drift region 2, a p-type layer for the p base region 3, and a high impurity n-type layer for the n contact region 4 are sequentially grown. Next, masking is performed, and ion implantation of high-concentration Al for contact is selectively performed on the surface of the p-contact region 5 part, and then Al ion implantation is performed to a region deeper than the depth below the trench using, for example, the same mask. The base region lower electric field shield region 13 is formed. Next, for example, another masking is performed to selectively implant the trench portion 6 and the electric field shield coupling region 14 into a region deeper than the depth below the trench, thereby forming the lower trench electric field shield region 12 and the electric field shield coupling region 14. Form. Next, for example, using another mask, etching is performed to form the trench portion 6. After forming the next gate oxide film 7, a gate electrode 8, a source electrode 10, and a drain electrode 11 are formed.
[0034]
In this example, a manufacturing method is shown in which the trench lower field shield region 12, the base region lower field shield region 13, and the field shield coupling region 14 are formed by ion implantation in the drift region. It is also possible to form an n-type conductive region by forming the layer by epi-growth and implanting nitrogen ions into regions other than the three regions.
[0035]
As described above, in the semiconductor device according to the present embodiment, the electric field strength of the gate oxide film 7 is relaxed by the trench lower electric field shield region 12 and the base region lower electric field shield region 13, and the dielectric breakdown of the oxide film is reduced. Is the same as in the first embodiment. Further, in this embodiment, since the p base region and the p shield region are electrically coupled, there is no potential floating region, and no charge accumulation occurs. High reliability of switching operation and oxide film can be obtained.
[0036]
Also in the manufacturing method in the present embodiment, as in the first embodiment, since the ion implantation and the activation annealing can be performed in the process before the trench portion 6 is formed, a channel is formed. Implant damage generated on the side wall of the trench 6 to be formed and surface roughness due to annealing can be reduced, and a channel having high mobility and high reliability can be formed, and the device characteristics can be improved.
[0037]
Embodiment 3 FIG.
FIG. 3 shows another embodiment of the present invention, and is a cross-sectional view of a trench gate type SiC semiconductor MOS field effect power transistor semiconductor device. 1 is an n-type SiC substrate, 2 is a drift region, 3 is a base region, 4 is an n contact region, 5 is a p contact region, 6 is a trench portion, 7 is a gate oxide film, 8 is a gate electrode, and 9 is a channel portion. 10 is a source electrode, 11 is a drain electrode, 12 is a trench lower electric field shield region, 13 is a base region lower electric field shield region, 14 is an electric field shield coupling region, and 15 is a p base region for reducing resistance during conduction. This is an n-type current diffusion layer provided in the lower part and having higher conductivity (ie, higher carrier concentration) than the drift region 2. The principle of electric field relaxation in the oxide film by applying a voltage to the gate electrode 8 to cut off high voltage, switching conduction, and effect of the electric field shield region is the same as in the first and second embodiments.
[0038]
Next, a manufacturing method will be described. The trench gate type SiC semiconductor MOS field effect power transistor shown in the present embodiment can be manufactured as follows, for example. On SiC substrate 1, a low impurity n-type layer for drift region 2, then an n-type layer having higher conductivity than drift region 2 for current diffusion layer 15, and then for p base region 3 Next, a high impurity n-type layer for the n-contact region 4 is successively grown. Similarly to the second embodiment, the p contact region 5, the base region lower electric field shield region 13, the trench lower electric field shield region 12, and the electric field shield coupling region 14 are formed by ion implantation of Al. Next, the n contact region 4 is formed by, for example, donor ion implantation using another masking. Next, for example, using another mask, etching is performed to form the trench portion 6. Next, after forming the gate oxide film 7, the gate electrode 8, the source electrode 10, and the drain electrode 11 are formed. In this example, a manufacturing example in which a current diffusion layer is formed by epi-growth is shown, but a manufacturing example in which a current diffusion layer is formed by ion implantation of a donor is also possible.
[0039]
As described above, the semiconductor device described in the present embodiment can obtain the same effects as those of the first and second embodiments described above, and is more conductive than the drift region 2 below the p base region 3. Since the high n-type current diffusion layer 15 is provided, when conducting, the current path is not only from the vicinity of the channel 9 formed by reversal by application of the gate voltage, but from the entire n-type current diffusion layer 15 to the n-type. Since the current flows through the drift region 2, the resistance is effectively reduced as compared with the case where the current diffusion layer 15 is not provided.
[0040]
Also in the manufacturing method in the present embodiment, as in the first embodiment, since the ion implantation and the activation annealing can be performed in the process before the trench portion 6 is formed, a channel is formed. Implant damage generated on the side wall of the trench 6 to be formed and surface roughness due to annealing can be reduced, and a channel having high mobility and high reliability can be formed, and the device characteristics can be improved.
[0041]
Embodiment 4 FIG.
FIG. 4 shows another embodiment of the present invention and is a sectional view of a trench gate type SiC semiconductor MOS field effect power transistor semiconductor device. 1 is an n-type SiC substrate, 2 is a drift region, 3 is a base region, 4 is an n contact region, 5 is a p contact region, 6 is a trench portion, 7 is a gate oxide film, 8 is a gate electrode, and 9 is a channel portion. 10 is a source electrode, 11 is a drain electrode, 12A is wider than the width of the trench portion 6, and has a structure extending laterally to a region without the trench portion 6, and 13 is a lower portion of the base region. The electric field shield region 15 is a current diffusion layer. The principles of high voltage cutoff and conduction switching by applying a voltage to the gate electrode 8, and electric field relaxation in the gate oxide film 7 and resistance reduction by the current diffusion layer 15 due to the effects of the electric field shield regions 12 and 13 are as follows. This is the same as in the first to third embodiments.
[0042]
Next, a manufacturing method will be described. The trench gate type SiC semiconductor MOS field effect power transistor shown in the present embodiment can be manufactured as follows, for example. On SiC substrate 1, a low impurity n-type layer for drift region 2, then an n-type layer for current diffusion layer 15, then a p-type layer for p base region 3, and then n A high impurity n-type layer for the contact region 4 is sequentially grown. Similarly to the third embodiment, the p contact region 5, the base region lower electric field shield region 13, the trench lower electric field shield region 12, and the electric field shield coupling region 14 are formed by ion implantation of Al. At this time, by making the mask pattern for implanting the trench lower electric field shield region 12 wider than the width of the trench portion 6, it is possible to form an implantation region extending to a lateral region without the trench portion 6 on the upper portion. Next, an n-contact region 4 is formed by donor ion implantation. After the next trench portion 6 is formed and the gate oxide film 7 is formed, the gate electrode 8, the source electrode 10, and the drain electrode 11 are formed. In this example, a manufacturing example in which a current diffusion layer is formed by epi-growth is shown, but a manufacturing example in which a current diffusion layer is formed by ion implantation of a donor is also possible.
[0043]
As described above, the semiconductor device shown in the present embodiment can obtain the same effects as those of the first to third embodiments, and the width of the trench lower shield region 12 is wider than the width of the groove. The structure extends to a region without the upper trench portion 6, and in particular, the corner portion at the lower portion of the trench and the portion having a high electric field strength are separated from each other even in a planar position. The effect of relaxing the applied electric field strength is great, and there is a feature that dielectric breakdown of the oxide film does not occur.
[0044]
Also in the manufacturing method in the present embodiment, as in the first embodiment, since the ion implantation and the activation annealing can be performed in the process before the trench portion 6 is formed, a channel is formed. Implant damage generated on the side wall of the trench 6 to be formed and surface roughness due to annealing can be reduced, and a channel having high mobility and high reliability can be formed, and the device characteristics can be improved.
[0045]
FIG. 5 shows another configuration of the fourth embodiment, and shows an example in which the trench lower electric field shield region 12 is wide and the base region lower electric field shield region 13 is not provided. It can be produced in the same manner as in FIG. 4 and has the same effect of suppressing dielectric breakdown of the oxide film.
[0046]
Embodiment 5 FIG.
Next, another embodiment of the present invention will be described. The semiconductor device described in this embodiment has the same element structure and manufacturing method as those in Embodiments 1 to 4, and has an effect of suppressing the dielectric breakdown of the gate oxide film 7 by the electric field shielding effect. In the present embodiment, the channel 9 is formed on the side wall of the trench portion 6 on the 1st, 2nd, and 0th planes of SiC crystal formed by etching. Due to the crystal orientation dependence of the channel mobility, a larger mobility than the channel formed on the substrate surface can be obtained, and the channel resistance can be reduced. At the same time, since the p region for electric field shielding is provided, the dielectric breakdown of the oxide film hardly occurs.
[0047]
【The invention's effect】
  This inventionForming an n-type layer made of a low-impurity n-type conductive silicon carbide semiconductor on a substrate made of a silicon carbide semiconductor; and a p-type conductive silicon carbide semiconductor on the n-type layer A step of forming a p-type base layer comprising: a step of forming an n-type contact layer made of a silicon carbide semiconductor having high impurity n-type conductivity on the p-type base layer; and the p-type base layer A step of forming a p-type contact region made of a silicon carbide semiconductor in a region where the n-type contact layer is not provided above, and ion implantation using a mask are performed in the n-type layer when a high voltage is cut off. Forming a groove lower field shield means for shielding the invasion of an electric field from the n-type layer into the gate oxide film by the p-type region, and forming an activation anion after forming the groove lower field shield means. An activation annealing step for performing etching, and after the activation annealing step, etching is performed using the mask, thereby penetrating the n-type contact layer and the p-type base layer and lowering the groove in the n-type layer. A step of forming a groove having a depth reaching the electric field shielding means, a step of forming a gate oxide film on the bottom and side walls of the groove, and a gate electrode on the side wall of the groove with the gate oxide film interposed therebetween. A method of manufacturing a semiconductor device, comprising: a step of forming a source electrode in contact with the n-type contact layer and the p-type contact region; and a step of forming a drain electrode on the lower surface of the substrateSince the p-type region for electric field shielding is provided at the lower part of the groove, the electric field strength of the gate oxide film part, particularly, the gate oxide film at the corner of the lower part of the groove where electric field concentration is likely to occur is relaxed. Since breakdown of the gate oxide film does not occur, an element withstand voltage corresponding to the insulation characteristics of the SiC material can be obtained.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view of a trench gate type SiC semiconductor MOS field effect power transistor semiconductor device according to a first embodiment of the present invention.
FIG. 2 is a cross-sectional view of a trench gate type SiC semiconductor MOS field effect power transistor semiconductor device according to a second embodiment of the present invention.
FIG. 3 is a cross-sectional view of a trench gate type SiC semiconductor MOS field effect power transistor semiconductor device according to a third embodiment of the present invention.
FIG. 4 is a sectional view of a trench gate type SiC semiconductor MOS field effect power transistor semiconductor device according to a fourth embodiment of the present invention.
FIG. 5 is a cross-sectional view of another trench gate type SiC semiconductor MOS field effect power transistor semiconductor device according to Embodiment 4 of the present invention;
FIG. 6 is a cross-sectional view of a conventional trench gate type SiC semiconductor MOS field effect power transistor semiconductor device.
FIG. 7 is a cross-sectional view of a conventional SiC semiconductor MOS field effect power transistor semiconductor device having a MOS channel structure on the wafer surface.
[Explanation of symbols]
1 n-type SiC substrate, 2 drift region, 3 base region, 4 n contact region, 5 p contact region, 6 trench portion, 7 gate oxide film, 8 gate electrode, 9 channel portion, 10 source electrode, 11 drain electrode, 12 trench lower electric field shield region, 13 base region lower electric field shield region, 14 electric field shield coupling region, 15 current diffusion layer.

Claims (1)

  1. 炭化珪素半導体からなる基板上に、低不純物のn型の導電性を有する炭化珪素半導体からなるn型層を形成する工程と、
    上記n型層上に、p型の導電性を有する炭化珪素半導体からなるp型ベース層を形成する工程と、
    上記p型ベース層上に、高不純物のn型の導電性を有する炭化珪素半導体からなるn型コンタクト層を形成する工程と、
    上記p型ベース層上の上記n型コンタクト層が設けられていない領域に炭化珪素半導体からなるp型コンタクト領域を形成する工程と、
    マスクを用いイオン注入を行うことにより、上記n型層内に、高電圧遮断時の上記n型層からのゲート酸化膜への電界の侵入をシールドさせるための溝下部電界シールド手段をp型領域によって形成する工程と、
    上記溝下部電界シールド手段を形成した後に活性化アニールを行なう活性化アニール工程と、
    上記活性化アニール工程後に、上記マスクを用いエッチングを行うことにより、上記n型コンタクト層及び上記p型ベース層を貫通して上記n型層内の上記溝下部電界シールド手段に達する深さを有する溝を形成する工程と、
    上記溝の底面及び側壁上にゲート酸化膜を形成する工程と、
    上記ゲート酸化膜を介在させて上記溝の側壁上にゲート電極を形成する工程と、
    上記n型コンタクト層及び上記p型コンタクト領域に接触させてソース電極を形成する工程と、
    上記基板の下面にドレイン電極を形成する工程と、
    を備えたことを特徴とする半導体装置の製造方法。
    Forming an n-type layer made of a low-impurity n-type conductive silicon carbide semiconductor on a substrate made of a silicon carbide semiconductor;
    Forming a p-type base layer made of a silicon carbide semiconductor having p-type conductivity on the n-type layer;
    Forming an n-type contact layer made of a high-impurity n-type conductive silicon carbide semiconductor on the p-type base layer;
    Forming a p-type contact region made of a silicon carbide semiconductor in a region where the n-type contact layer is not provided on the p-type base layer;
    By ion implantation using a mask on the n-type layer, p-type region a groove bottom field shielding means for shielding the electric field from entering the gate oxide film from the n-type layer at a high voltage blocking A step of forming by:
    An activation annealing step of performing activation annealing after forming the groove lower field shielding means;
    Etching using the mask after the activation annealing step has a depth that penetrates the n-type contact layer and the p-type base layer and reaches the groove lower field shield means in the n-type layer. Forming a groove;
    Forming a gate oxide film on the bottom and side walls of the trench;
    Forming a gate electrode on the sidewall of the groove with the gate oxide film interposed therebetween;
    Forming a source electrode in contact with the n-type contact layer and the p-type contact region;
    Forming a drain electrode on the lower surface of the substrate;
    A method for manufacturing a semiconductor device, comprising:
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