JP2001267570A - Semiconductor device and method of manufacturing semiconductor device - Google Patents
Semiconductor device and method of manufacturing semiconductor deviceInfo
- Publication number
- JP2001267570A JP2001267570A JP2000072298A JP2000072298A JP2001267570A JP 2001267570 A JP2001267570 A JP 2001267570A JP 2000072298 A JP2000072298 A JP 2000072298A JP 2000072298 A JP2000072298 A JP 2000072298A JP 2001267570 A JP2001267570 A JP 2001267570A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 74
- 238000004519 manufacturing process Methods 0.000 title claims description 26
- 230000005684 electric field Effects 0.000 claims abstract description 158
- 239000000758 substrate Substances 0.000 claims abstract description 31
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 claims description 56
- 229910010271 silicon carbide Inorganic materials 0.000 claims description 56
- 239000012535 impurity Substances 0.000 claims description 28
- 230000008878 coupling Effects 0.000 claims description 21
- 238000010168 coupling process Methods 0.000 claims description 21
- 238000005859 coupling reaction Methods 0.000 claims description 21
- 238000009792 diffusion process Methods 0.000 claims description 20
- 238000000034 method Methods 0.000 claims description 10
- 239000013078 crystal Substances 0.000 claims description 6
- 230000000149 penetrating effect Effects 0.000 claims description 4
- 230000015556 catabolic process Effects 0.000 abstract description 21
- 238000005530 etching Methods 0.000 abstract description 9
- 238000009826 distribution Methods 0.000 abstract description 2
- 230000035515 penetration Effects 0.000 abstract description 2
- 238000005468 ion implantation Methods 0.000 description 26
- 230000005669 field effect Effects 0.000 description 22
- 238000000137 annealing Methods 0.000 description 14
- 230000000694 effects Effects 0.000 description 11
- 238000002513 implantation Methods 0.000 description 8
- 230000000873 masking effect Effects 0.000 description 7
- 230000004913 activation Effects 0.000 description 6
- 150000002500 ions Chemical class 0.000 description 6
- 239000000463 material Substances 0.000 description 4
- IJGRMHOSHXDMSA-UHFFFAOYSA-N nitrogen Substances N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 3
- 229910052757 nitrogen Inorganic materials 0.000 description 3
- -1 nitrogen ions Chemical class 0.000 description 3
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000008595 infiltration Effects 0.000 description 2
- 238000001764 infiltration Methods 0.000 description 2
- 230000009545 invasion Effects 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 239000001301 oxygen Substances 0.000 description 2
- 229910052760 oxygen Inorganic materials 0.000 description 2
- 238000003892 spreading Methods 0.000 description 2
- 230000003746 surface roughness Effects 0.000 description 2
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical compound O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 2
- 238000009825 accumulation Methods 0.000 description 1
- 230000003213 activating effect Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 230000002040 relaxant effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
- H01L29/0623—Buried supplementary region, e.g. buried guard ring
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1095—Body region, i.e. base region, of DMOS transistors or IGBTs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66053—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide
- H01L29/66068—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
- H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
- H01L29/0852—Source or drain regions of field-effect devices of field-effect transistors with insulated gate of DMOS transistors
- H01L29/0873—Drain regions
- H01L29/0878—Impurity concentration or distribution
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
- H01L29/1608—Silicon carbide
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Manufacturing & Machinery (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は半導体装置及び半導
体装置の製造方法に関し、特に、トレンチゲート型のＳ
ｉＣ（炭化珪素）半導体を用いたＭＯＳ電界効果パワー
トランジスタとして用いる半導体装置及びその製造方法
に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing a semiconductor device, and more particularly to a trench gate type S device.
The present invention relates to a semiconductor device used as a MOS field-effect power transistor using an iC (silicon carbide) semiconductor and a method for manufacturing the same.
【０００２】[0002]
【従来の技術】トレンチゲート型のＳｉＣ半導体を用い
た従来のＭＯＳ電界効果パワートランジスタは、例え
ば、電子情報通信学会論文誌Ｃ−ＩＩ Vol．Ｊ８１−
Ｃ−ＩＩ、Ｎｏ．１の１３５ページの図２に示されるよ
うな構造であり、トレンチ側壁に設けたＭＯＳ構造のゲ
ート部分で電流を制御し、高電圧のスイッチングを行
う。2. Description of the Related Art A conventional MOS field effect power transistor using a trench gate type SiC semiconductor is disclosed in, for example, IEICE Transactions C-II Vol. J81-
C-II, no. 1 is a structure as shown in FIG. 2 on page 135, in which the current is controlled by the gate portion of the MOS structure provided on the side wall of the trench, and high-voltage switching is performed.
【０００３】図６は、従来のこのようなトレンチゲート
型のＳｉＣ半導体を用いたＭＯＳ電界効果パワートラン
ジスタ半導体装置の概念図である。図において、１０１
はｎ型のＳｉＣ基板、１０２はエピ成長で形成した低不
純物のｎ型の導電性を持つＳｉＣのドリフト領域、１０
３はエピ成長もしくはイオン注入により形成したｐ型導
電性ベース領域、１０４はエピ成長もしくはイオン注入
により形成したｎ型導電性のｎコンタクト領域、１０５
はエピ成長もしくはイオン注入により形成したｐ型導電
性のｐコンタクト領域、１０６はエッチングにより形成
したトレンチ部、１０７はゲート酸化膜、１０８はゲー
ト酸化膜１０７上に形成されたゲート電極、１０９はゲ
ート電極１０８に印加した電圧で形成されるチャネル
部、１１０はソース電極、１１１はドレイン電極を示し
ている。FIG. 6 is a conceptual diagram of a conventional MOS field effect power transistor semiconductor device using such a trench gate type SiC semiconductor. In the figure, 101
Denotes an n-type SiC substrate, 102 denotes a low impurity n-type conductive SiC drift region formed by epitaxial growth, 10
3 is a p-type conductive base region formed by epi growth or ion implantation, 104 is an n-type conductive n contact region formed by epi growth or ion implantation, 105
Is a p-type conductive p-contact region formed by epitaxial growth or ion implantation, 106 is a trench formed by etching, 107 is a gate oxide film, 108 is a gate electrode formed on the gate oxide film 107, and 109 is a gate. A channel portion formed by a voltage applied to the electrode 108, 110 is a source electrode, and 111 is a drain electrode.
【０００４】動作について説明する。ソース電極１１０
とドレイン電極１１１間に高電圧を印加した状態で、ゲ
ート電極１０８に電圧を印加することにより、ｐ型導電
性ベース領域１０３のチャネル部１０９にｎ型反転層が
形成され、ｎ型導電性コンタクト領域１０４とドリフト
領域１０２間に電流が導通し、ドリフト領域１０２を経
てドレイン電極１１１に電流が流れる。ゲート電極１０
８に電圧が印加されないオフ状態では、チャネル部１０
９にｎ型反転層が形成されないので、この時、ソース電
極１１０とドレイン電極１１１間に印加された高電圧
は、ドリフト領域１０２並びにｐベース領域１０３に延
びた空乏層で遮断される。The operation will be described. Source electrode 110
By applying a voltage to the gate electrode 108 with a high voltage applied between the gate electrode 108 and the drain electrode 111, an n-type inversion layer is formed in the channel portion 109 of the p-type conductive base region 103, and the n-type conductive contact A current flows between the region 104 and the drift region 102, and a current flows to the drain electrode 111 via the drift region 102. Gate electrode 10
In the off state where no voltage is applied to the channel section 8,
Since an n-type inversion layer is not formed in 9, a high voltage applied between the source electrode 110 and the drain electrode 111 at this time is cut off by the depletion layer extending to the drift region 102 and the p base region 103.
【０００５】次に、製造方法について説明する。従来の
トレンチゲート型のＳｉＣ半導体ＭＯＳ電界効果パワー
トランジスタは、次のようにして作製する。ＳｉＣ基板
１０１上に、エピ成長により、ドリフト領域１０２のた
めの低不純物ｎ型層を成長させ、次に、ｐ型導電性のベ
ース領域１０３のためのｐ型層を成長させ、次に、ｎコ
ンタクト領域１０４のため高不純物のｎ型層を順次成長
させる。次に例えばマスキングを行ってエッチングを行
い、トレンチ部６を形成する。次に、別のマスキングを
行い、ｐコンタクト領域１０５部に、選択的に、表面に
ｐコンタクト用にイオン注入を行って、その後、注入さ
れた不純物を電気的に活性化し、アクセプタとして活性
化させるため、例えば、Ａｒ雰囲気中で、１５００°Ｃ
で１時間程度のアニールを行って、ｐコンタクト領域１
０５を形成する。次に、水蒸気分圧を含んだ、酸素雰囲
気でＳｉＣ表面の熱酸化を行い、ゲート酸化膜７を形成
した後、ゲート電極８、ソース電極１０、ドレイン電極
１１を形成する。Next, a manufacturing method will be described. A conventional trench gate type SiC semiconductor MOS field effect power transistor is manufactured as follows. A low-impurity n-type layer for the drift region 102 is grown on the SiC substrate 101 by epi growth, then a p-type layer for the p-type conductive base region 103 is grown, and then n A high impurity n-type layer is sequentially grown for the contact region 104. Next, etching is performed by, for example, masking to form a trench portion 6. Next, another masking is performed, ions are selectively implanted into the surface of the p-contact region 105 for p-contact, and thereafter, the implanted impurities are electrically activated and activated as an acceptor. Therefore, for example, in an Ar atmosphere at 1500 ° C.
Anneal for about 1 hour in p contact region 1
05 is formed. Next, thermal oxidation of the SiC surface is performed in an oxygen atmosphere containing a partial pressure of water vapor to form a gate oxide film 7, and then a gate electrode 8, a source electrode 10, and a drain electrode 11 are formed.
【０００６】なお、ここでは、ｐコンタクト領域１０５
をイオン注入により形成する例について説明したが、そ
の場合に限らず、逆に例えば、ｐコンタクト領域１０５
に相当する層をエピ成長で形成し、領域１０５以外の領
域に窒素のイオン注入を行い、その後に、注入された不
純物を電気的に活性化し、ドナーとして活性化させるた
め、例えば、Ａｒ雰囲気中で、１５００°Ｃで１時間程
度のアニールを行って、ｎコンタクト領域１０４を形成
するようにしてもよい。Here, p contact region 105 is used.
Has been described by ion implantation, but the present invention is not limited to this case.
Is formed by epi-growth, nitrogen ions are implanted into regions other than the region 105, and thereafter, the implanted impurities are electrically activated and activated as donors. The n-contact region 104 may be formed by performing annealing at 1500 ° C. for about one hour.
【０００７】図７は、例えば、電子情報通信学会論文誌
Ｃ-ＩＩ，Vol.J81-Ｃ-ＩＩ，No.1の１３５ページに示さ
れるような構造であり、従来型のウエハー表面にＭＯＳ
チャネルを持つ構造のＳｉＣ半導体を用いたＭＯＳ電界
効果パワートランジスタ半導体装置の概念図である。２
０１はｎ型のＳｉＣ基板、２０２はエピ成長で形成した
低不純物のｎ型の導電性を持つＳｉＣのドリフト領域、
２０３はイオン注入により形成したｐ型導電性ベース領
域、２０４はイオン注入により形成したｎ型導電性のｎ
コンタクト領域、２０７はゲート酸化膜、２０８はゲー
ト電極、２０９はゲート電極に印加した電圧で形成され
るチャネル部、２１０はソース電極、２１１はドレイン
電極を示している。図６と同様にゲート電極２０８に電
圧を印加することにより、ｐ型導電性ベース領域２０３
の表面のチャネル部２０９にｎ型反転層が形成され、ｎ
型導電性コンタクト領域２０４とドリフト領域２０２間
に電流が導通し、ドリフト領域２０２を経てドレイン電
極２１１に電流が流れる。FIG. 7 shows a structure as shown on page 135 of the IEICE Transactions C-II, Vol.J81-C-II, No. 1, for example, in which a MOS is formed on the surface of a conventional wafer.
FIG. 3 is a conceptual diagram of a MOS field-effect power transistor semiconductor device using a SiC semiconductor having a channel. 2
01 is an n-type SiC substrate, 202 is a low-impurity n-type SiC drift region formed by epitaxial growth,
203 is a p-type conductive base region formed by ion implantation, 204 is an n-type conductive n formed by ion implantation.
A contact region, 207 is a gate oxide film, 208 is a gate electrode, 209 is a channel portion formed by a voltage applied to the gate electrode, 210 is a source electrode, and 211 is a drain electrode. By applying a voltage to the gate electrode 208 as in FIG. 6, the p-type conductive base region 203 is formed.
An n-type inversion layer is formed in the channel portion 209 on the surface of
A current flows between the mold conductive contact region 204 and the drift region 202, and a current flows to the drain electrode 211 via the drift region 202.
【０００８】[0008]
【発明が解決しようとする課題】ＳｉＣはＳｉに比較し
絶縁破壊電界強度が１０倍大きい。この特長を利用し
て、素子特性の向上を図る様に素子の構造を最適化する
と、ＳｉＣ中にはＳｉの絶縁破壊電界強度の十倍に近い
電界が存在する。このため、上述したような図６の従来
のトレンチゲート型のＳｉＣ半導体を用いたＭＯＳ電界
効果パワートランジスタでは、絶縁破壊電界強度に近い
電界が発生するＳｉＣ部分に接したゲート酸化膜中にお
いても、両者の誘電率比によって定まる電界が発生し、
その強度は酸化膜の絶縁破壊電界強度を越えることか
ら、酸化膜中で絶縁破壊が生じる。またトレンチゲート
構造では、特にトレンチ下部の角部分で電界集中が起こ
り、酸化膜中の電界強度が大きくなり、上記理由と相ま
って、ゲート酸化膜に絶縁破壊が生じ易い。このような
結果、従来のトレンチゲート型のＳｉＣ半導体を用いた
ＭＯＳ電界効果パワートランジスタでは、ＳｉＣの材料
特性から期待される素子耐圧が得られないという問題点
があった。SUMMARY OF THE INVENTION SiC has a dielectric field strength that is 10 times greater than Si. By utilizing this feature and optimizing the structure of the device so as to improve the device characteristics, an electric field in the SiC that is nearly ten times as large as the electric field strength of the dielectric breakdown of Si exists. Therefore, in the MOS field-effect power transistor using the conventional trench gate type SiC semiconductor of FIG. 6 as described above, even in the gate oxide film in contact with the SiC portion where an electric field close to the breakdown electric field strength is generated. An electric field determined by the dielectric constant ratio of both occurs,
Since the strength exceeds the breakdown electric field strength of the oxide film, breakdown occurs in the oxide film. Further, in the trench gate structure, electric field concentration occurs particularly in the corner portion at the lower portion of the trench, and the electric field intensity in the oxide film increases, and in combination with the above-described reason, dielectric breakdown easily occurs in the gate oxide film. As a result, in a conventional MOS field effect power transistor using a trench gate type SiC semiconductor, there is a problem that an element withstand voltage expected from the material characteristics of SiC cannot be obtained.
【０００９】一方、図７に示した、従来の基板表面にＭ
ＯＳチャネルを持つ構造のＭＯＳパワートランジスタで
は、不純物を注入後、不純物を電気的に活性化させる工
程で、例えば、Ａｒ雰囲気中で、１５００°Ｃで１時間
のアニールを行う必要がある。この時、表面のＳｉが選
択的に離脱したり、表面で部分的に不均一に成長やエッ
チングが生じることにより、ＳｉＣの表面に荒れが生じ
たり、階段状のステップ構造が形成される問題があっ
た。基板表面にＭＯＳチャネルを持つ構造のＭＯＳパワ
ートランジスタでは、この荒れもしくはステップの生じ
た面が、ＭＯＳチャネルの界面となる構造のため、ＭＯ
Ｓ界面の劣化により、十分なチャネル特性が得られない
問題があった。On the other hand, as shown in FIG.
In a MOS power transistor having a structure having an OS channel, it is necessary to perform annealing at 1500 ° C. for 1 hour in an Ar atmosphere, for example, in a step of electrically activating the impurities after the implantation of the impurities. At this time, there is a problem that the Si on the surface is selectively detached, or the surface is unevenly grown or etched on the surface, so that the surface of the SiC is roughened or a step-like step structure is formed. there were. In a MOS power transistor having a structure in which a MOS channel is provided on the surface of the substrate, the surface on which the roughness or the step occurs becomes an interface of the MOS channel.
There is a problem that sufficient channel characteristics cannot be obtained due to deterioration of the S interface.
【００１０】また、基板表面にＭＯＳチャネルを持つ構
造では、チャネル移動度が大きい１１２バー０面を、Ｍ
ＯＳチャネルの界面として用いるためには、入手が困難
な１１２バー０面ウエハーを作製し、さらにそれに伴い
従来基板面のプロセスとは異なった、エピ成長、注入、
電極等の作製条件が必要であるという問題点があった。In the structure having a MOS channel on the surface of the substrate, the plane 112 bar 0 having a large channel mobility is
In order to use it as an interface of the OS channel, a hard-to-obtain 112-bar zero-plane wafer is manufactured, and the epitaxial growth, implantation,
There has been a problem that manufacturing conditions for electrodes and the like are required.
【００１１】本発明は、かかる問題点を解決するために
成されたもので、ＳｉＣ中の電界分布の強い箇所がゲー
ト酸化膜から離れた所になるような構造を備え、ゲート
酸化膜が破壊されない特長をもち、ＳｉＣの材料特性に
対応した素子耐圧を持つ半導体装置及びその製造方法を
提供することを目的とする。The present invention has been made in order to solve such a problem, and has a structure in which a place where the electric field distribution in SiC is strong is located away from the gate oxide film. It is an object of the present invention to provide a semiconductor device having characteristics not to be exhibited and having an element breakdown voltage corresponding to the material characteristics of SiC, and a method for manufacturing the same.
【００１２】[0012]
【課題を解決するための手段】この発明は、ＳｉＣ半導
体からなる基板と、基板上に設けられ、低不純物のｎ型
の導電性を有するｎ型層と、ｎ型層上に設けられ、ｐ型
の導電性を有するｐ型ベース層と、ｐ型ベース層上に設
けられ、高不純物のｎ型の導電性を有するｎ型コンタク
ト層と、ｐ型ベース層上の上記ｎ型コンタクト層が設け
られていない領域に設けられたｐ型コンタクト領域と、
ｎ型コンタクト層及び上記ｐ型ベース層を貫通してｎ型
層にまで達する深さを有する溝と、溝の底面及び側壁上
に設けられたゲート酸化膜と、ゲート酸化膜を介在させ
て上記溝の側壁上に設けられたゲート電極と、ｎ型コン
タクト層及び上記ｐ型コンタクト領域に接触して設けら
れたソース電極と、基板の下面に設けられたドレイン電
極と、ゲート電極に電圧が印加されたときに反転してｎ
型コンタクト層とｎ型層とを導通させるチャネル手段
と、溝の下側の上記ｎ型層内に設けられ、高電圧遮断時
のｎ型層からのゲート酸化膜への電界の侵入を遮蔽する
溝下部電界シールド手段とを備えた半導体装置である。According to the present invention, there is provided a substrate made of a SiC semiconductor, an n-type layer provided on the substrate and having n-type conductivity of low impurity, and a p-type layer provided on the n-type layer. A p-type base layer having n-type conductivity, an n-type contact layer provided on the p-type base layer and having high impurity n-type conductivity, and the n-type contact layer on the p-type base layer A p-type contact region provided in a region that is not
a groove having a depth penetrating the n-type contact layer and the p-type base layer to reach the n-type layer; a gate oxide film provided on the bottom and side walls of the groove; and a gate oxide film interposed therebetween. A voltage is applied to the gate electrode provided on the sidewall of the groove, the source electrode provided in contact with the n-type contact layer and the p-type contact region, the drain electrode provided on the lower surface of the substrate, and the gate electrode. N when it is inverted
A channel means for conducting the type contact layer and the n-type layer, and a channel means provided in the n-type layer below the groove to block an electric field from entering the gate oxide film from the n-type layer when the high voltage is cut off. And a semiconductor device provided with an electric field shield means below the groove.
【００１３】また、溝下部電界シールド手段が、ｐ型の
導電性を有するｐ型領域から構成されている。Further, the electric field shielding means under the groove is constituted by a p-type region having p-type conductivity.
【００１４】また、ｐ型コンタクト領域の範囲におい
て、ｐ型ベース層の下面から略々垂直方向に向かって溝
の底面の深さより深い位置に至るまで延びて設けられ、
ｐ型ベース層の下方からのゲート酸化膜への電界の侵入
を遮蔽するベース層下部電界シールド手段をさらに備え
ている。In the range of the p-type contact region, the lower surface of the p-type base layer extends substantially vertically to a position deeper than the depth of the bottom surface of the groove,
The semiconductor device further includes a base layer lower electric field shield means for shielding an electric field from entering the gate oxide film from below the p-type base layer.
【００１５】また、ベース層下部電界シールド手段が、
ｐ型の導電性を有するｐ型領域から構成されている。[0015] Further, the electric field shielding means under the base layer includes:
It is composed of a p-type region having p-type conductivity.
【００１６】また、溝下部電界シールド手段とベース層
下部電界シールド手段とを電気的に結合する電界シール
ド結合手段をさらに備えている。Further, there is further provided an electric field shield coupling means for electrically coupling the groove lower electric field shield means and the base layer lower electric field shield means.
【００１７】また、ｐ型ベース層とｎ型層との間に設け
られ、ｎ型層より高いｎ型の導電性を有する電流拡散層
をさらに備えている。Further, the semiconductor device further includes a current diffusion layer provided between the p-type base layer and the n-type layer and having n-type conductivity higher than that of the n-type layer.
【００１８】また、溝下部電界シールド手段が、溝の幅
より広い幅を有している。Further, the electric field shield means below the groove has a width wider than the width of the groove.
【００１９】また、チャネル手段が溝の側壁から構成さ
れている。Further, the channel means is constituted by the side wall of the groove.
【００２０】また、チャネル手段が、溝の上記側壁にお
けるＳｉＣ結晶の１、１、２バー、０面に設けられてい
る。Further, channel means are provided on the 1, 1, 2 bar and 0 planes of the SiC crystal on the side walls of the groove.
【００２１】また、この発明は、ＳｉＣ半導体からなる
基板上に、低不純物のｎ型の導電性を有するｎ型層を形
成する工程と、ｎ型層上に、ｐ型の導電性を有するｐ型
ベース層を形成する工程と、ｐ型ベース層上に、高不純
物のｎ型の導電性を有するｎ型コンタクト層を形成する
工程と、ｐ型ベース層上にｐ型コンタクト領域を形成す
る工程と、溝を形成する予定領域のｎ型層内に、高電圧
遮断時の上記ｎ型層からのゲート酸化膜への電界の侵入
をシールドさせるための溝下部電界シールド手段を形成
する工程と、ｎ型コンタクト層及びｐ型ベース層を貫通
してｎ型層内の溝下部電界シールド手段に達する深さを
有する溝を形成する工程と、溝の底面及び側壁上にゲー
ト酸化膜を形成する工程と、ゲート酸化膜を介在させて
溝の側壁上にゲート電極を形成する工程と、ｎ型コンタ
クト層及びｐ型コンタクト領域に接触させてソース電極
を形成する工程と、基板の下面にドレイン電極を形成す
る工程とを備えた半導体装置の製造方法である。According to the present invention, there is further provided a step of forming an n-type layer having low impurity n-type conductivity on a substrate made of a SiC semiconductor, and forming a p-type conductive layer having p-type conductivity on the n-type layer. Forming a p-type base layer, forming an n-type contact layer having high impurity n-type conductivity on the p-type base layer, and forming a p-type contact region on the p-type base layer Forming a groove lower electric field shield means for shielding an electric field from entering the gate oxide film from the n-type layer at the time of high voltage interruption in the n-type layer in a region where a groove is to be formed; forming a groove having a depth penetrating the n-type contact layer and the p-type base layer and reaching the groove lower electric field shielding means in the n-type layer; and forming a gate oxide film on the bottom and side walls of the groove And the gate oxide film Forming an electrode, forming a source electrode in contact with the n-type contact layer and p-type contact region, a manufacturing method of a semiconductor device and forming a drain electrode on the lower surface of the substrate.
【００２２】また、ｐ型コンタクト領域の範囲におい
て、ｐ型ベース層の下面から、略々垂直方向に向かっ
て、溝の底面の深さより深い位置にかけて、ｐ型ベース
層の下部からのゲート酸化膜への電界の侵入をシールド
させるためのベース層下部電界シールド手段を形成する
工程をさらに備えている。Further, in the range of the p-type contact region, the gate oxide film from the lower portion of the p-type base layer extends from the lower surface of the p-type base layer to a position substantially deeper than the depth of the bottom surface of the groove. Forming a base layer lower electric field shield means for shielding the intrusion of an electric field into the base layer.
【００２３】また、溝下部電界シールド手段とベース層
下部電界シールド手段とを電気的に結合する電界シール
ド結合手段を形成する工程をさらに備えている。Further, the method further comprises the step of forming electric field shield coupling means for electrically coupling the electric field shield means under the groove and the electric field shield means under the base layer.
【００２４】また、ｐ型ベース層とｎ型層との間に、ｎ
型層より高いｎ型の導電性を有する電流拡散層を形成す
る工程をさらに備えている。Further, between the p-type base layer and the n-type layer, n
Forming a current diffusion layer having n-type conductivity higher than that of the mold layer;
【００２５】また、溝下部電界シールド手段を形成する
際に、溝の幅より広い幅を有するように形成する。Further, when the electric field shielding means under the groove is formed, it is formed so as to have a width wider than the width of the groove.
【００２６】[0026]
【発明の実施の形態】実施の形態１．図１は本発明の一
実施の形態を示すもので、トレンチゲート型のＳｉＣ半
導体ＭＯＳ電界効果パワートランジスタ半導体装置の断
面図である。１はｎ型のＳｉＣ基板、２は低不純物のｎ
型の導電性を有するドリフト領域、３はドレイン電流制
御用のＭＯＳチャネルを形成するためのｐ型導電性のベ
ース領域、４はｎ型導電性のｎコンタクト領域、５はｐ
型導電性のｐコンタクト領域、６はエッチングにより形
成したトレンチ部、７はトレンチ部６の底面および側壁
に設けられたゲート酸化膜、８はゲート電極、９はゲー
ト電極に印加した電圧で形成されるチャネル部、１０は
ソース電極、１１はドレイン電極、１２はゲート酸化膜
７部の電界強度を緩和するために、トレンチ部６の下部
にエピ成長もしくはイオン注入により形成した、ｐ型導
電性のトレンチ下部電界シールド領域、１３はｐ型のベ
ース領域３下部にエピ成長もしくはイオン注入により形
成した、ｐ型導電性のベース領域下部電界シールド領域
である。DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiment 1 FIG. 1 shows an embodiment of the present invention and is a cross-sectional view of a trench gate type SiC semiconductor MOS field effect power transistor semiconductor device. 1 is an n-type SiC substrate, 2 is a low impurity n
Drift region 3 having a p-type conductivity; 3 a p-type conductive base region for forming a MOS channel for controlling drain current; 4 a n-type conductive n-contact region;
Mold conductive p-contact region, 6 is a trench formed by etching, 7 is a gate oxide film provided on the bottom and side walls of the trench 6, 6 is a gate electrode, 9 is a voltage applied to the gate electrode. A channel portion, 10 is a source electrode, 11 is a drain electrode, and 12 is a p-type conductive layer formed under the trench portion 6 by epi-growth or ion implantation in order to reduce the electric field intensity of the gate oxide film 7 portion. The trench lower electric field shield region 13 is a p-type conductive base region lower electric field shield region formed under the p-type base region 3 by epitaxial growth or ion implantation.
【００２７】動作について説明する。ゲート電極８に電
圧を印加することにより、チャネル部９にｎ型反転層が
形成され、ｎ型導電性のｎコンタクト領域４とドリフト
領域２間に電流が導通し、ドリフト領域２を経てドレイ
ン電極１１に電流が流れる。ゲート電極８に電圧が印加
されないオフ状態では、チャネル部９にｎ型反転層が形
成されない。この時ソース電極１０とドレイン電極１１
間に印加された高電圧は、ドリフト領域２、トレンチ下
部電界シールド領域１２、ベース領域下部電界シールド
領域１３に延びた空乏層で遮断される。ここで、本実施
の形態においては、トレンチ部６の下部にトレンチ下部
電界シールド１２を備えているので、それによって電界
侵入が阻まれ、ゲート酸化膜７部分、特に、電界集中が
起こるトレンチ部６下部の角部分の電界強度が緩和さ
れ、ゲート酸化膜７の絶縁破壊が生じない。また、ｐベ
ース領域３下にもベース領域下部電界シールド領域１３
が備えられているため、ｐベース領域下からの電界の浸
入がシールドされるため、ゲート酸化膜７の電界強度が
緩和される。このような構造により、逆高電圧遮断時の
電界強度の最強な箇所は、シールド領域１３の下端にな
り、電界強度の強い部分とゲート酸化膜７に接する部分
が接触せずに分離されることにより、酸化膜の絶縁破壊
が生じない。The operation will be described. By applying a voltage to the gate electrode 8, an n-type inversion layer is formed in the channel portion 9, current flows between the n-type conductive n-contact region 4 and the drift region 2, and the drain electrode passes through the drift region 2. Current flows through 11. When no voltage is applied to the gate electrode 8, no n-type inversion layer is formed in the channel portion 9. At this time, the source electrode 10 and the drain electrode 11
The high voltage applied therebetween is cut off by the depletion layer extending to the drift region 2, the lower electric field shield region 12 of the trench, and the lower electric field shield region 13 of the base region. Here, in the present embodiment, since trench lower electric field shield 12 is provided below trench portion 6, electric field penetration is prevented by this, and gate oxide film portion 7, particularly trench portion 6 where electric field concentration occurs, is prevented. The electric field intensity in the lower corner portion is reduced, and the dielectric breakdown of the gate oxide film 7 does not occur. Also, under the p base region 3, the base region lower electric field shield region 13 is provided.
Is provided, the infiltration of the electric field from below the p base region is shielded, and the electric field strength of the gate oxide film 7 is reduced. With such a structure, the portion where the electric field strength is strongest at the time of reverse high voltage cutoff is located at the lower end of the shield region 13, and the portion where the electric field strength is strong and the portion in contact with the gate oxide film 7 are separated without contact. Thereby, dielectric breakdown of the oxide film does not occur.
【００２８】次に、製造方法について説明する。本実施
の形態に示したトレンチゲート型のＳｉＣ半導体ＭＯＳ
電界効果パワートランジスタは例えば、次のように作製
できる。ＳｉＣ基板１上に、ＣＶＤエピ成長により、ド
リフト領域２のための低不純物ｎ型層を成長させ、次
に、ｐ型導電性のベース領域３のためのｐ型層を成長さ
せ、次に、ｎコンタクト領域４のため高不純物のｎ型層
を順次成長させる。次に、マスキングを行い、ｐコンタ
クト領域５部に、選択的に、表面にｐコンタクト用に高
濃度のＡｌのイオン注入を行って、ｐコンタクト領域５
を形成し、次に、例えば、同じマスクを用い、トレンチ
部６の下部（底面）の深さより深い領域まで垂直方向に
（すなわち、深さ方向に）Ａｌのイオン注入を行い、ベ
ース領域下部電界シールド領域１３を形成する。また、
次に例えば別のマスキングを行いトレンチ部６に選択的
に、トレンチ部６下部（底面）の深さより深い領域にＡ
ｌ（アクセプタ）のイオン注入を行い、トレンチ下部電
界シールド領域１２を形成する。このとき、トレンチ下
部電界シールド領域１２の厚さが、ドリフト領域２から
の酸化ゲート膜７への電界の侵入を妨げるに十分な所定
の厚さになるようにする。次に例えば同じマスクを用
い、エッチングを行いトレンチ部６を形成する。次に例
えば、水蒸気分圧を含んだ、酸素雰囲気でＳｉＣ表面の
熱酸化を行い、ゲート酸化膜７を形成した後、ゲート電
極８、ソース電極１０、ドレイン電極１１を形成する。Next, the manufacturing method will be described. Trench gate type SiC semiconductor MOS shown in this embodiment
The field effect power transistor can be manufactured, for example, as follows. A low-impurity n-type layer for the drift region 2 is grown on the SiC substrate 1 by CVD epi growth, and then a p-type layer for the p-type conductive base region 3 is grown. A high impurity n-type layer is sequentially grown for the n-contact region 4. Next, masking is performed, and high-concentration Al ion implantation for p-contact is selectively performed on the surface of the p-contact region 5 in the p-contact region 5.
Then, using the same mask, for example, ion implantation of Al is performed in a vertical direction (that is, in the depth direction) to a region deeper than the depth (bottom) of the trench portion 6, thereby forming a base region lower electric field. The shield region 13 is formed. Also,
Next, for example, another masking is performed to selectively form the trench portion 6 in a region deeper than the depth of the lower portion (bottom surface) of the trench portion 6.
I (acceptor) ions are implanted to form a trench lower electric field shield region 12. At this time, the thickness of the trench lower electric field shield region 12 is set to a predetermined thickness sufficient to prevent the electric field from entering the oxide gate film 7 from the drift region 2. Next, for example, using the same mask, etching is performed to form a trench portion 6. Next, for example, thermal oxidation of the SiC surface is performed in an oxygen atmosphere containing a partial pressure of water vapor to form a gate oxide film 7, and then a gate electrode 8, a source electrode 10, and a drain electrode 11 are formed.
【００２９】この例では、ｎコンタクト領域４のための
高不純物のエピ成長したｎ型層にイオン注入により、ｐ
コンタクト領域５を形成する例を示したが、逆に、ｐコ
ンタクト領域５のためのｐ層を成長により形成し、そこ
に窒素のイオン注入により、ｎコンタクト領域４を形成
しても作製可能である。また、ここでは、ｐベース領域
３のためのｐ型層を、エピ成長で形成する例を示した
が、イオン注入によっても可能である。In this example, p-type ions are implanted into the n-type layer of high impurity for epitaxial growth for the n-contact region 4 by ion implantation.
Although the example in which the contact region 5 is formed has been described, it is possible to form the n-contact region 4 by forming a p-layer for the p-contact region 5 by growth and implanting nitrogen ions therein. is there. Further, here, an example is shown in which the p-type layer for the p base region 3 is formed by epi growth, but it is also possible by ion implantation.
【００３０】以上のように、本実施の形態が示す半導体
装置では、トレンチ部６の下部にトレンチ下部電界シー
ルド領域１２があるため、ゲート酸化膜７の電界強度が
緩和される。また、ｐベース領域３下にもベース領域下
部電界シールド領域１３が備えられているため、ｐベー
ス領域下からの電界の浸入がシールドされるため、ゲー
ト酸化膜７の電界強度が緩和される。このような構造に
より、逆高電圧遮断時の電界強度の最強な箇所は、ｐシ
ールド領域の下端になり、電界強度の強い部分と、ゲー
ト酸化膜７に接する部分が接触せずに分離されることに
より、酸化膜の絶縁破壊が生じない。この結果、高電圧
遮断時の、ゲート酸化膜７の電界強度を低減し、ゲート
酸化膜７の絶縁破壊が防がれ、ＳｉＣ材料の絶縁特性に
対応した、素子耐圧を得ることができる。As described above, in the semiconductor device according to the present embodiment, the electric field strength of the gate oxide film 7 is reduced since the trench lower electric field shield region 12 is provided below the trench portion 6. Further, since the base region lower electric field shield region 13 is also provided below the p base region 3, the infiltration of the electric field from below the p base region is shielded, so that the electric field intensity of the gate oxide film 7 is reduced. With such a structure, the portion where the electric field strength is strongest at the time of reverse high voltage cutoff is the lower end of the p shield region, and the portion where the electric field strength is strong and the portion in contact with the gate oxide film 7 are separated without contact. Thus, dielectric breakdown of the oxide film does not occur. As a result, the electric field strength of the gate oxide film 7 at the time of high-voltage interruption is reduced, dielectric breakdown of the gate oxide film 7 is prevented, and an element withstand voltage corresponding to the insulating characteristics of the SiC material can be obtained.
【００３１】また、本実施の形態が示す製造方法に於い
ては、トレンチ部６を形成する前の工程で、イオン注入
と活性化アニールを行い、その後に、トレンチ部６を形
成し、その側壁をチャネルとして用いるので、チャネル
が形成されるトレンチ部６の側壁に生じる注入の損傷、
及び、アニールによる表面の荒れを低減することがで
き、高移動度で信頼性の高いチャネルを形成することが
できる効果があり、素子特性を向上できる。Further, in the manufacturing method shown in the present embodiment, ion implantation and activation annealing are performed in a step before the trench 6 is formed, and thereafter, the trench 6 is formed and the side wall thereof is formed. Is used as a channel, so that implantation damage occurs on the side wall of the trench 6 where the channel is formed,
In addition, surface roughness due to annealing can be reduced, a channel having high mobility and high reliability can be formed, and device characteristics can be improved.
【００３２】実施の形態２．図２は本発明の別の一実施
の形態を示すもので、トレンチゲート型のＳｉＣ半導体
ＭＯＳ電界効果パワートランジスタ半導体装置の断面図
である。１はｎ型のＳｉＣ基板、２はドリフト領域、３
はベース領域、４はｎコンタクト領域、５はｐコンタク
ト領域、６はトレンチ部、７はゲート酸化膜、８はゲー
ト電極、９はチャネル部、１０はソース電極、１１はド
レイン電極、１２はトレンチ下部電界シールド領域、１
３はｐ型導電性のベース領域下部電界シールド領域、１
４はトレンチ下部電界シールド領域１２とベース領域下
部電界シールド領域１３を電気的に結合する、電界シー
ルド結合領域をしめしている。ゲート電極８への電圧の
印加による、高電圧の遮断、導通の切り替えの原理及び
電界シールド領域による、酸化膜における電界緩和の原
理は実施の形態１と同様である。Embodiment 2 FIG. FIG. 2 shows another embodiment of the present invention and is a sectional view of a trench gate type SiC semiconductor MOS field effect power transistor semiconductor device. 1 is an n-type SiC substrate, 2 is a drift region, 3
Is a base region, 4 is an n-contact region, 5 is a p-contact region, 6 is a trench portion, 7 is a gate oxide film, 8 is a gate electrode, 9 is a channel portion, 10 is a source electrode, 11 is a drain electrode, and 12 is a trench. Lower electric field shield area, 1
Reference numeral 3 denotes a p-type conductive base region lower electric field shield region;
Reference numeral 4 denotes an electric field shield coupling region for electrically coupling the trench lower electric field shield region 12 and the base region lower electric field shield region 13. The principle of switching off and conducting high voltage by applying a voltage to the gate electrode 8 and the principle of electric field relaxation in the oxide film by the electric field shield region are the same as in the first embodiment.
【００３３】次に製造方法について説明する。本実施の
形態に示したトレンチゲート型のＳｉＣ半導体ＭＯＳ電
界効果パワートランジスタは、例えば、次のように作製
できる。ＳｉＣ基板１上に、ドリフト領域２のための低
不純物ｎ型層を、ｐベース領域３のためのｐ型層を、ｎ
コンタクト領域４のため高不純物のｎ型層を順次成長す
る。次にマスキングを行いｐコンタクト領域５部に選択
的に、表面にコンタクト用に高濃度のＡｌのイオン注入
を行い、次に例えば同じマスクを用い、トレンチ下部の
深さより深い領域までＡｌのイオン注入を行い、ベース
領域下部電界シールド領域１３を形成する。また次に例
えば別のマスキングを行いトレンチ部６と電界シールド
結合領域１４に選択的に、トレンチ下部の深さより深い
領域にＡｌのイオン注入を行い、トレンチ下部電界シー
ルド領域１２と電界シールド結合領域１４を形成する。
次に例えば別のマスクを用い、エッチングを行いトレン
チ部６を形成する。次ゲート酸化膜７を形成した後、ゲ
ート電極８、ソース電極１０、ドレイン電極１１を形成
する。Next, the manufacturing method will be described. The trench gate type SiC semiconductor MOS field effect power transistor shown in the present embodiment can be manufactured, for example, as follows. On the SiC substrate 1, a low impurity n-type layer for the drift region 2, a p-type layer for the p base region 3,
A high impurity n-type layer is sequentially grown for the contact region 4. Next, masking is performed, and high-concentration Al ions are implanted into the surface of the p-contact region 5 selectively for contact, and then, for example, using the same mask, Al ions are implanted to a region deeper than the trench lower portion. To form the base region lower electric field shield region 13. Then, for example, another masking is performed to selectively implant Al ions into the trench portion 6 and the electric field shield coupling region 14 in a region deeper than the depth below the trench, and thereby the trench lower electric field shield region 12 and the electric field shield coupling region 14 are formed. To form
Next, for example, using another mask, etching is performed to form a trench portion 6. After forming the next gate oxide film 7, a gate electrode 8, a source electrode 10, and a drain electrode 11 are formed.
【００３４】この例では、ドリフト領域にイオン注入に
より、トレンチ下部電界シールド領域１２、ベース領域
下部電界シールド領域１３並びに電界シールド結合領域
１４を形成する作製方法を示したが、逆に例えば上記３
領域に相当する層をエピ成長で形成し、３領域以外の領
域に窒素のイオン注入を行いｎ型導電領域を作製するこ
とも可能である。In this example, the manufacturing method of forming the trench lower electric field shield region 12, the base region lower electric field shield region 13, and the electric field shield coupling region 14 by ion implantation into the drift region has been described.
It is also possible to form an n-type conductive region by forming a layer corresponding to the region by epi growth and implanting nitrogen ions into a region other than the three regions.
【００３５】以上のように、本実施の形態における半導
体装置において、トレンチ下部電界シールド領域１２と
ベース領域下部電界シールド領域１３によりゲート酸化
膜７部の電界強度が緩和され酸化膜の絶縁破壊が軽減さ
れる原理は実施の形態１と同様である。さらに本実施の
形態では、ｐベース領域とｐシールド領域を電気的に結
合する構造を備えているので、電位的に浮遊した領域が
生じず、電荷の蓄積の片寄も生じないため、より安定な
スイッチング動作と酸化膜の高い信頼性が得られる。As described above, in the semiconductor device according to the present embodiment, the electric field strength of gate oxide film 7 is reduced by trench lower electric field shield region 12 and base region lower electric field shield region 13 and dielectric breakdown of the oxide film is reduced. The principle performed is the same as in the first embodiment. Further, in the present embodiment, a structure is provided in which the p base region and the p shield region are electrically coupled, so that a region floating in potential does not occur, and a bias in charge accumulation does not occur. The switching operation and high reliability of the oxide film can be obtained.
【００３６】また、本実施の形態における製造方法にお
いても、上述の実施の形態１と同様に、トレンチ部６を
形成する前の工程で、イオン注入と、活性化アニールを
行うことができるので、チャネルが形成されるトレンチ
部６の側壁に生じる注入の損傷、アニールによる表面の
荒れを低減することができ、高移動度で信頼性の高いチ
ャネルを形成することができる効果があり、素子特性を
向上できる。In the manufacturing method according to the present embodiment, as in the first embodiment, ion implantation and activation annealing can be performed in a step before forming trench 6. Damage due to implantation on the side wall of the trench portion 6 where the channel is formed and roughness of the surface due to annealing can be reduced, so that a channel having high mobility and high reliability can be formed. Can be improved.
【００３７】実施の形態３．図３は本発明の別の一実施
の形態を示すもので、トレンチゲート型のＳｉＣ半導体
ＭＯＳ電界効果パワートランジスタ半導体装置の断面図
である。１はｎ型のＳｉＣ基板、２はドリフト領域、３
はベース領域、４はｎコンタクト領域、５はｐコンタク
ト領域、６はトレンチ部、７はゲート酸化膜、８はゲー
ト電極、９はチャネル部、１０はソース電極、１１はド
レイン電極、１２はトレンチ下部電界シールド領域、１
３はベース領域下部電界シールド領域、１４は電界シー
ルド結合領域、１５は導通時の抵抗を低減するためにｐ
ベース領域の下部に設けた、ドリフト領域２より導電性
の高い（すなわち、キャリア濃度の高い）ｎ型の電流拡
散層である。ゲート電極８への電圧を印加による、高電
圧の遮断、導通の切り替え、及び電界シールド領域の効
果による、酸化膜における電界緩和の原理は実施の形態
１及び２と同様である。Embodiment 3 FIG. 3 shows another embodiment of the present invention and is a cross-sectional view of a trench gate type SiC semiconductor MOS field effect power transistor semiconductor device. 1 is an n-type SiC substrate, 2 is a drift region, 3
Is a base region, 4 is an n-contact region, 5 is a p-contact region, 6 is a trench portion, 7 is a gate oxide film, 8 is a gate electrode, 9 is a channel portion, 10 is a source electrode, 11 is a drain electrode, and 12 is a trench. Lower electric field shield area, 1
Reference numeral 3 denotes a base region lower electric field shield region, 14 denotes an electric field shield coupling region, and 15 denotes p for reducing resistance during conduction.
An n-type current diffusion layer provided below the base region and having higher conductivity than the drift region 2 (that is, having a higher carrier concentration). The principle of electric field relaxation in an oxide film by applying a voltage to the gate electrode 8 to cut off a high voltage, switch conduction, and effect the electric field shield region is the same as in the first and second embodiments.
【００３８】次に製造方法について説明する。本実施の
形態に示したトレンチゲート型のＳｉＣ半導体ＭＯＳ電
界効果パワートランジスタは例えば、次のように作製で
きる。ＳｉＣ基板１上に、ドリフト領域２のための低不
純物ｎ型層を、次に電流拡散層１５のための、ドリフト
領域２より導電率の高いｎ型層を、次にｐベース領域３
のためのｐ型層を、次にｎコンタクト領域４のための高
不純物のｎ型層を順次成長する。実施の形態２と同様に
選択的に、ｐコンタクト領域５、ベース領域下部電界シ
ールド領域１３、トレンチ下部電界シールド領域１２並
びに電界シールド結合領域１４をＡｌのイオン注入によ
り形成する。また次に例えば別のマスキングによるドナ
ーのイオン注入によりｎコンタクト領域４を形成する。
次に例えば別のマスクを用い、エッチングを行いトレン
チ部６を形成する。次にゲート酸化膜７を形成した後、
ゲート電極８、ソース電極１０、ドレイン電極１１を形
成する。この例では、エピ成長により電流拡散層を形成
する作製例を示したが、ドナーのイオン注入により電流
拡散層を形成する作製例も可能である。Next, the manufacturing method will be described. The trench gate type SiC semiconductor MOS field effect power transistor shown in the present embodiment can be manufactured, for example, as follows. A low-impurity n-type layer for the drift region 2, an n-type layer having a higher conductivity than the drift region 2 for the current diffusion layer 15, and a p-base region 3
And then a highly doped n-type layer for n-contact region 4 is grown. As in the second embodiment, the p contact region 5, the base region lower electric field shield region 13, the trench lower electric field shield region 12, and the electric field shield coupling region 14 are selectively formed by ion implantation of Al. Next, the n-contact region 4 is formed by ion implantation of a donor by another masking, for example.
Next, for example, using another mask, etching is performed to form a trench portion 6. Next, after forming the gate oxide film 7,
A gate electrode 8, a source electrode 10, and a drain electrode 11 are formed. In this example, a production example in which the current diffusion layer is formed by epi growth is described, but a production example in which the current diffusion layer is formed by ion implantation of a donor is also possible.
【００３９】以上のように、本実施の形態に示した半導
体装置は、上述の実施の形態１及び２と同様の効果が得
られるとともに、さらに、ｐベース領域３の下部に、ド
リフト領域２より導電性の高いｎ型の電流拡散層１５そ
なえているので、導通時には、電流経路は、ゲート電圧
印加により反転して形成されたチャネル９近傍からのみ
ではなく、ｎ型の電流拡散層１５全体から、ｎ型ドリフ
ト領域２を経て流れるので、その抵抗は、電流拡散層１
５がないときに比べ低減される効果がある。As described above, the semiconductor device shown in the present embodiment can obtain the same effects as those of the above-described first and second embodiments, and further, below the p base region 3, Since the n-type current diffusion layer 15 having high conductivity is provided, when conducting, the current path is not only from the vicinity of the channel 9 formed by inversion by applying a gate voltage, but also from the entire n-type current diffusion layer 15. , N-type drift region 2, so that its resistance is
There is an effect of being reduced as compared with the case where there is no 5.
【００４０】また、本実施の形態における製造方法にお
いても、上述の実施の形態１と同様に、トレンチ部６を
形成する前の工程で、イオン注入と、活性化アニールを
行うことができるので、チャネルが形成されるトレンチ
部６の側壁に生じる注入の損傷、アニールによる表面の
荒れを低減することができ、高移動度で信頼性の高いチ
ャネルを形成することができる効果があり、素子特性を
向上できる。In the manufacturing method according to the present embodiment, as in the first embodiment, ion implantation and activation annealing can be performed in a step before forming trench 6. Damage due to implantation on the side wall of the trench portion 6 where the channel is formed and roughness of the surface due to annealing can be reduced, so that a channel having high mobility and high reliability can be formed. Can be improved.
【００４１】実施の形態４．図４は本発明の別の一実施
の形態を示すもので、トレンチゲート型のＳｉＣ半導体
ＭＯＳ電界効果パワートランジスタ半導体装置の断面図
である。１はｎ型のＳｉＣ基板、２はドリフト領域、３
はベース領域、４はｎコンタクト領域、５はｐコンタク
ト領域、６はトレンチ部、７はゲート酸化膜、８はゲー
ト電極、９はチャネル部、１０はソース電極、１１はド
レイン電極、１２Ａはトレンチ部６の幅より広い幅を持
ち、トレンチ部６のない領域まで横に延びた構造を有し
たトレンチ下部電界シールド領域、１３はベース領域下
部電界シールド領域、１５は電流拡散層である。ゲート
電極８への電圧を印加による、高電圧の遮断と導通の切
り替え、及び、電界シールド領域１２、１３の効果によ
る、ゲート酸化膜７における電界緩和、電流拡散層１５
による抵抗の低減の原理は実施の形態１から３と同様で
ある。Embodiment 4 FIG. FIG. 4 shows another embodiment of the present invention and is a sectional view of a trench gate type SiC semiconductor MOS field effect power transistor semiconductor device. 1 is an n-type SiC substrate, 2 is a drift region, 3
Is a base region, 4 is an n-contact region, 5 is a p-contact region, 6 is a trench portion, 7 is a gate oxide film, 8 is a gate electrode, 9 is a channel portion, 10 is a source electrode, 11 is a drain electrode, and 12A is a trench. A trench lower electric field shield region having a structure wider than the width of the portion 6 and extending laterally to a region without the trench portion 6, 13 is a base region lower electric field shield region, and 15 is a current diffusion layer. Switching of high-voltage interruption and conduction by applying a voltage to the gate electrode 8, and electric field relaxation in the gate oxide film 7 by the effect of the electric field shield regions 12 and 13, and a current diffusion layer 15
The principle of the reduction of the resistance is the same as in the first to third embodiments.
【００４２】次に製造方法について説明する。本実施の
形態に示したトレンチゲート型のＳｉＣ半導体ＭＯＳ電
界効果パワートランジスタは例えば、次のように作製で
きる。ＳｉＣ基板１上に、ドリフト領域２のための低不
純物ｎ型層を、次に電流拡散層１５のためのｎ型層を、
次にｐベース領域３のためのｐ型層を、次にｎコンタク
ト領域４のための高不純物のｎ型層を順次成長する。実
施の形態３と同様に選択的に、ｐコンタクト領域５、ベ
ース領域下部電界シールド領域１３、トレンチ下部電界
シールド領域１２並びに電界シールド結合領域１４をＡ
ｌのイオン注入により形成する。この時、トレンチ下部
電界シールド領域１２注入のためのマスクパターンを、
トレンチ部６の幅より広くすることにより上部にトレン
チ部６のない横の領域まで延びた注入領域を形成でき
る。また次にドナーのイオン注入によりｎコンタクト領
域４を形成する。次トレンチ部６を形成し、ゲート酸化
膜７を形成した後、ゲート電極８、ソース電極１０、ド
レイン電極１１を形成する。この例では、エピ成長によ
り電流拡散層を形成する作製例を示したが、ドナーのイ
オン注入により電流拡散層を形成する作製例も可能であ
る。Next, the manufacturing method will be described. The trench gate type SiC semiconductor MOS field effect power transistor shown in the present embodiment can be manufactured, for example, as follows. A low impurity n-type layer for the drift region 2 and then an n-type layer for the current diffusion layer 15 are formed on the SiC substrate 1.
Next, a p-type layer for the p-base region 3 and a highly doped n-type layer for the n-contact region 4 are sequentially grown. As in the third embodiment, the p contact region 5, the base region lower electric field shield region 13, the trench lower electric field shield region 12, and the electric field shield coupling region 14 are selectively changed to A.
1 by ion implantation. At this time, a mask pattern for implanting the trench lower electric field shield region 12 is
By making the width wider than the width of the trench 6, an implantation region extending to a lateral region without the trench 6 can be formed at the upper portion. Next, an n-contact region 4 is formed by ion implantation of a donor. After forming the next trench portion 6 and forming the gate oxide film 7, the gate electrode 8, the source electrode 10, and the drain electrode 11 are formed. In this example, a production example in which the current diffusion layer is formed by epi growth is described, but a production example in which the current diffusion layer is formed by ion implantation of a donor is also possible.
【００４３】以上のように、本実施の形態に示した半導
体装置は、上述の実施の形態１〜３と同様の効果が得ら
れるとともに、さらに、トレンチ下部シールド領域１２
の幅が、溝の幅より広く、上部のトレンチ部６のない領
域まで延びた構造であり、特にトレンチ下部の角の部分
と電界強度の大きい箇所とが、平面位置的にも分離され
るので、特にトレンチ下部の角の酸化膜に印加される電
界強度の緩和効果が大きく、酸化膜の絶縁破壊が生じな
い特長がある。As described above, the semiconductor device shown in the present embodiment can obtain the same effects as those of the above-described first to third embodiments, and further, can further improve the lower shield region 12 of the trench.
Is wider than the width of the groove and extends to a region where the upper trench 6 is not provided. In particular, the corner at the lower portion of the trench and the portion where the electric field intensity is high are separated also in a planar position. In particular, the effect of reducing the intensity of the electric field applied to the oxide film at the corner at the lower portion of the trench is large, and there is a feature that dielectric breakdown of the oxide film does not occur.
【００４４】また、本実施の形態における製造方法にお
いても、上述の実施の形態１と同様に、トレンチ部６を
形成する前の工程で、イオン注入と、活性化アニールを
行うことができるので、チャネルが形成されるトレンチ
部６の側壁に生じる注入の損傷、アニールによる表面の
荒れを低減することができ、高移動度で信頼性の高いチ
ャネルを形成することができる効果があり、素子特性を
向上できる。In the manufacturing method according to the present embodiment, as in the first embodiment, ion implantation and activation annealing can be performed in a step before forming trench 6. Damage due to implantation on the side wall of the trench portion 6 where the channel is formed and roughness of the surface due to annealing can be reduced, so that a channel having high mobility and high reliability can be formed. Can be improved.
【００４５】なお、図５は同じく実施の形態４の他の構
成を示すもので、トレンチ下部電界シールド領域１２の
幅が広く、ベース領域下部電界シールド領域１３がない
例をしめす。図４と同様に作製でき、また、同様な酸化
膜の絶縁破壊を抑制する効果がある。FIG. 5 shows another structure of the fourth embodiment, in which the width of the trench lower electric field shield region 12 is large and the base region lower electric field shield region 13 is not provided. It can be manufactured in the same manner as in FIG. 4 and has an effect of suppressing dielectric breakdown of a similar oxide film.
【００４６】実施の形態５．つぎに、本発明の別の一実
施の形態を示す。本実施の形態に示す半導体装置は、素
子構造、作製方法は、上記実施の形態１から４と同様で
あり、電界シールド効果により、ゲート酸化膜７の絶縁
破壊を抑制する効果をもっている。本実施の形態では、
チャネル９は、エッチングにより形成したＳｉＣ結晶の
１、１、２バー、０面のトレンチ部６の側壁に形成され
ている。チャネル移動度の結晶方位依存性より、基板表
面に形成されたチャネルより大きな移動度が得られ、チ
ャネル抵抗を低減できる。また同時に、電界シールドの
ためのｐ領域を備えているので、酸化膜の絶縁破壊が起
こりにくい。Embodiment 5 FIG. Next, another embodiment of the present invention will be described. The semiconductor device described in this embodiment has the same element structure and manufacturing method as those in the first to fourth embodiments, and has an effect of suppressing dielectric breakdown of the gate oxide film 7 by an electric field shielding effect. In the present embodiment,
The channel 9 is formed on the side wall of the trench 6 on the 1, 1, 2 bar and 0 planes of the SiC crystal formed by etching. Due to the crystal orientation dependence of the channel mobility, a mobility higher than that of the channel formed on the substrate surface can be obtained, and the channel resistance can be reduced. At the same time, since a p region for shielding the electric field is provided, dielectric breakdown of the oxide film hardly occurs.
【００４７】[0047]
【発明の効果】この発明は、ＳｉＣ半導体からなる基板
と、基板上に設けられ、低不純物のｎ型の導電性を有す
るｎ型層と、ｎ型層上に設けられ、ｐ型の導電性を有す
るｐ型ベース層と、ｐ型ベース層上に設けられ、高不純
物のｎ型の導電性を有するｎ型コンタクト層と、ｐ型ベ
ース層上の上記ｎ型コンタクト層が設けられていない領
域に設けられたｐ型コンタクト領域と、ｎ型コンタクト
層及び上記ｐ型ベース層を貫通してｎ型層にまで達する
深さを有する溝と、溝の底面及び側壁上に設けられたゲ
ート酸化膜と、ゲート酸化膜を介在させて上記溝の側壁
上に設けられたゲート電極と、ｎ型コンタクト層及び上
記ｐ型コンタクト領域に接触して設けられたソース電極
と、基板の下面に設けられたドレイン電極と、ゲート電
極に電圧が印加されたときに反転してｎ型コンタクト層
とｎ型層とを導通させるチャネル手段と、溝の下側のｎ
型層内に設けられ、高電圧遮断時のｎ型層からのゲート
酸化膜への電界の侵入を遮蔽する溝下部電界シールド手
段とを備えた半導体装置であり、溝の下部に電界シール
ドのためのｐ型領域を備えているので、ゲート酸化膜
部、特に、電界集中の起こりやすい溝下部の角のゲート
酸化膜の電界強度が緩和されるため、ゲート酸化膜の絶
縁破壊が生じないので、ＳｉＣ材料の絶縁特性に対応し
た、素子耐圧を得ることができる。According to the present invention, there is provided a substrate made of a SiC semiconductor, an n-type layer provided on the substrate and having low impurity n-type conductivity, and a p-type conductive film provided on the n-type layer. A n-type contact layer provided on the p-type base layer and having high impurity n-type conductivity; and a region on the p-type base layer where the n-type contact layer is not provided A groove having a depth reaching the n-type layer through the n-type contact layer and the p-type base layer, and a gate oxide film provided on the bottom and side walls of the groove A gate electrode provided on the side wall of the trench with a gate oxide film interposed therebetween, a source electrode provided in contact with the n-type contact layer and the p-type contact region, and provided on a lower surface of the substrate. Voltage is applied to the drain electrode and the gate electrode. And channel means for conducting the n-type contact layer and the n-type layer is inverted when the, the lower groove n
A lower part of the trench for shielding the electric field from entering the gate oxide film from the n-type layer when the high voltage is cut off. Since the p-type region is provided, the electric field strength of the gate oxide film portion, particularly, the gate oxide film at the corner under the groove where the electric field concentration is likely to occur is reduced, so that the dielectric breakdown of the gate oxide film does not occur. An element withstand voltage corresponding to the insulating characteristics of the SiC material can be obtained.
【００４８】また、溝下部電界シールド手段が、ｐ型の
導電性を有するｐ型領域から構成されているので、電界
の侵入を遮蔽する能力が高く、かつ、エッチングにより
溝を形成する前の工程で、イオン注入と活性化アニール
を行うことにより容易に形成できる。Further, since the electric field shielding means under the groove is composed of a p-type region having p-type conductivity, the ability to shield the invasion of the electric field is high, and the step before forming the groove by etching is performed. Then, it can be easily formed by performing ion implantation and activation annealing.
【００４９】また、ｐ型コンタクト領域の範囲におい
て、ｐ型ベース層の下面から略々垂直方向に向かって溝
の底面の深さより深い位置に至るまで延びて設けられ、
ｐ型ベース層の下方からのゲート酸化膜への電界の侵入
を遮蔽するベース層下部電界シールド手段をさらに備え
ているので、ｐ型ベース層の下方からの電界の侵入を遮
蔽できる。さらに、このシールド手段を設けたことによ
り、電界強度の最強の箇所がこのシールド手段の下部と
なるため、電界集中が起こりやすい溝の角のゲート酸化
膜の部分が電界強度の最強の箇所に接しないで分離され
るので、ゲート酸化膜の絶縁破壊をさらに防止すること
ができる。In the range of the p-type contact region, the lower surface of the p-type base layer extends substantially vertically to a position deeper than the depth of the bottom surface of the groove.
Since the semiconductor device further includes a base layer lower electric field shield means for shielding an electric field from entering the gate oxide film from below the p-type base layer, the electric field can be shielded from entering from below the p-type base layer. Further, by providing this shielding means, the portion having the strongest electric field strength is located below the shielding means, so that the portion of the gate oxide film at the corner of the groove where the electric field concentration tends to occur is in contact with the portion having the strongest electric field strength. Therefore, the gate oxide film can be further prevented from dielectric breakdown.
【００５０】また、ベース層下部電界シールド手段が、
ｐ型の導電性を有するｐ型領域から構成されているの
で、電界の侵入を遮蔽する能力が高く、かつ、イオン注
入を行うことにより容易に形成できる。Further, the electric field shielding means under the base layer includes:
Since it is composed of a p-type region having p-type conductivity, it has a high ability to block the invasion of an electric field and can be easily formed by ion implantation.
【００５１】また、溝下部電界シールド手段とベース層
下部電界シールド手段とを電気的に結合する電界シール
ド結合手段をさらに備えているので、電位的な浮遊した
領域が生じず、電荷の蓄積の片寄も生じないため、安定
なスイッチング動作とゲート酸化膜の高い信頼性が得ら
れる。Further, since the electric field shield coupling means for electrically coupling the electric field shield means under the groove and the electric field shield means under the base layer is further provided, no potential floating region is generated, and the electric charge is not accumulated. Therefore, stable switching operation and high reliability of the gate oxide film can be obtained.
【００５２】また、ｐ型ベース層とｎ型層との間に設け
られ、ｎ型層より高いｎ型の導電性を有する電流拡散層
をさらに備えているので、導通時には、電流経路は、ゲ
ート電圧印加により反転して形成されたチャネル近傍か
らのみではなく、ｎ型の電流拡散層全体から、ｎ型層を
経て流れるので、その抵抗は、電流拡散層がないときに
比べ低減される。Further, a current diffusion layer provided between the p-type base layer and the n-type layer and having an n-type conductivity higher than that of the n-type layer is further provided. Since the current flows not only from the vicinity of the channel formed by application of the voltage but also from the entire n-type current diffusion layer through the n-type layer, the resistance is reduced as compared with the case where there is no current diffusion layer.
【００５３】また、溝下部電界シールド手段が溝の幅よ
り広い幅を有しているので、溝下部の角の部分と電界強
度の大きい箇所とが接触せずに平面位置的にも分離され
るので、特に溝下部の角のゲート酸化膜に印加される電
界強度の緩和効果が大きく、酸化膜の絶縁破壊が生じな
い。Further, since the electric field shielding means at the bottom of the groove has a width wider than the width of the groove, the corner at the lower part of the groove and a portion having a large electric field strength are separated from each other even in a plane position without contact. Therefore, the effect of reducing the electric field intensity applied to the gate oxide film at the corner under the groove is particularly large, and the dielectric breakdown of the oxide film does not occur.
【００５４】また、チャネル手段が、溝の側壁から構成
されているので、チャネル手段はアニールによる表面の
損傷の影響を受けないので、高移動度で信頼性の高いチ
ャネルを形成することができ、チャネル抵抗を低減でき
る。Further, since the channel means is constituted by the side wall of the groove, the channel means is not affected by surface damage due to annealing, so that a channel having high mobility and high reliability can be formed. Channel resistance can be reduced.
【００５５】また、チャネル手段が、溝の上記側壁にお
けるＳｉＣ結晶の１、１、２バー、０面に設けられてい
るので、チャネル移動度の結晶方位依存性より、基板表
面に形成されたチャネルより大きな移動度が得られ、チ
ャネル抵抗を低減できる。Further, since the channel means is provided on the 1, 1, 2 bar and 0 planes of the SiC crystal on the side wall of the trench, the channel mobility formed on the substrate surface may be reduced due to the crystal orientation dependence of the channel mobility. Greater mobility can be obtained, and channel resistance can be reduced.
【００５６】また、この発明は、ＳｉＣ半導体からなる
基板上に、低不純物のｎ型の導電性を有するｎ型層を形
成する工程と、ｎ型層上に、ｐ型の導電性を有するｐ型
ベース層を形成する工程と、ｐ型ベース層上に、高不純
物のｎ型の導電性を有するｎ型コンタクト層を形成する
工程と、ｐ型ベース層上にｐ型コンタクト領域を形成す
る工程と、溝を形成する予定領域のｎ型層内に、高電圧
遮断時の上記ｎ型層からのゲート酸化膜への電界の侵入
をシールドさせるための溝下部電界シールド手段を形成
する工程と、ｎ型コンタクト層及びｐ型ベース層を貫通
してｎ型層内の溝下部電界シールド手段に達する深さを
有する溝を形成する工程と、溝の底面及び側壁上にゲー
ト酸化膜を形成する工程と、ゲート酸化膜を介在させて
溝の側壁上にゲート電極を形成する工程と、ｎ型コンタ
クト層及びｐ型コンタクト領域に接触させてソース電極
を形成する工程と、基板の下面にドレイン電極を形成す
る工程とを備えた半導体装置の製造方法であるので、溝
を形成する前の工程で、イオン注入と、活性化アニール
を行うことができるので、チャネルが形成される溝の側
壁に生じる注入の損傷、アニールによる表面の荒れを低
減することができ、高移動度で信頼性の高いチャネルを
形成することができ、素子特性を向上できる。Further, according to the present invention, a step of forming an n-type layer having low impurity n-type conductivity on a substrate made of a SiC semiconductor and a step of forming a p-type conductive layer having p-type conductivity on the n-type layer are provided. Forming a p-type base layer, forming an n-type contact layer having high impurity n-type conductivity on the p-type base layer, and forming a p-type contact region on the p-type base layer Forming a groove lower electric field shield means for shielding an electric field from entering the gate oxide film from the n-type layer at the time of high voltage interruption in the n-type layer in a region where a groove is to be formed; forming a groove having a depth penetrating the n-type contact layer and the p-type base layer and reaching the groove lower electric field shielding means in the n-type layer; and forming a gate oxide film on the bottom and side walls of the groove And the gate oxide film The method for manufacturing a semiconductor device includes a step of forming an electrode, a step of forming a source electrode in contact with an n-type contact layer and a p-type contact region, and a step of forming a drain electrode on a lower surface of a substrate. In the step before forming the groove, ion implantation and activation annealing can be performed, so that damage to the implantation caused on the side wall of the groove where the channel is formed and surface roughness due to annealing can be reduced. A highly reliable channel with high mobility can be formed, and element characteristics can be improved.
【００５７】また、ｐ型コンタクト領域の範囲におい
て、ｐ型ベース層の下面から、略々垂直方向に向かっ
て、溝の底面の深さより深い位置にかけて、ｐ型ベース
層の下部からのゲート酸化膜への電界の侵入をシールド
させるためのベース層下部電界シールド手段を形成する
工程をさらに備えているので、ベース層下部電界シール
ド手段により、ｐ型ベース層の下方からの電界の侵入を
遮蔽でき、さらに、このシールド手段を設けたことによ
り、電界強度の最強の箇所がこのシールド手段の下部と
なるため、電界集中が起こりやすい溝の角のゲート酸化
膜の部分が電界強度の最強の箇所に接しないで分離され
るので、ゲート酸化膜の絶縁破壊をさらに防止すること
ができる。In the range of the p-type contact region, the gate oxide film from the lower portion of the p-type base layer extends from the lower surface of the p-type base layer to a position substantially deeper than the depth of the bottom surface of the groove in a substantially vertical direction. The method further comprises a step of forming a base layer lower electric field shield means for shielding the intrusion of an electric field into the base layer, so that the electric field intrusion from below the p-type base layer can be shielded by the base layer lower electric field shield means, Further, by providing this shielding means, the portion having the strongest electric field strength is located below the shielding means, so that the portion of the gate oxide film at the corner of the groove where the electric field concentration tends to occur is in contact with the portion having the strongest electric field strength. Therefore, the gate oxide film can be further prevented from dielectric breakdown.
【００５８】また、溝下部電界シールド手段とベース層
下部電界シールド手段とを電気的に結合する電界シール
ド結合手段を形成する工程をさらに備えているので、電
位的な浮遊した領域が生じず、電荷の蓄積の片寄も生じ
ないため、安定なスイッチング動作とゲート酸化膜の高
い信頼性が得られる。Further, since the method further comprises the step of forming an electric field shield coupling means for electrically coupling the electric field shield means under the groove and the electric field shield means under the base layer, a potential floating region is not generated, and , And stable switching operation and high reliability of the gate oxide film can be obtained.
【００５９】また、ｐ型ベース層とｎ型層との間に、ｎ
型層より高いｎ型の導電性を有する電流拡散層を形成す
る工程をさらに備えているので、導通時には、電流経路
は、ゲート電圧印加により反転して形成されたチャネル
近傍からのみではなく、ｎ型の電流拡散層全体から、ｎ
型層を経て流れるので、その抵抗は、電流拡散層がない
ときに比べ低減される。Further, between the p-type base layer and the n-type layer, n
Since the method further includes a step of forming a current diffusion layer having n-type conductivity higher than that of the mold layer, during conduction, the current path is formed not only from the vicinity of the channel formed by inversion by applying a gate voltage, but also from the vicinity of n. From the entire current spreading layer of the type
Since it flows through the mold layer, its resistance is reduced compared to when there is no current spreading layer.
【００６０】また、溝下部電界シールド手段を形成する
際に、溝の幅より広い幅を有するように形成するので、
溝下部の角の部分と電界強度の大きい箇所とが接触せず
に平面位置的にも分離されるので、特に溝下部の角のゲ
ート酸化膜に印加される電界強度の緩和効果が大きく、
酸化膜の絶縁破壊が生じない。Further, when the electric field shielding means under the groove is formed, it is formed so as to have a width wider than the width of the groove.
Since the corner portion at the bottom of the groove and the portion having a large electric field strength are separated from each other even in a planar position without contact, the effect of relaxing the electric field intensity applied to the gate oxide film at the corner at the bottom of the groove is particularly large,
No dielectric breakdown of the oxide film occurs.
【図１】 本発明の実施の形態１によるトレンチゲート
型のＳｉＣ半導体ＭＯＳ電界効果パワートランジスタ半
導体装置の断面図である。FIG. 1 is a sectional view of a trench gate type SiC semiconductor MOS field effect power transistor semiconductor device according to a first embodiment of the present invention.
【図２】 本発明の実施の形態２によるトレンチゲート
型のＳｉＣ半導体ＭＯＳ電界効果パワートランジスタ半
導体装置の断面図である。FIG. 2 is a sectional view of a trench gate type SiC semiconductor MOS field effect power transistor semiconductor device according to a second embodiment of the present invention.
【図３】 本発明の実施の形態３によるトレンチゲート
型のＳｉＣ半導体ＭＯＳ電界効果パワートランジスタ半
導体装置の断面図である。FIG. 3 is a sectional view of a trench gate type SiC semiconductor MOS field effect power transistor semiconductor device according to a third embodiment of the present invention.
【図４】 本発明の実施の形態４によるトレンチゲート
型のＳｉＣ半導体ＭＯＳ電界効果パワートランジスタ半
導体装置の断面図である。FIG. 4 is a sectional view of a trench gate type SiC semiconductor MOS field effect power transistor semiconductor device according to a fourth embodiment of the present invention.
【図５】 本発明の実施の形態４による他のトレンチゲ
ート型のＳｉＣ半導体ＭＯＳ電界効果パワートランジス
タ半導体装置の断面図である。FIG. 5 is a sectional view of another trench gate type SiC semiconductor MOS field effect power transistor semiconductor device according to a fourth embodiment of the present invention.
【図６】 従来のトレンチゲート型のＳｉＣ半導体ＭＯ
Ｓ電界効果パワートランジスタ半導体装置の断面図であ
る。FIG. 6 shows a conventional trench gate type SiC semiconductor MO.
It is sectional drawing of an S field effect power transistor semiconductor device.
【図７】 従来のウエハー表面にＭＯＳチャネルを持つ
構造のＳｉＣ半導体ＭＯＳ電界効果パワートランジスタ
半導体装置の断面図である。FIG. 7 is a cross-sectional view of a conventional SiC semiconductor MOS field effect power transistor semiconductor device having a MOS channel on a wafer surface.
１ ｎ型のＳｉＣ基板、２ ドリフト領域、３ ベース
領域、４ ｎコンタクト領域、５ ｐコンタクト領域、
６ トレンチ部、７ ゲート酸化膜、８ ゲート電極、
９ チャネル部、１０ ソース電極、１１ ドレイン電
極、１２ トレンチ下部電界シールド領域、１３ ベー
ス領域下部電界シールド領域、１４ 電界シールド結合
領域、１５ 電流拡散層。1 n-type SiC substrate, 2 drift region, 3 base region, 4 n contact region, 5 p contact region,
6 trench part, 7 gate oxide film, 8 gate electrode,
9 channel part, 10 source electrode, 11 drain electrode, 12 trench lower electric field shield area, 13 base area lower electric field shield area, 14 electric field shield coupling area, 15 current diffusion layer.
フロントページの続き (72)発明者 樽井 陽一郎 東京都千代田区丸の内二丁目２番３号 三 菱電機株式会社内 (72)発明者 大塚 健一 東京都千代田区丸の内二丁目２番３号 三 菱電機株式会社内Continued on the front page (72) Inventor Yoichiro Tarui 2-3-2 Marunouchi, Chiyoda-ku, Tokyo Mitsubishi Electric Corporation (72) Inventor Kenichi Otsuka 2-3-2 Marunouchi, Chiyoda-ku, Tokyo Mitsubishi Electric Co., Ltd. In company
Claims (14)
るｎ型層と、 上記ｎ型層上に設けられ、ｐ型の導電性を有するｐ型ベ
ース層と、 上記ｐ型ベース層上に設けられ、高不純物のｎ型の導電
性を有するｎ型コンタクト層と、 上記ｐ型ベース層上の上記ｎ型コンタクト層が設けられ
ていない領域に設けられたｐ型コンタクト領域と、 上記ｎ型コンタクト層及び上記ｐ型ベース層を貫通して
上記ｎ型層にまで達する深さを有する溝と、 上記溝の底面及び側壁上に設けられたゲート酸化膜と、 上記ゲート酸化膜を介在させて上記溝の側壁上に設けら
れたゲート電極と、 上記ｎ型コンタクト層及び上記ｐ型コンタクト領域に接
触して設けられたソース電極と、 上記基板の下面に設けられたドレイン電極と、 上記ゲート電極に電圧が印加されたときに反転して上記
ｎ型コンタクト層と上記ｎ型層とを導通させるチャネル
手段と、 上記溝の下側の上記ｎ型層内に設けられ、高電圧遮断時
の上記ｎ型層からの上記ゲート酸化膜への電界の侵入を
遮蔽する溝下部電界シールド手段とを備えたことを特徴
とする半導体装置。1. A substrate made of a silicon carbide semiconductor, an n-type layer provided on the substrate and having low impurity n-type conductivity, and a p-type conductivity provided on the n-type layer. A p-type base layer, an n-type contact layer provided on the p-type base layer and having high impurity n-type conductivity, and the n-type contact layer on the p-type base layer is not provided. A p-type contact region provided in a region; a groove having a depth reaching the n-type layer through the n-type contact layer and the p-type base layer; and a groove provided on a bottom surface and a side wall of the groove. A gate oxide film, a gate electrode provided on a side wall of the trench with the gate oxide film interposed, a source electrode provided in contact with the n-type contact layer and the p-type contact region, Dray provided on the lower surface of the substrate Channel means for inverting when a voltage is applied to the gate electrode to conduct the n-type contact layer and the n-type layer, and provided in the n-type layer below the groove. And a lower-field electric field shielding means for shielding an electric field from entering the gate oxide film from the n-type layer when a high voltage is cut off.
導電性を有するｐ型領域から構成されていることを特徴
とする請求項１記載の半導体装置。2. The semiconductor device according to claim 1, wherein the electric field shielding means under the groove is formed of a p-type region having p-type conductivity.
て、上記ｐ型ベース層の下面から略々垂直方向に向かっ
て上記溝の底面の深さより深い位置に至るまで延びて設
けられ、上記ｐ型ベース層の下方からの上記ゲート酸化
膜への電界の侵入を遮蔽するベース層下部電界シールド
手段をさらに備えたことを特徴とする請求項１または２
に記載の半導体装置。3. The p-type base region is provided so as to extend from a lower surface of the p-type base layer to a position substantially deeper than a depth of a bottom surface of the groove in a range of the p-type contact region. 3. The device according to claim 1, further comprising a base layer lower electric field shielding means for shielding an electric field from entering the gate oxide film from under the layer.
3. The semiconductor device according to claim 1.
ｐ型の導電性を有するｐ型領域から構成されていること
を特徴とする請求項３に記載の半導体装置。4. The electric field shielding means under the base layer,
4. The semiconductor device according to claim 3, comprising a p-type region having p-type conductivity.
ス層下部電界シールド手段とを電気的に結合する電界シ
ールド結合手段をさらに備えたことを特徴とうする請求
項３または４に記載の半導体装置。5. The semiconductor device according to claim 3, further comprising electric field shield coupling means for electrically coupling said electric field shield means under said groove and said electric field shield means under said base layer.
設けられ、上記ｎ型層より高いｎ型の導電性を有する電
流拡散層をさらに備えたことを特徴とする請求項１ない
し５のいずれかに記載の半導体装置。6. The semiconductor device according to claim 1, further comprising a current diffusion layer provided between the p-type base layer and the n-type layer and having a higher n-type conductivity than the n-type layer. 6. The semiconductor device according to any one of items 5 to 5.
の幅より広い幅を有していることを特徴とする請求項１
ないし６のいずれかに記載の半導体装置。7. The device according to claim 1, wherein the electric field shield means below the groove has a width larger than the width of the groove.
7. The semiconductor device according to any one of items 6 to 6.
から構成されていることを特徴とする請求項１ないし７
のいずれかに記載の半導体装置。8. The apparatus according to claim 1, wherein said channel means comprises said side wall of said groove.
The semiconductor device according to any one of the above.
におけるＳｉＣ結晶の１、１、２バー、０面に設けられ
ていることを特徴とする請求項１ないし７のいずれかに
記載の半導体装置。9. The semiconductor according to claim 1, wherein the channel means is provided on the 1, 1, 2 bar, and 0 planes of the SiC crystal on the side wall of the groove. apparatus.
不純物のｎ型の導電性を有するｎ型層を形成する工程
と、 上記ｎ型層上に、ｐ型の導電性を有するｐ型ベース層を
形成する工程と、 上記ｐ型ベース層上に、高不純物のｎ型の導電性を有す
るｎ型コンタクト層を形成する工程と、 上記ｐ型ベース層上にｐ型コンタクト領域を形成する工
程と、 溝を形成する予定領域の上記ｎ型層内に、高電圧遮断時
の上記ｎ型層からのゲート酸化膜への電界の侵入をシー
ルドさせるための溝下部電界シールド手段を形成する工
程と、 上記ｎ型コンタクト層及び上記ｐ型ベース層を貫通して
上記ｎ型層内の上記溝下部電界シールド手段に達する深
さを有する溝を形成する工程と、 上記溝の底面及び側壁上にゲート酸化膜を形成する工程
と、 上記ゲート酸化膜を介在させて上記溝の側壁上にゲート
電極を形成する工程と、上記ｎ型コンタクト層及び上記
ｐ型コンタクト領域に接触させてソース電極を形成する
工程と、 上記基板の下面にドレイン電極を形成する工程と、 を備えたことを特徴とする半導体装置の製造方法。10. A step of forming an n-type layer having low impurity n-type conductivity on a substrate made of a silicon carbide semiconductor; and forming a p-type base having p-type conductivity on the n-type layer. Forming a layer; forming an n-type contact layer having high impurity n-type conductivity on the p-type base layer; and forming a p-type contact region on the p-type base layer. Forming, in the n-type layer in a region where a groove is to be formed, a groove lower electric field shield means for shielding an electric field from entering the gate oxide film from the n-type layer at the time of high voltage cutoff; Forming a groove having a depth penetrating the n-type contact layer and the p-type base layer and reaching the groove lower electric field shielding means in the n-type layer; and a gate on a bottom surface and a side wall of the groove. A step of forming an oxide film; Forming a gate electrode on the side wall of the trench with a film interposed therebetween, forming a source electrode in contact with the n-type contact layer and the p-type contact region, and forming a drain electrode on the lower surface of the substrate. Forming a semiconductor device.
て、上記ｐ型ベース層の下面から、略々垂直方向に向か
って、上記溝の底面の深さより深い位置にかけて、上記
ｐ型ベース層の下部からの上記ゲート酸化膜への電界の
侵入をシールドさせるためのベース層下部電界シールド
手段を形成する工程をさらに備えたことを特徴とする請
求項１０に記載の半導体装置の製造方法。11. In a range of the p-type contact region, from a lower surface of the p-type base layer to a position substantially deeper than a depth of a bottom surface of the groove in a direction substantially perpendicular to the lower portion of the p-type base layer. 11. The method of manufacturing a semiconductor device according to claim 10, further comprising the step of: forming a base layer lower electric field shield means for shielding the intrusion of an electric field into the gate oxide film.
ース層下部電界シールド手段とを電気的に結合する電界
シールド結合手段を形成する工程をさらに備えたことを
特徴とする請求項１１に記載の半導体装置の製造方法。12. The semiconductor according to claim 11, further comprising a step of forming an electric field shield coupling means for electrically coupling the electric field shield means under the groove and the electric field shield means under the base layer. Device manufacturing method.
に、上記ｎ型層より高いｎ型の導電性を有する電流拡散
層を形成する工程をさらに備えたことを特徴とする請求
項１０ないし１２のいずれかに記載の半導体装置の製造
方法。13. The method according to claim 1, further comprising the step of forming a current diffusion layer having a higher n-type conductivity than the n-type layer between the p-type base layer and the n-type layer. Item 13. A method for manufacturing a semiconductor device according to any one of Items 10 to 12.
る際に、上記溝の幅より広い幅を有するように形成する
ことを特徴とする請求項１０ないし１３のいずれかに記
載の半導体装置の製造方法。14. The method of manufacturing a semiconductor device according to claim 10, wherein when forming the electric field shielding means under the groove, the electric field shielding means is formed to have a width wider than the width of the groove. Method.
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|---|---|---|---|
| JP2000072298A JP4738562B2 (en) | 2000-03-15 | 2000-03-15 | Manufacturing method of semiconductor device |
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| JP4738562B2 JP4738562B2 (en) | 2011-08-03 |
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Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5658267A (en) * | 1979-10-17 | 1981-05-21 | Nippon Telegr & Teleph Corp <Ntt> | Insulated gate type field-effect transistor |
| JPH06224437A (en) * | 1992-07-24 | 1994-08-12 | Siliconix Inc | Field-effect transistor and manufacture thereof |
| JPH07131016A (en) * | 1993-09-10 | 1995-05-19 | Hitachi Ltd | Fet transistor and fabrication thereof |
| JPH08316479A (en) * | 1995-03-14 | 1996-11-29 | Mitsubishi Electric Corp | Insulated-gate type semiconductor device and manufacture thereof |
| JPH1098188A (en) * | 1996-08-01 | 1998-04-14 | Kansai Electric Power Co Inc:The | Insulated gate semiconductor device |
| JPH10209432A (en) * | 1997-01-21 | 1998-08-07 | Mitel Semiconductor Ltd | Improvement in semiconductor device |
| WO1998035390A1 (en) * | 1997-02-07 | 1998-08-13 | Cooper James Albert Jr | Structure for increasing the maximum voltage of silicon carbide power transistors |
| JPH10308512A (en) * | 1997-03-05 | 1998-11-17 | Denso Corp | Silicon carbide semiconductor device |
| JPH11251573A (en) * | 1998-02-26 | 1999-09-17 | Toyota Central Res & Dev Lab Inc | Semiconductor device |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5168331A (en) * | 1991-01-31 | 1992-12-01 | Siliconix Incorporated | Power metal-oxide-semiconductor field effect transistor |
-
2000
- 2000-03-15 JP JP2000072298A patent/JP4738562B2/en not_active Expired - Lifetime
Patent Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5658267A (en) * | 1979-10-17 | 1981-05-21 | Nippon Telegr & Teleph Corp <Ntt> | Insulated gate type field-effect transistor |
| JPH06224437A (en) * | 1992-07-24 | 1994-08-12 | Siliconix Inc | Field-effect transistor and manufacture thereof |
| JPH07131016A (en) * | 1993-09-10 | 1995-05-19 | Hitachi Ltd | Fet transistor and fabrication thereof |
| JPH08316479A (en) * | 1995-03-14 | 1996-11-29 | Mitsubishi Electric Corp | Insulated-gate type semiconductor device and manufacture thereof |
| JPH1098188A (en) * | 1996-08-01 | 1998-04-14 | Kansai Electric Power Co Inc:The | Insulated gate semiconductor device |
| JPH10209432A (en) * | 1997-01-21 | 1998-08-07 | Mitel Semiconductor Ltd | Improvement in semiconductor device |
| WO1998035390A1 (en) * | 1997-02-07 | 1998-08-13 | Cooper James Albert Jr | Structure for increasing the maximum voltage of silicon carbide power transistors |
| JPH10308512A (en) * | 1997-03-05 | 1998-11-17 | Denso Corp | Silicon carbide semiconductor device |
| JPH11251573A (en) * | 1998-02-26 | 1999-09-17 | Toyota Central Res & Dev Lab Inc | Semiconductor device |
Cited By (127)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
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| US7470953B2 (en) | 2003-10-08 | 2008-12-30 | Toyota Jidosha Kabushiki Kaisha | Insulated gate type semiconductor device and manufacturing method thereof |
| JP4538211B2 (en) * | 2003-10-08 | 2010-09-08 | トヨタ自動車株式会社 | Insulated gate semiconductor device and manufacturing method thereof |
| EP1748492A1 (en) * | 2004-03-29 | 2007-01-31 | Shindengen Electric Manufacturing Co., Ltd. | Semiconductor device and semiconductor device manufacturing method |
| EP1748492A4 (en) * | 2004-03-29 | 2009-11-04 | Shindengen Electric Mfg | Semiconductor device and semiconductor device manufacturing method |
| JP2008071896A (en) * | 2006-09-13 | 2008-03-27 | Nippon Steel Corp | Metal-insulating film-silicon carbide semiconductor structure |
| JP2008078174A (en) * | 2006-09-19 | 2008-04-03 | Fuji Electric Holdings Co Ltd | Trench gate type silicon carbide semiconductor device |
| JP2008147232A (en) * | 2006-12-06 | 2008-06-26 | Mitsubishi Electric Corp | Silicon carbide semiconductor device and manufacturing method therefor |
| JP2008235546A (en) * | 2007-03-20 | 2008-10-02 | Denso Corp | Silicon carbide semiconductor device and manufacturing method therefor |
| US8022414B2 (en) | 2007-03-20 | 2011-09-20 | Denso Corporation | Silicon carbide semiconductor device, and method of manufacturing the same |
| DE102008000660B4 (en) * | 2007-03-20 | 2014-06-05 | Denso Corporation | The silicon carbide semiconductor device |
| US7825449B2 (en) | 2007-11-06 | 2010-11-02 | Denso Corporation | Silicon carbide semiconductor device and related manufacturing method |
| DE102008055689B4 (en) * | 2007-11-06 | 2016-07-21 | Denso Corporation | Silicon carbide semiconductor device and manufacturing method thereof |
| JP2009117593A (en) * | 2007-11-06 | 2009-05-28 | Denso Corp | Silicon carbide semiconductor apparatus and method of manufacturing the same |
| JP2009117649A (en) * | 2007-11-07 | 2009-05-28 | Fuji Electric Device Technology Co Ltd | Semiconductor device |
| EP2068363A2 (en) * | 2007-12-07 | 2009-06-10 | Cree, Inc. | Trench-gate MISFET |
| JP2013065907A (en) * | 2007-12-07 | 2013-04-11 | Cree Inc | Transistor with a-face conductive channel and trench protecting well region |
| EP2615642A1 (en) * | 2007-12-07 | 2013-07-17 | Cree, Inc. | Trench-gate MISFET |
| US8211770B2 (en) | 2007-12-07 | 2012-07-03 | Cree, Inc. | Transistor with A-face conductive channel and trench protecting well region |
| US9064710B2 (en) | 2007-12-07 | 2015-06-23 | Cree, Inc. | Transistor with A-face conductive channel and trench protecting well region |
| JP2009141363A (en) * | 2007-12-07 | 2009-06-25 | Cree Inc | Transistor with a-face conductive channel and trench protecting well region |
| DE102008063128A1 (en) | 2007-12-26 | 2009-07-02 | Denso Corporation, Kariya | SiC semiconductor device with a bottom layer and method for its production |
| US7851854B2 (en) | 2007-12-26 | 2010-12-14 | Denso Corporation | SiC semiconductor device having bottom layer and method for manufacturing the same |
| KR101015445B1 (en) * | 2008-02-13 | 2011-02-18 | 가부시키가이샤 덴소 | Silicon carbide semiconductor device including deep layer |
| US8193564B2 (en) | 2008-02-13 | 2012-06-05 | Denso Corporation | Silicon carbide semiconductor device including deep layer |
| JP2009194065A (en) * | 2008-02-13 | 2009-08-27 | Denso Corp | Silicon carbide semiconductor device and method of manufacturing the same |
| EP2091083A3 (en) * | 2008-02-13 | 2009-10-14 | Denso Corporation | Silicon carbide semiconductor device including a deep layer |
| US8283721B2 (en) | 2008-03-26 | 2012-10-09 | Rohm Co., Ltd. | Semiconductor device, and method for manufacturing the same |
| US11127851B2 (en) | 2008-03-26 | 2021-09-21 | Rohm Co., Ltd. | Semiconductor device, and method for manufacturing the same |
| US10290733B2 (en) | 2008-03-26 | 2019-05-14 | Rohm Co., Ltd. | Semiconductor device, and method for manufacturing the same |
| EP4297097A3 (en) * | 2008-03-26 | 2024-04-03 | Rohm Co., Ltd. | Semiconductor device, and method for manufacturing the same |
| EP4095928A1 (en) * | 2008-03-26 | 2022-11-30 | Rohm Co., Ltd. | Semiconductor device and method for manufacturing the same |
| JP2009260253A (en) * | 2008-03-26 | 2009-11-05 | Rohm Co Ltd | Semiconductor device and method for manufacturing the same |
| US9166038B2 (en) | 2008-03-26 | 2015-10-20 | Rohm Co., Ltd. | Semiconductor device, and method for manufacturing the same |
| US10686067B2 (en) | 2008-03-26 | 2020-06-16 | Rohm Co., Ltd. | Semiconductor device, and method for manufacturing the same |
| US12009420B2 (en) | 2008-03-26 | 2024-06-11 | Rohm Co., Ltd. | Semiconductor device, and method for manufacturing the same |
| US9496387B2 (en) | 2008-03-26 | 2016-11-15 | Rohm Co., Ltd. | Semiconductor device, and method for manufacturing the same |
| US12034073B2 (en) | 2008-03-26 | 2024-07-09 | Rohm Co., Ltd. | Semiconductor device, and method for manufacturing the same |
| WO2009119735A1 (en) * | 2008-03-26 | 2009-10-01 | ローム株式会社 | Semiconductor device, and method for manufacturing the same |
| JP4640436B2 (en) * | 2008-04-14 | 2011-03-02 | 株式会社デンソー | Method for manufacturing silicon carbide semiconductor device |
| JP2009259896A (en) * | 2008-04-14 | 2009-11-05 | Denso Corp | Method for manufacturing silicon carbide semiconductor device |
| JP2010114152A (en) * | 2008-11-04 | 2010-05-20 | Toyota Motor Corp | Semiconductor device, and method of manufacturing the same |
| JP2010258386A (en) * | 2009-04-28 | 2010-11-11 | Fuji Electric Systems Co Ltd | Silicon carbide semiconductor device, and method of manufacturing the same |
| JP2011253837A (en) * | 2010-05-31 | 2011-12-15 | Denso Corp | Silicon carbide semiconductor device and method for manufacturing the same |
| US8896058B2 (en) | 2010-11-08 | 2014-11-25 | Sumitomo Electric Industries, Ltd. | Semiconductor device and method for producing same |
| JP2012104567A (en) * | 2010-11-08 | 2012-05-31 | Sumitomo Electric Ind Ltd | Semiconductor device and method of manufacturing the same |
| WO2012063578A1 (en) * | 2010-11-08 | 2012-05-18 | 住友電気工業株式会社 | Semiconductor device and method for producing same |
| JP2013098315A (en) * | 2011-10-31 | 2013-05-20 | Toyota Motor Corp | Switching element and method of manufacturing the same |
| CN103151376A (en) * | 2011-12-07 | 2013-06-12 | Nxp股份有限公司 | Trench-gate RESURF semiconductor device and manufacturing method |
| US9735254B2 (en) | 2011-12-07 | 2017-08-15 | Nexperia B.V. | Trench-gate RESURF semiconductor device and manufacturing method |
| US9006822B2 (en) | 2011-12-07 | 2015-04-14 | Nxp B.V. | Trench-gate RESURF semiconductor device and manufacturing method |
| US20130146967A1 (en) * | 2011-12-07 | 2013-06-13 | Nxp B. V. | Trench-Gate Resurf Semiconductor Device and Manufacturing Method |
| EP2602829A1 (en) * | 2011-12-07 | 2013-06-12 | Nxp B.V. | Trench-gate resurf semiconductor device and manufacturing method |
| US9209294B1 (en) | 2012-02-10 | 2015-12-08 | Panasonic Intellectual Property Management Co., Ltd. | Semiconductor device and method for manufacturing same |
| US9673288B2 (en) | 2012-04-19 | 2017-06-06 | Denso Corporation | Silicon carbide semiconductor device including conductivity layer in trench |
| US9337298B2 (en) | 2012-06-14 | 2016-05-10 | Denso Corporation | Silicon carbide semiconductor device and method for producing the same |
| EP2863417A4 (en) * | 2012-06-14 | 2016-03-09 | Denso Corp | Silicon carbide semiconductor device and method for producing same |
| CN104380442A (en) * | 2012-06-14 | 2015-02-25 | 株式会社电装 | Silicon carbide semiconductor device and method for producing same |
| US9515160B2 (en) | 2012-06-14 | 2016-12-06 | Denso Corporation | Silicon carbide semiconductor device and method for producing the same |
| JP7241848B2 (en) | 2013-02-05 | 2023-03-17 | 三菱電機株式会社 | Insulated gate type silicon carbide semiconductor device |
| CN109755321A (en) * | 2013-02-05 | 2019-05-14 | 三菱电机株式会社 | Insulated-gate type manufacturing silicon carbide semiconductor device and its manufacturing method |
| US10510843B2 (en) | 2013-02-05 | 2019-12-17 | Mitsubishi Electric Corporation | Insulated gate silicon carbide semiconductor device and method for manufacturing same |
| JP2020038995A (en) * | 2013-02-05 | 2020-03-12 | 三菱電機株式会社 | Insulation gate type silicon carbide semiconductor device and manufacturing method therefor |
| JP2022010335A (en) * | 2013-02-05 | 2022-01-14 | 三菱電機株式会社 | Insulated gate type silicon carbide semiconductor device |
| US9741797B2 (en) | 2013-02-05 | 2017-08-22 | Mitsubishi Electric Corporation | Insulated gate silicon carbide semiconductor device and method for manufacturing same |
| JP7105752B2 (en) | 2013-02-05 | 2022-07-25 | 三菱電機株式会社 | Insulated gate type silicon carbide semiconductor device |
| EP2973723A4 (en) * | 2013-03-13 | 2016-11-09 | Cree Inc | Field effect transistor devices with protective regions |
| US10784338B2 (en) | 2013-03-13 | 2020-09-22 | Cree, Inc. | Field effect transistor devices with buried well protection regions |
| US10134834B2 (en) | 2013-03-13 | 2018-11-20 | Cree, Inc. | Field effect transistor devices with buried well protection regions |
| US9570585B2 (en) | 2013-03-13 | 2017-02-14 | Cree, Inc. | Field effect transistor devices with buried well protection regions |
| US9349856B2 (en) | 2013-03-26 | 2016-05-24 | Toyoda Gosei Co., Ltd. | Semiconductor device including first interface and second interface as an upper surface of a convex protruded from first interface and manufacturing device thereof |
| US9318600B2 (en) | 2013-04-16 | 2016-04-19 | Panasonic Intellectual Property Management Co., Ltd. | Silicon carbide semiconductor device and method for manufacturing same |
| JPWO2014171048A1 (en) * | 2013-04-16 | 2017-02-16 | パナソニックＩｐマネジメント株式会社 | Method for manufacturing silicon carbide semiconductor device |
| JP5834179B2 (en) * | 2013-04-16 | 2015-12-16 | パナソニックＩｐマネジメント株式会社 | Method for manufacturing silicon carbide semiconductor device |
| JP2014241368A (en) * | 2013-06-12 | 2014-12-25 | 住友電気工業株式会社 | Silicon carbide semiconductor device |
| WO2014199748A1 (en) * | 2013-06-12 | 2014-12-18 | 住友電気工業株式会社 | Silicon carbide semiconductor device |
| WO2015012009A1 (en) * | 2013-07-26 | 2015-01-29 | 住友電気工業株式会社 | Silicon carbide semiconductor device and method for manufacturing same |
| US10192960B2 (en) | 2013-07-26 | 2019-01-29 | Sumitomo Electric Industries, Ltd. | Silicon carbide semiconductor device and method for manufacturing same |
| JP2015026727A (en) * | 2013-07-26 | 2015-02-05 | 住友電気工業株式会社 | Silicon carbide semiconductor device and manufacturing method for the same |
| US9825164B2 (en) | 2013-08-01 | 2017-11-21 | Mitsubishi Electric Corporation | Silicon carbide semiconductor device and manufacturing method for same |
| WO2015049838A1 (en) * | 2013-10-02 | 2015-04-09 | 株式会社デンソー | Silicon carbide semiconductor device |
| US9647108B2 (en) | 2013-10-02 | 2017-05-09 | Denso Corporation | Silicon carbide semiconductor device |
| JP2015072999A (en) * | 2013-10-02 | 2015-04-16 | 株式会社デンソー | Silicon carbide semiconductor device |
| JP2015082544A (en) * | 2013-10-22 | 2015-04-27 | ルネサスエレクトロニクス株式会社 | Semiconductor device and method of manufacturing the same |
| JP2015141919A (en) * | 2014-01-27 | 2015-08-03 | トヨタ自動車株式会社 | semiconductor device |
| WO2015177914A1 (en) * | 2014-05-23 | 2015-11-26 | 株式会社日立製作所 | Semiconductor device, semiconductor device manufacturing method, power conversion device, three-phase motor system, automobile, and train car |
| JPWO2015177914A1 (en) * | 2014-05-23 | 2017-04-20 | 株式会社日立製作所 | Semiconductor device, semiconductor device manufacturing method, power conversion device, three-phase motor system, automobile, and railway vehicle |
| JPWO2016002766A1 (en) * | 2014-06-30 | 2017-04-27 | 住友電気工業株式会社 | Silicon carbide semiconductor device and manufacturing method thereof |
| WO2016116998A1 (en) * | 2015-01-19 | 2016-07-28 | 株式会社日立製作所 | Semiconductor device, method for manufacturing same, power conversion device, three-phase motor system, automobile, and railway carriage |
| US10074741B2 (en) | 2015-03-03 | 2018-09-11 | Infineon Technologies Ag | Semiconductor device with trench gate structure including a gate electrode and a contact structure for a diode region |
| JP2016163049A (en) * | 2015-03-03 | 2016-09-05 | インフィネオン テクノロジーズ アクチエンゲゼルシャフトＩｎｆｉｎｅｏｎ Ｔｅｃｈｎｏｌｏｇｉｅｓ ＡＧ | Semiconductor device including trench structure including a gate electrode for diode region and contact structure |
| US10734514B2 (en) | 2015-03-03 | 2020-08-04 | Infineon Technologies Ag | Semiconductor device with trench gate structure including a gate electrode and a contact structure for a diode region |
| JPWO2016157606A1 (en) * | 2015-03-30 | 2017-09-14 | 三菱電機株式会社 | Silicon carbide semiconductor device and manufacturing method thereof |
| US10157986B2 (en) | 2015-03-30 | 2018-12-18 | Mitsubishi Electric Corporation | Silicon carbide semiconductor device and method for manufacturing same |
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| US10199493B2 (en) | 2015-10-16 | 2019-02-05 | Fuji Electric Co., Ltd. | Semiconductor device and method of manufacturing semiconductor device |
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| US10403749B2 (en) | 2015-10-16 | 2019-09-03 | Fuji Electric Co., Ltd. | Method of manufacturing semiconductor device |
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| CN108352402B (en) * | 2015-10-16 | 2020-12-18 | 富士电机株式会社 | Semiconductor device and method for manufacturing semiconductor device |
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