JP2001094098A - Silicon carbide semiconductor device and fabrication method thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To control the concentration profile of a base region such that an avalanche breakdown position can be formed accurately. SOLUTION: C(carbon) ions are implanted, as inert ion species, into the surface layer part of an n- epi layer 2 and B ions are implanted into a region for implanting C ions at a specified concentration ratio to C ions and then it is activated by heat treatment while suppressing diffusion of B thus forming a heavily doped deep base layer 30. Since inert C ion species enter voids of carbon site to eliminate the voids, diffusion of B is suppressed and a stepwise junction of the deep base layer 30 and the n- epi layer 2 is formed. Consequently, breakdown strength is lowered at the junction and avalanche breakdown takes place at that part.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a silicon carbide semiconductor device having a base region and a method of manufacturing the same, and is particularly suitable for use in a vertical MOSFET or a horizontal MOSFET.

[0002]

2. Description of the Related Art FIG. 14 shows a sectional structure of a conventional vertical MOSFET. As shown in FIG. 14, a horizontal MO using Si
In a semiconductor device such as an SFET or a vertical MOSFET, a second p-well layer 130 is formed on a predetermined region of the first p-well layer 103 so as to extract surge voltage energy applied to the n-type drain layer 101. Then, a method of causing avalanche breakdown at the bottom of the second well layer 130 is used.

There are two conditions for causing avalanche breakdown in this part. One of them is
The second p-well layer 103 formed deeply, the distance between the n ⁺ -type substrate shorter than the distance between the first well layer 103 and the n ⁺ -type substrate 101, the second p-well layer when the surge voltage is applied The depletion layer extending from the first p-well layer 103 is made to reach the substrate before the depletion layer extending from the first p-well layer 103 (reach-through), thereby increasing the electric field intensity at the bottom of the second well layer 130, and This is a method of causing avalanche breakdown before the bottom of the avalanche.

Another is that the withstand voltage is reduced by increasing the concentration of the second p-well layer 130 higher than the concentration of the first p-well layer 103 and making the junction of the pn diode a high-concentration junction. Is the way. It is known that the concentration profile of Si can be easily controlled by thermal diffusion, and it is also known that the distribution has a substantially Gaussian distribution shape. Both of the above two methods could be easily used by controlling the profile shape obtained by ion implantation and diffusion.

[0005]

SUMMARY OF THE INVENTION The present inventors attempted to apply the above method to silicon carbide (SiC) by ion implantation of B (boron) as a well-forming dopant because of the advantage that ion implantation damage is small. About 1600 ° C
Was subjected to activation heat treatment, and the diffusion was examined. As a result, about 10
It has been found that a concentration of ¹⁷ cm ^-3 causes a tail-diffusion on the order of 1 to ³ μm.

[0006] From this result, if the first method used for Si is to be used, it is difficult to use the first method used for general Si.
In the ion implantation apparatus of not more than 00 keV, the depth immediately after the ion implantation is 1 μm or less even if the ion implantation is performed at the maximum acceleration voltage, but the diffusion amount is larger, so that the first well layer 103 and the second It is clear that it is difficult to make a difference in the depth of the well layer 130, and control is difficult.

When the second method is used, a low-concentration tail is already formed at the time of the activation heat treatment.
It is difficult to make a difference in the junction concentration at the junction between the second well layer 130 and the second well layer 130, which proved to be difficult. Therefore, a new concentration profile control method applicable to SiC is desired.

In view of the above, it is a first object of the present invention to control a density profile of a base region so that an avalanche breakdown position can be accurately formed.

It is a second object of the present invention to improve a breakdown voltage by causing avalanche breakdown at a desired position.

[0010]

In order to achieve the above object, according to the first aspect of the present invention, the first base region is formed by thermal diffusion of a second conductivity type impurity. The junction with the semiconductor layer (2) forms an inclined junction in which the concentration distribution of the second conductivity type impurity gradually changes,
Inactive ion species are implanted in the second base region (30), and the junction between the second base region and the semiconductor layer is formed at a step where the concentration distribution of the second conductivity type impurity changes sharply. It is characterized by forming a mold.

As described above, since the diffusion of the second conductivity type impurity is suppressed in the second base region, which is the region into which the inert ion species is implanted, the second conductivity type is formed at the junction with the semiconductor layer. A stair-type junction in which the impurity concentration distribution changes steeply, the second conductivity type impurity is diffused in the first base region into which no inactive ion species is implanted, and the concentration distribution at the junction with the semiconductor layer is reduced. This results in a gradual junction that changes gradually.

Thus, the second junction formed by the step-shaped junction is formed.
Is reduced at the PN junction between the base region and the semiconductor layer, and avalanche breakdown can occur at this portion. Thereby, the withstand voltage of the device can be improved.

Such a configuration is applicable to, for example, a silicon carbide semiconductor device forming a vertical MOSFET as described in claim 3 and a silicon carbide semiconductor device forming a horizontal MOSFET as described in claim 6. is there.

According to the second aspect of the present invention, the second base region (30) is formed to have a deeper junction depth than the first base region, and the first base region has inert ions. A seed is implanted, and a junction between the first base region and the semiconductor layer forms a step-shaped junction in which the concentration distribution of the second conductivity type impurity changes steeply. Is characterized by forming an inclined junction in which the concentration distribution of the second conductivity type impurity gradually changes.

As described above, since the diffusion of the second conductivity type impurity is suppressed in the first base region, which is the region into which the inert ion species is implanted, the second conductivity type impurity is bonded at the junction with the semiconductor layer. A stair-type junction in which the impurity concentration distribution changes steeply, the second conductivity type impurity is diffused in the second base region into which no inactive ion species is implanted, and the concentration distribution at the junction with the semiconductor layer is reduced. This results in a gradual junction that changes gradually. At this time, in the second base region, the junction depth can be formed to be deeper than the first base region by thermal diffusion of the second conductivity type impurity, so that the distance to the semiconductor substrate can be shortened. , Can act as a deep base layer. For this reason, the avalanche breakdown can be ensured in the second base region, and the breakdown voltage can be improved.

Such a structure is applicable to, for example, a silicon carbide semiconductor device forming a vertical MOSFET as described in claim 5 and a silicon carbide semiconductor device forming a horizontal MOSFET as described in claim 7. is there.

In the case where the above structure is applied to the vertical and horizontal MOSFETs according to the third and fifth aspects of the present invention, as described in the eighth aspect, the lower portion of the base region below the contact portion with the source electrode. The second base region can be formed at the same time. If the second base region is formed at the bottom of the contact portion with the source electrode in this manner, the hole current generated by avalanche breakdown can be drawn directly above, so that the base sandwiched between the source and the drain The current can hardly flow through the resistance (pinch resistance) of the portion, and the parasitic bipolar transistor can hardly operate. As a result, the surge energy resistance can be further improved.

According to the ninth aspect of the present invention, after the second conductivity type impurity is ion-implanted into the surface layer of the semiconductor layer (2), the second conductivity type impurity is activated while being diffused by heat treatment. Forming a first base region by ion-implanting an inert ion species into a surface portion of the semiconductor layer; and implanting the inert ion species into a region where the inert ion species is implanted. The second conductivity type impurity is ion-implanted at a predetermined concentration ratio, and then activated by heat treatment while suppressing the diffusion of the second conductivity type impurity, so that the impurity concentration is higher than that of the first base region. Forming two base regions (30).

By implanting inert ionic species,
Inactive ion species enter the vacancies of the carbon site, and the vacancies can be eliminated. The diffusion of impurities in silicon carbide is caused by crystal defects such as vacancies, and by eliminating such vacancies, it becomes possible to suppress impurity diffusion.

Therefore, the first base region is
The first conductive type impurity is formed so as to be thermally diffused, and the second base region is implanted with an inert impurity so as to prevent the second conductive type impurity from being thermally diffused. The impurity concentration profile can be controlled such that the junction between the base region and the semiconductor layer becomes an inclined junction, and the junction between the second base region and the semiconductor layer becomes a step-shaped junction. Therefore, the withstand voltage can be reduced at the junction between the second base region and the semiconductor layer, and avalanche breakdown can occur at this portion.

Such a manufacturing method is described, for example, in claim 1
13. Production of a base region of a silicon carbide semiconductor device constituting the vertical MOSFET shown in FIG.
The present invention can be applied to manufacture of a base region of a silicon carbide semiconductor device constituting an FET.

In such a case, if the source region (4) and the mask material (51) for forming the first base region are the same, the first base region is formed. Are formed by thermal diffusion, so that the source region and the base region can be formed in a self-aligned manner. Therefore, the length of the first base region between the source region and the semiconductor layer (the width of the first base region below the channel region) is accurately defined by the diffusion amount, and the channel characteristics can be made uniform. As a result, the threshold voltage, on-resistance, channel breakdown voltage, and the like can be uniformly and stably formed in the cell.

In this case, a recess penetrating the source region and reaching the first base region is formed, and the inert ion species and the second conductivity type impurity are formed so as to include the recess. Is implanted, the second base region can be formed deep. For this reason,
Further, the withstand voltage of the second base region can be made lower than the withstand voltage of the first base region.

According to a tenth aspect of the present invention, an inert ion species is ion-implanted into a surface portion of the semiconductor layer (2), and the inert ion species is implanted into a region where the inert ion species is implanted. Ion-implanting a second conductivity type impurity at a predetermined concentration ratio with respect to the seed, and then activating the second conductivity type impurity while suppressing diffusion of the second conductivity type impurity by heat treatment to form a first base region; After the second conductivity type impurity is ion-implanted, the second conductivity type impurity is activated while being diffused downward by a heat treatment, and the second base region is formed so that the junction depth becomes deeper than the first base region. Forming (30).

As described above, the second base region is formed by implanting an inert impurity so that the second conductivity type impurity is not thermally diffused, and the second base region is formed by the second conductivity type. By forming the impurity so that the impurities are thermally diffused, the junction between the first base region and the semiconductor layer becomes a step-type junction, and the junction between the second base region and the semiconductor layer becomes an inclined junction. Thus, the impurity concentration profile can be controlled. Since the second base region is formed by thermal diffusion, the junction depth of the second base region can be made deeper than that of the first base region. For this reason, the distance between the second base region and the semiconductor substrate can be reduced, and avalanche breakdown can occur at this portion.

Such a manufacturing method is described, for example, in claim 1
17. Manufacture of a base region of a silicon carbide semiconductor device constituting the vertical MOSFET shown in FIG.
The present invention can be applied to manufacture of a base region of a silicon carbide semiconductor device constituting an FET.

The concentration ratio between the inert ion species and the second conductivity type impurity may be such that the inert ion species can eliminate vacancies in the carbon site.
As shown in the above, the amount of inactive ion species should be 10 times or more of the second conductivity type impurity.

As the inert ion species and the second conductivity type impurities, C (carbon)
And B (boron). Since B is a light element even in the second conductivity type impurity (p-type impurity), implantation damage can be reduced. Further, C is the same element as the lattice defect (C vacancy) that causes the diffusion of B.
The hole can be filled and repaired efficiently by
The injection amount can be reduced more efficiently than other inert ions.

Note that the reference numerals in parentheses of the above-mentioned means indicate the correspondence with specific means described in the embodiments described later.

[0030]

(First Embodiment) FIG. 1 shows a cross-sectional configuration of a vertical power MOSFET to which an embodiment of the present invention is applied. Hereinafter, the structure of the MOSFET according to the present embodiment will be described with reference to FIG.

The n ⁺ type semiconductor substrate 1 made of silicon carbide has an upper surface as a main surface 1a and a lower surface opposite to the main surface as a back surface 1b. On main surface 1a of substrate 1 made of this n ⁺ type semiconductor, an n ⁻ type epitaxial layer (hereinafter, referred to as silicon carbide) having a lower dopant concentration than substrate 1 is formed.
2 (referred to as an n ^- type epi layer).

A p-type base region 3 having a predetermined depth is formed in a predetermined region in the surface portion of the n ⁻ -type epi layer 2. The p-type base region 3 is formed using B as a dopant. Further, the p-type base region 3 includes a deep base layer (second base region) 30 whose junction depth is partially increased. This deep base layer 30
Is the other part of the p-type base region 3 (first base region)
It is composed of a relatively high concentration. For example, the deep base layer 30 has a concentration of 1 × 10 ¹⁷ cm ⁻³ or more. For this reason, the junction between the other part of the deep base layer 30 in the p-type base region 3 and the n ⁻ -type epi layer 2 forms an inclined junction in which the impurity concentration distribution gradually changes, and the deep base layer The junction between 30 and n ⁻ -type epi layer 2 forms a step-type junction in which the impurity concentration distribution changes sharply.

In the deep base layer 30, C (carbon) is implanted as an inert ion species. This C
With respect to the concentration of B in the deep base layer 30,
B: C is a ratio of about 1:10, preferably C is 1 of B
It is mixed in the deep base layer 30 to an extent of at least 0 times.

The other portion of the deep base layer 30 in the p-type base region 3 is formed by thermal diffusion, and the radius of curvature of the corner of the junction between this portion and the n ⁻ -type epi layer 2 is Is larger than the radius of curvature at the corner of the junction between the deep base layer 30 and the n ⁻ -type epi layer 2.

Further, an n ⁺ -type source region 4 shallower than the base region 3 is formed in a predetermined region of the surface layer of the p-type base region 3. Then, the n ⁺ type source region 4 and n
^An n ⁻ -type SiC layer 5 extends on the surface of the p-type base region 3 so as to connect with the ⁻ type epi layer 2. The n ⁻ -type SiC layer 5 is formed by epitaxial growth, and has an epitaxial film having 4H, 6H, and 3C crystals. The n ⁻ -type SiC layer 5 functions as a channel forming layer during operation of the device. Hereinafter, n ⁻ -type SiC layer 5 is referred to as a surface channel layer.

The surface channel layer 5 is formed using N (nitrogen) as a dopant, and the dopant concentration is as low as about 1 × 10 ¹⁵ cm ^-3 to 1 × 10 ¹⁷ cm ^-3 , for example. , N ⁻ -type epi layer 2 and p-type base region 3 are lower than the dopant concentration. Thereby, low on-resistance is achieved.

The n ⁻ -type epi layer 2 located between the p-type base regions 3 constitutes a so-called J-FET section 6.

A gate oxide film 7 is formed on the upper surface of the surface channel layer 5 and the upper surface of the n ⁺ type source region 4 by thermal oxidation. Further, a gate electrode 8 is formed on the gate oxide film 7. Gate electrode 8 is covered with insulating film 9. LTO (Low Tempe) as the insulating film 9
(Rate oxide) film is used. A source electrode 10 is formed on insulating film 9, and source electrode 10 is in contact with n ⁺ -type source region 4 and p-type base region 3. A drain electrode layer 11 is formed on the back surface 1b of the n ⁺ type semiconductor substrate 1.

The planar type MOSF thus constructed
Since the ET operates in the accumulation mode in which the channel is induced without inverting the conductivity type of the channel forming layer, the channel mobility can be increased as compared with the MOSFET in the inversion mode in which the conductivity type is inverted, and the on-resistance is reduced. Can be done.

The deep base layer 30 of the p-type base region 3 is formed at a higher concentration than the other portions, and the junction of the PN diode formed by the deep base layer 30 and the n ⁻ -type epi layer 2 is formed at a higher concentration. Since the breakdown voltage is reduced by using a stair-shaped junction in which the distribution changes sharply, avalanche breakdown can occur in the deep base layer 30.

In the other part of the deep base layer 30 in the p-type base region 3, a parasitic bipolar transistor composed of the n ⁺ -type source region 4, the p-type base region 3, and the n ^-- type epi layer 2 is inherent. However, by performing the avalanche breakdown in the deep base layer 30 as described above, a hole current does not flow in a portion where the parasitic bipolar transistor is present, and the surge energy resistance can be increased.

In the p-type base region 3, since the deep base layer 30 is formed at the bottom of the contact portion with the source electrode 10, the hole current generated by the avalanche breakdown is reduced.
It can be extracted from 0 to the source electrode 10 directly above.
Therefore, current hardly flows through the resistance (pinch resistance) portion of the base portion sandwiched between the source and the drain, so that the parasitic transistor is less likely to operate. Therefore, the surge energy resistance can be increased.

Next, the manufacturing process of the MOSFET shown in FIG. 1 is shown in FIG. 2 to FIG.
A method for manufacturing the SFET will be described.

[Step shown in FIG. 2A] First, the n-type 4
An H, 6H, 3C or 15R-SiC substrate, that is, an n ⁺ type substrate 1 is prepared. Here, the n ⁺ type substrate 1 has a thickness of 400 μm and a main surface 1 a of (0001) S
The i-plane or the (112-0) a-plane. On the main surface 1a of the substrate 1, an n ⁻ -type epi layer 2 having a thickness of 5 μm is epitaxially grown. In this example, the same crystal as that of the underlying substrate 1 is obtained as the n ⁻ -type epi layer 2, which becomes an n-type 4H, 6H, 3C or 15R-SiC layer.

[Step shown in FIG. 2B] n^-Type epi layer 2
An opening is formed on the region where the deep base layer 30 is to be formed.
LTO film 20 is disposed, and this is
C ion as an ion species is implanted. At this time,
On implantation conditions are as follows: temperature is 700 ° C., and dose is 1 × 10
¹⁷cm^-2And Here, C is used.
But silicon (Si) and neon as inert ion species
(Ne) or argon (Ar)
No. When a carbon ion species is used, n^-Type d
C constituting the layer 2⁺¹²May be used, and n^-Type d
C different from the carbon ion constituting the p-layer^{+1 Three}Using
You may.

Thus, an inert ion implanted layer 40 is formed in a region where the deep base layer 30 is to be formed. By ion-implanting ionic species that do not become impurities, ionic species that do not become impurities enter the vacancies of the carbon sites generated when the n ⁻ -type epilayer 2 is epitaxially grown. By increasing the amount of ion implantation of non-impurity ion species, vacancies at carbon sites are almost eliminated.

Since the size of the vacancy in the carbon site is equivalent to the size of the carbon atom, carbon is most likely to enter the vacancy. Can be almost eliminated,
Since ion species other than carbon, such as silicon, are less likely to enter the vacancies at the carbon site than carbon, it is preferable to increase the ion implantation amount as compared with the case where carbon is ion-implanted.

[Steps shown in FIG. 2 (c)]
B ions are implanted using the film 20 as a mask. At this time, the ion implantation conditions are a temperature of 700 ° C. and a dose of 1
× 10 ¹⁶ cm ^-2 . That is, the dose is set so that the ratio of B: C to the concentration of C to about 1:10 with respect to C implanted in the step shown in FIG.

As a result, the B-implanted deep base layer 30 is positioned at a predetermined depth from the surface of n ⁻ -type epi layer 2.
Is formed.

Thereafter, as heat treatment, 1600 ° C., 30
Then, activation annealing for a minute is performed to activate B in the deep base layer 30. At this time, as described above,
In the region where the deep base layer 30 is formed, vacancies at the carbon site are eliminated by implanting ion species that do not become impurities, so that diffusion of B generated due to the vacancy at the carbon site is prevented. Can be suppressed.

For this reason, the deep base layer 30 hardly spreads due to the diffusion of B, and the deep base layer 30 keeps its shape at the time of ion implantation and is formed at a high concentration.

[Step shown in FIG. 3A] n ⁻ -type epi layer 2
The LTO film 21 is disposed on the substrate. Then, the J ⁺ FET region 6 of the LTO film 21 and the n ⁺ type source region 4 of the p
Other portions are removed except for a portion located above a portion sandwiched between the ET portions 6 (a portion where a channel region is to be formed (see FIG. 1)). That is, the p-type base region 3
Of these, the LTO film 21 is opened in an upper portion other than the portion located under the surface channel layer 5.

Thereafter, B ions are implanted using the LTO film 21 as a mask. At this time, the ion implantation conditions are that the temperature is 700 ° C. and the dose is 1 × 10 ¹⁶ cm ⁻² .
Thus, an impurity-implanted layer 41 into which B has been implanted is formed at a position at a predetermined depth from the surface of the n ⁻ -type epi layer 2.

At this time, since the above-described portion of the LTO film 20 is opened, ion implantation is not performed in a portion to be a channel region, and the impurity implanted layer 41 is not formed in this region.

[Step shown in FIG. 3B] Next, after the LTO film 21 is removed, heat treatment is performed at 1600.degree.
Activation anneal is performed for a minute to activate B in the impurity implantation layer 41. As a result, B is thermally diffused in the horizontal and downward directions, forming the p-type base region 3 and J.
-The FET unit 6 is determined. As described above, since the p-type base region 3 is formed by thermal diffusion, the p-type base region 3 is formed at a lower concentration than the deep base layer 30.

At this time, since no inactive ion species are implanted into the impurity implanted layer 41 and its surroundings, B diffuses laterally below the channel region.

Therefore, the p-type base region 3 can be formed under the channel region by thermal diffusion.
Therefore, when the p-type base region 3 is formed under the channel region by directly ion-implanting under the channel region, the crystallinity of the surface channel layer 5 formed thereon is deteriorated due to ion implantation damage. However, by forming by thermal diffusion as in the present embodiment, the crystallinity of the surface channel layer 5 can be improved and the number of defects can be reduced. Thereby, the channel characteristics of the channel region formed in the surface channel layer 5 are improved, and the on-resistance can be reduced.

In addition, as described above, the deep base layer 30 is prevented from being thermally diffused by inert ion species.
Is formed, and the deep base layer 3 of the p-type base region 3 is formed.
0 is formed by thermal diffusion, the radius of curvature at the corner of the junction with the n ⁻ -type epi layer 2 in the deep base layer 30 is reduced, and the p-type base region 3 In other portions, the radius of curvature at the corner of the junction with the n ⁻ -type epi layer 2 becomes large.

In the deep base layer 30, a stair-type junction in which the impurity concentration distribution at the junction with the n ⁻ -type epi layer 2 changes steeply is formed. In the portion, an inclined junction in which the impurity concentration at the junction with the n ⁻ -type epi layer 2 changes gradually is obtained.

[Step shown in FIG. 3C] The impurity concentration is 1 × on the n ⁻ -type epi layer 2 including the surface of the p-type base region 3.
A surface channel layer 5 having a thickness of 10 ¹⁶ cm ⁻² or less and a thickness of 0.3 μm or less is epitaxially grown.

At this time, in order to make the vertical power MOSFET normally-off type, the thickness (film thickness) of the surface channel layer 5 is changed from the p-type base region 3 when the voltage is not applied to the gate electrode 8 to the surface channel layer. It is set to be smaller than the sum of the extension amount of the depletion layer extending to the layer 5 and the extension amount of the depletion layer extending from the gate oxide film 7 to the surface channel layer 5.

[Step shown in FIG. 4A] Next, an LTO film 22 is disposed in a predetermined region on the surface channel layer 5 and an n-type impurity such as N (nitrogen) is ion-implanted using the LTO film 22 as a mask. After that, the n ⁺ -type source region 4 is formed by activating the n-type impurity ions implanted by the heat treatment. The ion implantation condition at this time is 700 ° C., and the dose amount is 1 × 10
^{It is 15} cm ^-2 .

[Steps shown in FIG. 4 (b)]
After removing the film 22, the LTO film 23 is disposed in a predetermined region on the surface channel layer 5 using a photoresist method, and the surface channel layer 5 on the deep base layer 30 is partially formed by RIE using the LTO film 23 as a mask. Remove by etching.

Subsequently, wet oxidation (H ₂ +
The gate oxide film 7 is formed by a pyrogenic method using O ₂ ). At this time, the ambient temperature is 1080 ° C.
And

Then, after a polysilicon film is deposited on the gate insulating film 7 by LPCVD, the gate electrode 8
Is patterned. The film formation temperature at this time is 600 ° C.

[Step shown in FIG. 4C] Subsequently, after removing unnecessary portions of the gate insulating film 7, an insulating film 9 made of LTO is formed to cover the gate electrode 8 and the gate insulating film 7. More specifically, the film formation temperature is 425 ° C., and annealing is performed at 1000 ° C. after the film formation.

Thereafter, after the source electrode 10 and the drain electrode 11 are arranged by metal sputtering at room temperature, annealing is performed at 1000 ° C., whereby the vertical power MOSFET shown in FIG. 1 is completed.

(Second Embodiment) A second embodiment of the present invention will be described. In the present embodiment, a method of manufacturing a MOSFET is changed from that of the first embodiment. Therefore, a method of manufacturing a MOSFET will be described.

FIGS. 5 to 7 show MOS transistors according to the present embodiment.
The manufacturing process of the FET is shown.
A method for manufacturing the FET will be described. In the present embodiment, the MOSFET shown in FIGS.
Since there is a portion similar to that of the manufacturing method described above, the first embodiment is referred to for a similar step.

[Step shown in FIG. 5A] First, FIG.
An n ⁻ -type epi layer 2 is grown on an n ⁺ -type substrate 1 in the same manner as in the step shown in FIG. Thereafter, an LTO film 51 is formed above the n ⁻ -type epi layer 2 so as to open the region where the n ⁺ -type source region 4 is to be formed and the region where the deep base layer 30 is to be formed. Then, using the LTO film 51 as a mask, an n-type impurity such as N or P is ion-implanted. This gives n
^{A +} type source region 4 is formed. The ion implantation conditions at this time are the same as those for forming the n ⁺ -type source region 4 shown in FIG.

[Step shown in FIG. 5 (b)]
B ions are implanted using the film 51 as a mask again. The ion implantation conditions at this time are the same as those for forming the impurity implantation layer 40 shown in FIG. This gives n ⁺
An impurity implanted layer 52 in which B is implanted to below the mold source region 4 is formed.

[Step shown in FIG. 5C] Next, after the LTO film 51 is removed, heat treatment is performed at 1600 ° C. and 30 ° C.
Activation anneal for a minute is performed to activate B in the impurity implantation layer 52. As a result, B is thermally diffused in the horizontal and downward directions, forming the p-type base region 3 and J.
-The FET unit 6 is determined. Thus, since the p-type base region 3 is formed by thermal diffusion, the p-type base region 3 is formed at a relatively low concentration.

At this time, since no inactive ion species are implanted into the impurity implanted layer 52 and its surroundings, B diffuses laterally below the channel region. For this reason, since ion implantation damage can be prevented from being formed on the surface of the p-type base region 3 under the channel region, the crystallinity of the surface channel layer 5 formed thereafter can be improved, and the first embodiment The same effect as in the embodiment can be obtained.

Further, since the n ⁺ type source region 4 and the p type base region 3 are formed using the same mask,
N ⁺ type source region 4 and p type base region 3 are formed in a self-aligned manner. That is, the width of the p-type base region 3 below the channel region is accurately defined by the diffusion amount of B.
Therefore, the channel characteristics can be made uniform, and the threshold voltage, on-resistance, channel breakdown voltage, and the like can be uniformly and stably formed in the cell.

[Step shown in FIG. 6A] The same step as that shown in FIG. 3C is performed to form the n ⁻ -type epi layer 2 including the surface of the p-type base region 3 and the surface of the n ⁺ -type source region 4. A surface channel layer 5 is epitaxially grown thereon.

[Step shown in FIG. 6B] Subsequently, the surface channel layer 5 is patterned to leave a region connecting the n ⁺ -type source region 4 and the n ^-- type epi layer 2 and unnecessary portions. Is removed.

Then, the upper portions of the n ⁺ type source region 4 and the n ⁻ type epi layer 2 are covered with an LTO film 53, and RIE (reactive ion etching) is performed using the LTO film 53 as a mask to form the n ⁺ type source region 4. A recess that penetrates and reaches the p-type base region 3 is formed.

[Step shown in FIG. 6C] Using the LTO film 53 as a mask, C (carbon) ions are implanted as inert ion species. The ion implantation conditions for C at this time are shown in FIG.
The implantation conditions of C shown in FIG. Thus, an inert ion implanted layer 54 in which C is implanted in a region where the deep base layer 30 is to be formed is formed. At this time,
C enters the vacancy of the carbon site, and the vacancy of the carbon site in the inert ion implantation layer 54 can be substantially eliminated.

Since the ion implantation of C at this time is performed in the recessed portion, it can be implanted deep even if the ion implantation energy is small, so that there is no need to use a high energy ion implantation apparatus.

[Steps shown in FIG. 7 (a)]
B ions are implanted using the film 53 as a mask. The conditions for the ion implantation at this time are the same as the implantation conditions for B shown in FIG. As a result, a deep base layer 30 into which B has been implanted is formed at a position at a predetermined depth from the surface of the n ⁻ -type epi layer 2.

Thereafter, as heat treatment, 1600 ° C., 30
Then, activation annealing for a minute is performed to activate B in the deep base layer 30. At this time, as described above,
In the region where the deep base layer 30 is formed, vacancies at the carbon site are eliminated by implanting ion species that do not become impurities, so that diffusion of B generated due to the vacancy at the carbon site is prevented. Can be suppressed.

As described above, other portions of the deep base layer 30 in the p-type base region 3 are formed by thermal diffusion, and the deep base layer 30 is formed so as not to thermally diffuse. The shape of the corner at the junction with the n ⁻ -type epi layer 2 is the same as that of the first embodiment, and the relationship of the impurity concentration distribution at the junction is also the first.
It is the same as the embodiment.

[Step shown in FIG. 7B] After removing the LTO film 53, the gate oxide film 7 is patterned by the same method as the step shown in FIG. The gate electrode 8 is patterned on the oxide film 7.

[Step shown in FIG. 7C] Then, after covering the gate electrode 8 with the insulating film 9 by the same method as the step shown in FIG. 4C of the first embodiment, the source electrode 10 The drain electrode 11 is formed, and the MOS in this embodiment is formed.
The FET is completed.

FIG. 7 (c) is a completed view of the MOSFET according to the present embodiment, which differs from the first embodiment in that a recess is formed above the deep base layer 3, and that n ⁺ There is a structural difference in that electrical connection to the surface channel layer 5 is made at the surface of the mold source region 4. However, this is a difference in the configuration due to the difference in the manufacturing method.
As for T, a large amount of surge energy can be improved as in the first embodiment.

(Third Embodiment) A third embodiment of the present invention will be described. FIG. 8 shows the MOSF in this embodiment.
The cross-sectional configuration of the ET is shown, and the configuration of the MOSFET according to the present embodiment will be described below with reference to this drawing. However, since the MOSFET in the present embodiment has substantially the same configuration as the MOSFET in the first embodiment,
Only different parts will be described.

As shown in FIG. 8, M in the present embodiment
In the OSFET, the deep base layer 30 in the p-type base region 3 is formed by thermal diffusion, and the impurity concentration is lower than in other parts of the p-type base region 3. That is, in the deep base layer 30 of the p-type base region, a stair-type junction in which the impurity concentration changes sharply at the junction with the n ⁻ -type epi layer 2 is formed, and the other of the p-type base region 3 is formed. The portion forms an inclined junction in which the impurity concentration gradually changes at the junction with the n ⁻ -type epi layer 2.

Further, in the deep base layer 30,
n ^- type epitaxial layer 2 has a curvature radius of the corner portion is constituted largely at the junction between, in the other parts of the deep base layer 30 of p-type base region 3, n ^- junction between type epi layer 2 The radius of curvature of the corner in the portion is configured to be small.

The deep base layer 30 extends below other portions of the p-type base region 3, and the p-type base region 3 and the n-type
It is configured such that the distance from the ⁺ type substrate 1 is reduced.

In the MOSFET configured as described above, the depletion layer extending from deep base layer 30 has n ⁺ faster than the depletion layer extending from the other portion of p-type base region 3.
Since it can reach (reach-through) the mold substrate 1, the electric field strength at the bottom of the deep base layer 30 is increased, and p
Avalanche breakdown may occur before the bottom of other portions of the mold base region.

Therefore, at the time of reverse bias, avalanche breakdown can occur at the bottom of deep base layer 30, and a hole current can be drawn to source electrode 10 through deep base layer 30. For this reason, the hole current becomes n ⁻ -type epi layer 2, p
It can be prevented from flowing to the parasitic bipolar transistor constituted by the mold base region 3 and the n ⁺ -type source region 4, and the surge energy withstand can be improved as in the first embodiment.

Next, a manufacturing process of the MOSFET according to the present embodiment is shown in FIG. Hereinafter, a method for manufacturing the MOSFET according to the present embodiment will be described with reference to FIG. However, in the present embodiment, FIGS.
Since there are portions similar to those of the MOSFET manufacturing method shown in FIG. 1, the first embodiment is referred to for the similar steps.

[Step shown in FIG. 9A] First, FIG.
An n ⁻ -type epi layer 2 is grown on an n ⁺ -type substrate 1 in the same manner as in the step shown in FIG. Thereafter, an LTO film 61 is formed above the n ⁻ -type epi layer 2 so that the LTO film 61 has an opening on the region where the other portion of the deep base layer 30 is to be formed. Then, C is ion-implanted as an inert ion species using the LTO film 61 as a mask. This gives p
An inert ion implantation layer 62 is formed in a region of the mold base region 3 where another portion of the deep base layer 30 is to be formed.

The ion implantation conditions at this time are as shown in FIG.
Are the same as the C implantation conditions shown in FIG. This gives p
In other portions of the deep base layer 30 in the mold base region 3, C enters the vacancies of the carbon sites, and the vacancies of the carbon sites almost disappear.

[Step shown in FIG. 9B] Subsequently, an LTO film 63 having an opening on a region where the p-type base region 3 including the deep base layer 30 is to be formed is arranged.
Is used as a mask to implant B ions. The ion implantation conditions at this time are as follows: a temperature of 700 ° C. and a dose of 1 × 10 ¹⁶ c.
m ^-2 .

As a result, only B is implanted into the region where the deep base layer 30 is to be formed in the p-type base region 3, and B is implanted into C in the region where the other portion of the p-type base region 3 is to be formed. An impurity implantation layer 64 implanted in a stacked manner is formed.

[Step shown in FIG. 9C]
Activation annealing is performed at 1600 ° C. for 30 minutes to activate B in the impurity implantation layer 64.

At this time, since only B is implanted into the region of the p-type base region 3 where the deep base layer 30 is to be formed, activation is performed in a state where B is thermally diffused downward. On the other hand, C is injected into the other part of the deep base layer 30 in the p-type base region 3 to eliminate the vacancies at the carbon site, so that thermal diffusion of B is prevented, and the position where the B is injected is almost eliminated. Activation is performed as it is.

As a result, the p-type base region 3 is formed, and the junction depth of the deep base layer 30 in the p-type base region 3 is deeper than the other portions, the impurity concentration becomes lower, and the p-type base region 3 becomes deeper. 30 and n ^- type epilayer 2
The radius of curvature at the corner of the deep base layer 30 at the junction with the p-type base region 3 at the junction between the other portion and the n ⁻ -type epi layer 2 is larger than that at the junction with the n ⁻ -type epi layer 2.

Thereafter, FIG. 3 shown in the first embodiment is used.
By performing the steps of (c) and FIGS. 4A to 4C, the MOSFET of the present embodiment is completed.

According to the above manufacturing process, the diffusion of B lowers the p-type impurity concentration in the deep base layer 30 in the deep base layer 30, so that the n ⁻ -type epi layer 2 and the p-type base region 3, and n ⁺
In some cases, the parasitic transistor constituted by the mold source region 4 is activated, and the element is destroyed. That is, the surge energy resistance can be reduced. For this reason,
In a step different from the step shown in FIG. 9B, p-type impurities are ion-implanted in the deep base layer 30 in a larger amount than in other parts of the p-type base region 3, so that the inside of the deep base layer has a high concentration. You may make it become.

(Fourth Embodiment) A fourth embodiment of the present invention will be described. In the present embodiment, a method of manufacturing a MOSFET is changed from that of the third embodiment. Therefore, a method of manufacturing a MOSFET will be described.

FIGS. 10 to 11 show M in this embodiment.
The manufacturing process of the OSFET is shown.
A method for manufacturing an OSFET will be described. In the present embodiment, the MOSF shown in FIGS.
Since there are portions similar to those of the ET manufacturing method, the first embodiment is referred to for the same steps.

[Steps shown in FIG. 10A] First, FIG.
An n ⁻ -type epi layer 2 is grown on an n ⁺ -type substrate 1 in the same manner as in the step shown in FIG. Thereafter, a p-type semiconductor layer 70 doped with Al (aluminum) as a p-type impurity is grown on the surface of the n ⁻ -type epi layer 2.

[Step shown in FIG. 10B] An LTO film 71 having an opening on a portion where the J-FET portion 6 is to be formed is arranged.
RIE is performed using the LTO film 71 as a mask, and the recess 7 penetrates the p-type semiconductor layer 70 and reaches the n ⁻ -type epi layer 2.
Form 2 Thus, the p-type base region 3 is formed by the p-type semiconductor layer 70.

[Step shown in FIG. 10C] LTO film 71
Is removed, an n-type semiconductor layer is deposited on the entire surface of the p-type base region 3 including the recess 72, and the recess 72 is buried. Then, the n-type semiconductor layer is etched back to leave only in the concave portion 72. Thus, an n-type layer 2a made of an n-type semiconductor is formed in the concave portion 72. The n-type layer 2a forms the J-FET section 6. Incidentally, the drift region comprising a J-FET unit 6 in the above embodiment the n ^- had been composed -type epitaxial layer 2, the present embodiment n-type layer 2a and the n ^- configuration drift region by the type epitaxial layer 2 Will be done.

[Step shown in FIG. 11A] In the same manner as the step shown in FIG. 3C, a surface channel layer 5 is epitaxially grown on the n ⁻ -type epi layer 2 including the surface of the p-type base region 3. Let it.

[Step shown in FIG. 11B] On the surface channel layer 5, an LTO film 73 having an opening in a region where the deep base layer 30 is to be formed is arranged. Then, ion implantation of B is performed using the LTO film 73 as a mask (a dotted line portion in the figure). The ion implantation conditions at this time are the same as the B implantation conditions shown in FIG.

[Step shown in FIG. 11C] A heat treatment is performed to activate the implanted B. At this time, in the other part of the deep base layer 30 in the p-type base region 3 formed by doping with Al, Al is hardly thermally diffused. Is maintained. On the other hand, since no inactive ion species is implanted around B,
B is diffused downward or the like by the heat treatment. This allows
A deep base layer 30 in which the p-type base region 3 is partially deepened is formed.

As described above, the deep base layer 30 of the p-type base region 3 is formed of B which is easily thermally diffused among the p-type impurities, and the other portions are made of Al which is not easily thermally diffused among the p-type impurities. The same structure as in the third embodiment can be formed also by using.

Further, as in this embodiment, the p-type base region 3
If another region of the deep base layer 30 is formed by epitaxial growth, ion implantation damage is not formed unlike the case of ion implantation, so that the surface channel layer 5 formed thereon has good crystallinity. , The channel mobility can be increased, and the on-resistance can be reduced. (Other Embodiments) In the first embodiment, the p-type base region 3
Above, the same effect can be obtained in other elements having a base region, and the above effects can be obtained.

For example, among devices having a plurality of base regions, there are devices having a small contact area between the base region and the electrode (in the case of the first embodiment, the p-type base region 3 and the source electrode 10). In this case, when the surge energy is extracted from the electrode, a local surge breakdown may occur due to an increase in the energy density.

In such a case, by forming the base region having a large contact area with a high concentration, the withstand voltage can be increased in the base region having a small contact area. Avalanche breakdown does not occur at the bottom of the base region where the area becomes small, and avalanche breakdown occurs at the base region where the contact area becomes large.

Therefore, at the time of reverse bias, holes generated during avalanche breakdown are drawn out to the electrode as surge voltage energy in the base region where the contact area is large, and holes are drawn out in the base region where the contact area is small. Since it can be prevented from being pulled out, the base region having a small contact area can be protected from surge destruction.

Also, as in the above embodiment, the vertical MOS
Instead of an FET, a channel region is formed below the gate electrode, n-type sources and drains are formed on both sides of the channel region in the surface layer of the p-type base region, and the p-type base region, the deep base layer and the source are formed. Lateral (horizontal) MOSFET having a source electrode in contact with the region and a drain electrode in contact with the drain region
May be applied.

In the first embodiment, the deep body layer 3 is formed in a region where no parasitic bipolar transistor exists.
0, so that avalanche breakdown occurs in this region. However, even if a deep body layer is formed in a region where a parasitic bipolar transistor is present, a hole current flows through a path that makes it difficult to operate the parasitic bipolar transistor. With such a configuration, the same effect as in the first embodiment can be obtained.

In the first and second embodiments, the junction depth of the deep body layer 30 is made deeper than other portions of the p-type base region 3. However, as shown in FIG. It may be formed so as to have the same depth as other portions of p-type base region 3 or may be formed so as to be shallower than other portions of p-type base region 3 as shown in FIG.

When the deep base layer 30 is made shallower than other portions of the p-type base region 3 as shown in FIG. 13, the step shown in FIG. 2C of the first embodiment is performed. May be omitted and the steps shown in FIGS. 3A and 3B may be performed as it is, so that the steps can be simplified.

In each of the above embodiments, B is used as the p-type impurity which is easily diffused by heat. However, when an impurity which is easily diffused due to a crystal defect is used regardless of whether it is a p-type impurity or an n-type impurity, A method of implanting an inert ion species even for other impurities can be adopted.

[Brief description of the drawings]

FIG. 1 is a diagram showing a cross-sectional configuration of a MOSFET according to a first embodiment of the present invention.

FIG. 2 is a view showing a manufacturing process of the MOSFET shown in FIG. 1;

FIG. 3 is a diagram showing a manufacturing step of the MOSFET following FIG. 2;

FIG. 4 is a view showing a manufacturing step of the MOSFET following FIG. 3;

FIG. 5 is a diagram showing a manufacturing process of the MOSFET according to the second embodiment.

FIG. 6 is a view showing a manufacturing step of the MOSFET following the step shown in FIG. 5;

FIG. 7 is a diagram showing a manufacturing step of the MOSFET following FIG. 6;

FIG. 8 is a diagram illustrating a cross-sectional configuration of a MOSFET according to a third embodiment.

FIG. 9 is a view showing a manufacturing process of the MOSFET shown in FIG. 8;

FIG. 10 is a diagram illustrating a manufacturing process of the MOSFET according to the fourth embodiment.

FIG. 11 is a view showing a manufacturing step of the MOSFET following the step shown in FIG. 10;

FIG. 12 is a diagram illustrating a cross-sectional configuration of a MOSFET according to another embodiment.

FIG. 13 is a diagram illustrating a cross-sectional configuration of a MOSFET according to another embodiment.

FIG. 14 is a diagram showing a cross-sectional configuration of a conventional MOSFET.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... n ⁺ type semiconductor substrate, 2 ... n ^- type epi layer, 3 ... p-type base region, 4 ... n ⁺ type source region, 5 ... surface channel layer, 6 ... J-FET part, 7 ... gate oxide film, 8 gate electrode, 9 insulating film, 10 source electrode, 11 drain electrode, 30 deep base layer.

Claims (19)

[Claims] A first conductivity type semiconductor substrate having a main surface and a back surface opposite to the main surface, the first conductivity type semiconductor substrate being made of single-crystal silicon carbide; and a semiconductor substrate formed on the main surface of the semiconductor substrate; A first conductivity type semiconductor layer having an impurity concentration lower than that of the semiconductor substrate; and a second conductivity type first base region formed in at least one predetermined region of a surface layer portion of the semiconductor layer. 3) and a second conductivity type second base region (30) formed at least one or more in a predetermined region on the surface of the semiconductor layer and having an impurity concentration higher than that of the first base region. A silicon carbide semiconductor device, wherein the first base region is formed by thermal diffusion of a second conductivity type impurity, and a junction between the first base region and the semiconductor layer is formed of a second conductivity type impurity. Inclined junction with gradual change in concentration distribution Inactive ion species are implanted in the second base region, and at the junction between the second base region and the semiconductor layer, the concentration distribution of the impurity of the second conductivity type changes sharply. A silicon carbide semiconductor device characterized by forming a step-shaped junction. 2. A semiconductor substrate (1) of a first conductivity type having a main surface and a back surface opposite to the main surface and made of single-crystal silicon carbide, and formed on the main surface of the semiconductor substrate; A first conductivity type semiconductor layer having an impurity concentration lower than that of the semiconductor substrate; and a second conductivity type first base region formed in at least one predetermined region of a surface layer portion of the semiconductor layer. 3) a second base region of the second conductivity type formed at least one or more in a predetermined region on the surface of the semiconductor layer and having a junction depth deeper than the first base region. And an inactive ion species is implanted in the first base region, and a junction between the first base region and the semiconductor layer has a second conductivity type. A step-type junction where the impurity concentration distribution changes steeply The second base region is formed so as to have a junction depth greater than that of the first base region by thermally diffusing a second conductivity type impurity, and a junction between the second base region and the semiconductor layer is formed. The portion forms an inclined junction in which the concentration distribution of the second conductivity type impurity gradually changes. 3. A semiconductor substrate (1) of a first conductivity type having a main surface and a back surface opposite to the main surface and made of single-crystal silicon carbide, formed on the main surface of the semiconductor substrate, A first conductivity type semiconductor layer having a lower impurity concentration than the semiconductor substrate; a second conductivity type base region formed in a surface portion of the semiconductor layer; and a surface portion of the base region. A first conductivity type source region (4) formed on the substrate; a gate insulating film (7) formed on the channel region to form a channel region between the source region and the semiconductor layer; A gate electrode (8) formed on the gate insulating film; a source electrode (10) formed to contact the base region and the source region; and a drain electrode formed on the back surface of the semiconductor substrate. (1
1), wherein the base region is constituted by a first base region and a second base region (30), and the first base region is formed by thermal diffusion of a second conductivity type impurity. At the junction with the semiconductor layer,
The second base region has an impurity concentration higher than that of the first base region, and forms an inactive ion species. While being implanted, at the junction with the semiconductor layer,
A silicon carbide semiconductor device having a step-shaped junction in which the concentration distribution of a second conductivity type impurity changes sharply. 4. A portion of the first base region sandwiched between the source region and the semiconductor layer,
4. The silicon carbide semiconductor device according to claim 3, wherein the silicon carbide semiconductor device is formed by thermally diffusing a conductive impurity. 5. A semiconductor substrate (1) of a first conductivity type having a main surface and a back surface opposite to the main surface and made of single-crystal silicon carbide, formed on a main surface of the semiconductor substrate, A first conductivity type semiconductor layer having a lower impurity concentration than the semiconductor substrate; a second conductivity type base region formed in a surface portion of the semiconductor layer; and a surface portion of the base region. A first conductivity type source region (4) formed on the substrate; a gate insulating film (7) formed on the channel region to form a channel region between the source region and the semiconductor layer; A gate electrode (8) formed on the gate insulating film; a source electrode (10) formed to contact the base region and the source region; and a drain electrode formed on the back surface of the semiconductor substrate. (1
Wherein the base region includes a first base region and a second base region (30), and the first base region is implanted with an inert ion species. Forming a stair-shaped junction in which the concentration distribution of the second conductivity type impurity changes steeply at a junction with the semiconductor layer, wherein the second base region thermally diffuses the second conductivity type impurity. Thereby, the junction depth is formed to be deeper than that of the first base region, and the junction with the semiconductor layer forms an inclined junction in which the concentration distribution of the second conductivity type impurity changes gradually. A silicon carbide semiconductor device characterized by the above-mentioned. 6. A semiconductor substrate of a first conductivity type having a main surface and a back surface opposite to the main surface and made of single-crystal silicon carbide; and the semiconductor substrate formed on the main surface of the semiconductor substrate. A first conductive type semiconductor layer having a lower impurity concentration than the first conductive type semiconductor layer, a second conductive type base region formed on a surface layer of the semiconductor layer, a gate insulating film formed on the base region, A gate electrode formed on a gate insulating film; and a first conductivity type source region formed on both sides of the channel region in a surface layer portion of the semiconductor layer so as to form a channel region below the gate electrode. And a drain region; a source electrode formed to contact the base region and the source region; and a drain electrode formed to contact the drain region. The base region includes a first base region and a second base region. The first base region is formed by thermal diffusion of a second conductivity type impurity, and at a junction with the semiconductor layer, Second
The second base region has an impurity concentration higher than that of the first base region, and forms an inactive ion species. While being implanted, at the junction with the semiconductor layer,
A silicon carbide semiconductor device having a step-shaped junction in which the concentration distribution of a second conductivity type impurity changes sharply. 7. A semiconductor substrate of a first conductivity type having a main surface and a back surface opposite to the main surface and made of single-crystal silicon carbide; and a semiconductor substrate formed on the main surface of the semiconductor substrate. A first conductive type semiconductor layer having a lower impurity concentration than the first conductive type semiconductor layer, a second conductive type base region formed on a surface layer of the semiconductor layer, a gate insulating film formed on the base region, A gate electrode formed on a gate insulating film; and a first conductivity type source region formed on both sides of the channel region in a surface layer portion of the semiconductor layer so as to form a channel region below the gate electrode. And a drain region; a source electrode formed to contact the base region and the source region; and a drain electrode formed to contact the drain region. The source region includes a first base region and a second base region. The first base region is implanted with an inactive ion species, and at a junction with the semiconductor layer. A stair-type junction in which the concentration distribution of the second conductivity type impurity changes steeply, and the second base region is made larger than the first base region by thermally diffusing the second conductivity type impurity. A silicon carbide semiconductor device formed so as to have a deep junction depth and forming a tilted junction in which the concentration distribution of the second conductivity type impurity gradually changes at the junction with the semiconductor layer. . 8. The semiconductor device according to claim 3, wherein the second base region is formed below a portion of the base region that contacts the source electrode.
4. The silicon carbide semiconductor device according to any one of the above. 9. A semiconductor substrate (1) of a first conductivity type having a main surface and a back surface opposite to the main surface and made of single-crystal silicon carbide, and formed on the main surface of the semiconductor substrate. A first conductivity type semiconductor layer (2) having an impurity concentration lower than that of the semiconductor substrate; and a two conductivity type first base region (3) formed in at least one predetermined region of a surface layer portion of the semiconductor layer. And a second base region (30) of the second conductivity type formed at least one or more in a predetermined region on the surface of the semiconductor layer and having an impurity concentration higher than that of the first base region. A method for manufacturing a silicon carbide semiconductor device, comprising: ion-implanting a second conductivity type impurity into a surface portion of the semiconductor layer; and activating the first base by diffusing the second conductivity type impurity by heat treatment. Forming a region; Inert ion species are ion-implanted into the surface layer of the semiconductor layer, and a second conductivity type impurity is implanted into the region where the inert ion species is implanted at a predetermined concentration ratio with respect to the inert ion species. Ion implantation, followed by heat treatment
Activating while suppressing diffusion of the conductive type impurity,
Forming the second base region so that the impurity concentration is higher than that of the base region. 10. A semiconductor substrate of a first conductivity type having a main surface and a back surface opposite to the main surface and made of single-crystal silicon carbide; and a semiconductor substrate formed on the main surface of the semiconductor substrate; A first conductivity type semiconductor layer having an impurity concentration lower than that of the semiconductor substrate; and a second conductivity type first base region formed in at least one predetermined region of a surface layer portion of the semiconductor layer. 3) forming at least one or more in a predetermined region on the surface portion of the semiconductor layer, having a lower impurity concentration than the first base region, and a deeper junction depth than the first region; A method for manufacturing a silicon carbide semiconductor device having a second base region (30) of a second conductivity type, wherein an inert ion species is ion-implanted into a surface portion of the semiconductor layer, and the inert layer is ion-implanted. Inert area for ion species implantation The second conductivity type impurity at a predetermined concentration ratio is ion implanted into the ion species, then, the second by a heat treatment
Activating while suppressing diffusion of the conductive type impurity,
Forming a base region of the second conductivity type, and ion-implanting the second conductivity type impurity, and then activating the second conductivity type impurity while diffusing it downward by heat treatment, thereby forming a junction depth higher than that of the first base region. Forming the second base region so as to increase the depth of the silicon carbide semiconductor device. 11. A semiconductor substrate (1) of a first conductivity type having a main surface and a back surface opposite to the main surface and made of single-crystal silicon carbide, formed on a main surface of the semiconductor substrate, A first conductivity type semiconductor layer having a lower impurity concentration than the semiconductor substrate; a second conductivity type base region formed in a surface portion of the semiconductor layer; and a surface portion of the base region. A first conductivity type source region (4) formed on the substrate; a gate insulating film (7) formed on the channel region to form a channel region between the source region and the semiconductor layer; A gate electrode (8) formed on the gate insulating film; a source electrode (10) formed to contact the base region and the source region; and a drain electrode formed on the back surface of the semiconductor substrate. (1
1) in the method of manufacturing a silicon carbide semiconductor device, wherein the step of forming the base region includes the step of: ion-implanting a second conductivity type impurity into a surface layer portion of the semiconductor layer; Activating the impurity while diffusing impurities to form the first base region; and implanting an inert ion species into a surface layer of the semiconductor layer, and implanting the inert ion species into a region where the inert ion species is implanted. A second conductivity type impurity is ion-implanted at a predetermined concentration ratio with respect to the inactive ion species, and thereafter, the second ion is implanted by heat treatment.
Activating while suppressing diffusion of the conductive type impurity,
Forming the second base region so that the impurity concentration is higher than that of the base region. 12. A semiconductor substrate of a first conductivity type having a main surface and a back surface opposite to the main surface and made of single-crystal silicon carbide; and the semiconductor substrate formed on the main surface of the semiconductor substrate. A first conductive type semiconductor layer having a lower impurity concentration than the first conductive type semiconductor layer, a second conductive type base region formed on a surface layer of the semiconductor layer, a gate insulating film formed on the base region, A gate electrode formed on a gate insulating film; and a first conductivity type source region formed on both sides of the channel region in a surface layer portion of the semiconductor layer so as to form a channel region below the gate electrode. And a drain region; a source electrode formed to contact the base region and the source region; and a drain electrode formed to contact the drain region. In the method for manufacturing a silicon carbide semiconductor device, in the step of forming the base region, a second conductivity type impurity is ion-implanted into a surface layer portion of the semiconductor layer, and then activated while diffusing the second conductivity type impurity by heat treatment. Forming the first base region by ion-implanting; ion-implanting an inert ion species into a surface portion of the semiconductor layer; and injecting the inert ion species into a region into which the inert ion species is implanted. Is ion-implanted with a second conductivity type impurity at a predetermined concentration ratio.
Activating while suppressing diffusion of the conductive type impurity,
Forming the second base region so that the impurity concentration is higher than that of the base region. 13. A step of arranging a mask material (51) having an opening at a portion where the source region is to be formed on the semiconductor layer, and ion-implanting a first conductivity type impurity using the mask material as a mask. Forming a source region; and ion-implanting a second conductivity type impurity using the mask material as a mask, and then diffusing the second conductivity type impurity laterally by heat treatment to form the first base region. 13. The method according to claim 11, further comprising the steps of:
3. The method for manufacturing a silicon carbide semiconductor device according to item 1. 14. A step of forming a concave portion penetrating the source region and reaching the first base region; ion-injecting an inert ion species into a region including the concave portion; Forming a second base region by ion-implanting the second conductivity-type impurity at a predetermined concentration ratio with respect to the second conductivity-type impurity, and activating the second conductivity-type impurity while suppressing diffusion of the second conductivity-type impurity by heat treatment. 14. The method according to claim 13, further comprising the steps of:
3. The method for manufacturing a silicon carbide semiconductor device according to item 1. 15. A semiconductor substrate (1) of a first conductivity type having a main surface and a back surface opposite to the main surface and made of single-crystal silicon carbide, and formed on the main surface of the semiconductor substrate; A first conductivity type semiconductor layer having a lower impurity concentration than the semiconductor substrate; a second conductivity type base region formed in a surface portion of the semiconductor layer; and a surface portion of the base region. A first conductivity type source region (4) formed on the substrate; a gate insulating film (7) formed on the channel region to form a channel region between the source region and the semiconductor layer; A gate electrode (8) formed on the gate insulating film; a source electrode (10) formed to contact the base region and the source region; and a drain electrode formed on the back surface of the semiconductor substrate. (1
1) In the method for manufacturing a silicon carbide semiconductor device provided with 1), in the step of forming the base region, an inert ion species is ion-implanted into a surface portion of the semiconductor layer, and the inert ion species is A second conductivity type impurity is ion-implanted into the region to be implanted at a predetermined concentration ratio with respect to the inactive ion species.
Activating while suppressing diffusion of the conductive type impurity,
Forming a base region of the second conductivity type, and ion-implanting the second conductivity type impurity, and then activating the second conductivity type impurity while diffusing it downward by heat treatment, thereby forming a junction depth higher than that of the first base region. Forming the second base region so as to increase the depth of the silicon carbide semiconductor device. 16. A semiconductor substrate of a first conductivity type having a main surface and a back surface opposite to the main surface and made of single-crystal silicon carbide; and the semiconductor substrate formed on the main surface of the semiconductor substrate. A first conductive type semiconductor layer having a lower impurity concentration than the first conductive type semiconductor layer, a second conductive type base region formed on a surface layer of the semiconductor layer, a gate insulating film formed on the base region, A gate electrode formed on a gate insulating film; and a first conductivity type source region formed on both sides of the channel region in a surface layer portion of the semiconductor layer so as to form a channel region below the gate electrode. And a drain region; a source electrode formed to contact the base region and the source region; and a drain electrode formed to contact the drain region. In the method for manufacturing a silicon carbide semiconductor device, in the step of forming the base region, an inert ion species is ion-implanted into a surface layer portion of the semiconductor layer, and the inert ion species is implanted into a region where the inert ion species is implanted. A second conductivity type impurity is ion-implanted at a predetermined concentration ratio with respect to the active ion species, and then the second ion is implanted by heat treatment.
Activating while suppressing diffusion of the conductive type impurity,
Forming a base region of the second conductivity type, and ion-implanting the second conductivity type impurity, and then activating the second conductivity type impurity while diffusing it downward by heat treatment, thereby forming a junction depth higher than that of the first base region. Forming the second base region so as to increase the depth of the silicon carbide semiconductor device. 17. The concentration ratio between the second conductivity type impurity and the inert ion species is set so that the inert ion species is 10 times or more the second conductivity type impurity. The method of manufacturing a silicon carbide semiconductor device according to claim 9, wherein: 18. In the first and second base region forming steps, the second conductivity type impurity is ion-implanted into both the first and second base region forming portions at the same time, and the second impurity is implanted by heat treatment. 18. The method of manufacturing a silicon carbide semiconductor device according to claim 9, wherein the first and second base regions are simultaneously formed by activating a conductive impurity. 19. The semiconductor device according to claim 9, wherein B (boron) is used as a second conductivity type impurity in the first and second base regions, and C (carbon) is used as the inactive ion species. 19. The method for manufacturing a silicon carbide semiconductor device according to any one of 18.