JPH10308510A - Silicon carbide semiconductor device and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a silicon carbide semiconductor device which can improve ON-resistance by improving channel mobility. SOLUTION: An n<-> -type silicon carbide epitaxial layer 2 is formed on a main surface of an n<+> -type silicon carbide semiconductor board 1, p-type silicon carbide base regions 3a, 3b with a specified depth are formed in a specified region of a surface layer of the n<-> -type silicon carbide epitaxial layer 2, and n<+> -type source regions 4a, 4b are formed in a specified region of a surface layer of the base regions 3a, 3b. A surface channel epitaxial layer 5 is arranged to connect the source regions 4a, 4b and the n<-> -type silicon carbide epitaxial layer 2 in a surface layer of the base regions 3a, 3b. A gate electrode 8 is formed in a surface of the surface channel epitaxial layer 5 through a gate insulation film 7. A source electrode 10 is formed to come into contact with the base regions 3a, 3b and the source regions 4a, 4b, and a drain electrode 11 is formed in a rear of the board 1.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a silicon carbide semiconductor device, and more particularly, to an insulated gate field effect transistor, and more particularly to a high power vertical MOSFET.

[0002]

2. Description of the Related Art In a silicon power switching element, the use of silicon, which is a material, has reached a limit in reducing breakdown. Substantial improvement can only be achieved by using a semiconductor with a higher breakdown region, such as silicon carbide (SiC). The critical electric field of silicon carbide is an order of magnitude higher than that of silicon (allowing a large doping layer and a thin drift region layer for a given breakdown voltage), resulting in a low on-resistance. In other words, the die size of the silicon carbide device can be reduced by about one digit or more compared to the case where a silicon device having the same on-resistance is used (M. Bha).
tnager and B. J. Baliga, IEEE Transacti
ons on Electron Devices 40, 645 (199
3)).

Further, the natural oxide of silicon carbide is SiO ₂
And is the only compound semiconductor. Thermal oxide is formed on the surface of the easily the silicon carbide by conventional methods, interfacial and bulk properties of the SiO ₂ is comparable to that of SiO ₂ grown on silicon (N.Tokura, K.H
ara, T .; Miyajima, H .; Fuma, and K. Hara, Jpn.
J. Appl. Phy. 34, 5567 (1995)).
Silicon carbide is a very good material when used as high speed / high voltage switching devices for electric vehicles, especially high power uni / bipolar devices (Hingorani and
K. E. FIG. Stahlkopf, Scientific American 26
9, 78 (1993)). Accordingly, high-performance power devices such as MOSFETs, IGBTs, MOS control thyristors or MOS integrated circuits having a MOS structure are manufactured using silicon carbide materials.

However, as expected with new material systems, some problems must be solved before such devices can be realized. Generally, two types of structures, a trench MOSFET and a planar MOSFET without a trench, are used for a power FET having a MOS structure. In silicon devices, trench MOSFET
The structure has already been theoretically and experimentally proven to be superior to the planar MOSFET structure (B.
J. Baliga, T. Syau, and P.S. Venkatraman, I
EEE Electoron Device Letter 13,427
(1992)). The trench MOSFET structure can achieve a low channel resistance and a high channel density even with a smaller surface area than the planar MOSFET.

FIG. 30 shows a conventional silicon carbide trench MOS.
FIG. 3 is a cross-sectional view showing an FET. In FIG. 30, n⁺Type charcoal
On the silicon nitride semiconductor substrate 60, n^-Type silicon carbide epitaxy
Char layer 61 and p^-Silicon carbide epitaxial layer 62
Are laminated, and p^-Of silicon carbide epitaxial layer 62
N in the layer⁺A mold source region 63 is formed. Ma
, P^-Through the silicon carbide epitaxial layer 62^-
Trench 64 reaching silicon carbide epitaxial layer 61
Is formed. The gate inside the trench 64
A gate electrode 66 is arranged via a gate insulating film 65,
The electrode 66 is covered with an insulating film 67. Also, p^-
-Type silicon carbide epitaxial layer 62 and n ⁺Type source area
When the source electrode 68 is arranged so as to be in contact with the region 63,
Originally, n⁺On the back surface of the silicon carbide semiconductor substrate 60
Electrode 69 is arranged.

In designing this structure, the impurity concentration of the channel formation region is determined by the epitaxial layer 62 because it is common to the p-type base region (p ⁻ -type silicon carbide epitaxial layer 62). In the design of the power MOSFET, the impurity concentration and the thickness of the p-type base region (62) are the main design parameters for determining the breakdown voltage, while the impurity concentration of the channel formation region is determined by the gate threshold voltage and the channel threshold. This is a design parameter for determining the resistance. Generally, polysilicon is used for the gate electrode 66, and the gate electrode 66 is separated from the channel region by interposing a gate insulating layer 65 (generally, SiO ₂ ). Turn-on and turn-off control is performed based on supply of an appropriate gate bias to the gate electrode 66. For example, when the conduction inversion layer is formed in the p-type channel region in response to the supply of the positive gate bias, turn-on occurs in the n-type enhancement MOSFET. In this inversion layer, the n ⁺ type source region 63 and the n type drain region (61) are electrically connected. Also, under the control of the polysilicon gate electrode 66 arranged along the side wall of the vertical trench 64, current flows vertically from the source electrode 68 to the drain electrode 69. Therefore, channel length is an important design parameter. This is because the channel length has a large effect on the on-resistance and the transconductance.

The critical electric field of 6H-SiC is about 2.6 Me
It has a value of V / cm. However, locally high electric fields can occur at the bottom of the trench 64 in this structure. The electric field in the oxide at the bottom of the trench 64 is three times higher (in terms of dielectric constant) than that of SiC,
That is, it is 7.8 MeV / cm. Therefore, the trench 6
If the quality of the oxide at the bottom of 4 is poor, it will be broken down by the electric field.

FIG. 31 shows a two-dimensional TMA MEDICI.
The electric field characteristics of a trench MOSFET when the withstand voltage is set to 500 volts using a simulator are shown. FIG.
In FIG. 1, the vertical axis represents the distance x from the substrate surface (see FIG. 30).
It is. It can be seen from FIG. 31 that the electric field is maximized at the bottom of the trench 64. As a result, the oxide at the bottom of the trench 64 causes a breakdown.

Also, for reliability reasons, the electric field in the oxide must be kept below about 3.0 MeV / cm. This is because the peak electric field in silicon carbide is limited to about 1 MeV / cm, which is 1/2 to 1/3 of the actual breakdown electric field of silicon carbide. Since the withstand voltage is determined by the square of the peak electric field, the maximum withstand voltage is 1
/ 4 to 1/9. The effect is further exacerbated by the electric field effect on the side surfaces of the trench 64. In addition, reactive ion etching (RIE) used to form a silicon carbide trench structure also causes crystal defects on the trench surface due to high energy ion bombardment, and this irregular trench surface (roughness) Causes the surface diffusion to reduce the surface mobility of the particles. The mobility of the surface of the inversion layer on the side wall of the trench formed by RIE is significantly lower than the mobility on the smoothed surface. Further, the surface roughness also reduces the breakdown voltage at the gate electrode / SiO ₂ and increases the leakage current between the source and the drain. Therefore, the element characteristics are greatly reduced due to these factors.

[0010] Considering these facts and looking at the planar MOSFET from another viewpoint, the planar MOSFET
Can be said to be a structure suitable for a silicon carbide power element. FIG.
FIG. 1 is a cross-sectional view showing a conventional silicon carbide planar MOSFET. 32, n ⁻ -type silicon carbide epitaxial layer 71 is stacked on n ⁺ -type silicon carbide semiconductor substrate 70, and p ⁻ -type silicon carbide by double diffusion is provided on the surface of n ⁻ -type silicon carbide epitaxial layer 71. A base region 72 and an n ⁺ type source region 73 are formed. In addition, n ^-
A gate electrode 75 is arranged on type silicon carbide epitaxial layer 71 with a gate insulating film 74 interposed therebetween.
5 is covered with an insulating film 76. Source electrode 77 is arranged in contact with p ⁻ -type silicon carbide base region 72 and n ⁺ -type source region 73, and drain electrode 78 is arranged on the back surface of n ⁺ -type silicon carbide semiconductor substrate 70.

Since silicon carbide has a very low diffusion coefficient, the diffusion method is not practical for silicon carbide.
^- type silicon carbide base region 72 and n ⁺ -type source region 73
Is formed by an ion implantation method. And, once implanted into the silicon carbide crystal, the dopant atoms occupy the interstices of the lattice and must be moved to alternative locations to be activated electronically. This activation is performed by high-temperature annealing in an inert atmosphere. In operation, when a positive bias is applied to polysilicon gate electrode 75, base region 72 at the interface between insulating film (SiO ₂ ) 74 and p ⁻ -type silicon carbide base region 72 is formed.
The surface of the surface inversion layer is formed, electrons, n ⁺
It flows from the type source region 73 along the inversion layer to the n ⁻ type drift region (71). Upon reaching the drift region (71), the electrons flow vertically to the bottom n ⁺ drain region (70).

However, the poor mobility of the surface inversion layer for electrons in the SiC material due to high oxide charge and Coulomb scattering from the state of the interface limits the channel mobility and consequently the planar type. It has been experimentally found that the on-resistance of the MOSFET increases. Further, poor thermal oxide grown on p ^- type silicon carbide base region 72 doped with impurities such as aluminum contains a high density of positive charges that result in unacceptable flat band shifts or high surface state densities ( B. J. Baliga, Microelectr
onic Engineering 28, 177 (1995)).

[0013]

SUMMARY OF THE INVENTION The present invention has been made in view of such circumstances, and has as its object to provide a silicon carbide semiconductor device capable of improving channel mobility and improving on-resistance. It is in.

[0014]

According to the first aspect of the present invention, a voltage is applied to the gate electrode to apply an electric field to the gate insulating film, thereby inducing a storage channel in the surface channel layer. Carriers flow between the gate electrode and the drain electrode.

Thus, the MOSFET operation mode is
The accumulation mode in which the channel is induced without inverting the conductivity type of the channel formation layer increases the channel mobility and improves the on-resistance compared to the inversion mode MOSFET in which the conductivity type is inverted and the channel is induced. In addition, the MOSFET can be operated with a low gate voltage.

Further, the impurity concentration of the base region and the impurity concentration of the surface channel layer can be controlled independently, and the influence of impurity scattering when carriers flow can be reduced by lowering the impurity concentration of the surface channel layer. . for that reason,
Channel mobility can be increased.

Here, as set forth in claim 8, in the silicon carbide semiconductor device according to claim 1, the surface channel layer is formed by epitaxial growth, and the semiconductor substrate, the silicon carbide epitaxial layer, and the base region are formed. It is preferable that silicon carbide forming the source region and silicon carbide of the surface channel layer have different crystal systems. For example, the semiconductor substrate, the silicon carbide epitaxial layer, the silicon carbide constituting the base region and the source region are hexagonal, and the silicon carbide of the surface channel layer is cubic.

Further, as described in claim 10, claim 1 is
In the silicon carbide semiconductor device described in the above, the surface channel layer is formed by epitaxial growth, and the silicon carbide forming the semiconductor substrate, the silicon carbide epitaxial layer, the base region, and the source region; The shape should be different.

Also, as described in claim 11, claim 1 is
Wherein the surface channel layer is formed by epitaxial growth, silicon carbide constituting the semiconductor substrate, the silicon carbide epitaxial layer, the base region and the source region is 6H, and the silicon carbide of the surface channel layer is Should be 3C.

When the silicon carbide polymorph of the surface channel layer formed by epitaxial growth is different from that on the substrate side, a device having high characteristics and high reliability is realized. It is possible to do.

Further, it is preferable that the thickness of a part of the base region is increased. This facilitates breakdown. Claim 13
As described in the above, in the silicon carbide semiconductor device according to the twelfth aspect, the impurity concentration of the portion where the thickness of the base region is increased may be higher than the impurity concentration of the portion where the thickness is small. This makes it easier to break down.

Also, as described in claim 14, claim 1
3. In the silicon carbide semiconductor device according to 2, a portion where the thickness of the base region is increased may be formed below the source region. In this case, the mask for forming the deep base region and the mask for forming the source region can be used in common during manufacturing.

In other words, the first conductive type semiconductor substrate made of single-crystal silicon carbide has a dopant concentration lower than that of the semiconductor substrate on the main surface of the first conductive type semiconductor substrate.
A silicon carbide epitaxial layer of a conductivity type is formed, and a first base region of a second conductivity type having a predetermined depth is formed in a predetermined region of a surface portion of the silicon carbide epitaxial layer. Then, a first conductivity type surface channel layer made of silicon carbide is arranged on the silicon carbide epitaxial layer, and a second region deeper than the first base region is formed in a predetermined region in the first base region.
A second base region of a conductivity type is formed, and a second base region forming mask is used to form, in a predetermined region of a surface layer portion of the first base region, a depth smaller than the depth of the first base region. A source region of the first conductivity type is formed. Thereafter, a gate electrode is formed on the surface of the surface channel layer with a gate insulating film interposed therebetween, and a source electrode in contact with the base region and the source region is formed.

As described above, the source region is formed using the second base region forming mask, and the mask can be shared. Also, as described in claim 15,
In the silicon carbide semiconductor device according to the twelfth aspect, a portion where the thickness of the base region is increased may be formed in a portion that does not overlap with the source region. This way,
It is hard to break.

Furthermore, as in the sixteenth aspect, in the silicon carbide semiconductor device according to the first aspect, it is preferable that the surface channel layer overlaps a part of the source region. By doing so, the contact area from the source region to the surface channel layer can be increased.

In this case, as a manufacturing method, a first conductive material having a lower dopant concentration than the semiconductor substrate is formed on the main surface of the first conductive type semiconductor substrate made of single crystal silicon carbide. Forming a second conductivity type base region having a predetermined depth in a predetermined region of a surface layer portion of the silicon carbide epitaxial layer; A first conductivity type source region shallower than the depth of the base region is formed. Then, a first conductivity type surface channel layer made of silicon carbide is epitaxially grown on the first conductivity type silicon carbide epitaxial layer, and an unnecessary surface is left in a state where the surface channel layer is left partially on the source region. Remove the channel layer. Further, a gate electrode is formed on the surface of the surface channel layer via a gate insulating film, and a source electrode that is in contact with the base region and the source region is formed.

Thus, the semiconductor device of claim 16 is manufactured.

[0028]

BEST MODE FOR CARRYING OUT THE INVENTION

(First Embodiment) An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 shows an n-channel type planar MOSFET (vertical power MOSFET) in this embodiment.
(ET) shows a sectional view. This device is suitable for application to a rectifier of an inverter or a vehicle alternator.

N⁺Type silicon carbide semiconductor substrate 1 has a hexagonal system
Silicon carbide is used. Note that n ⁺Type silicon carbide semiconductor
The substrate 1 may be cubic. Also, n⁺Type silicon carbide semiconductor
The body substrate 1 has an upper surface as a main surface 1a and an opposite surface to the main surface.
The lower surface is a back surface 1b. This n⁺Type silicon carbide semiconductor
Dopan lower than the substrate 1 on the main surface 1a of the body substrate 1
N with concentration^-Type silicon carbide epitaxial layer (hereinafter
Bottom, n^-2 (referred to as a silicon carbide epi layer)
You.

Here, the upper surfaces of n ⁺ -type silicon carbide semiconductor substrate 1 and n ^-- type silicon carbide epilayer 2 are (0001) Si surfaces. Alternatively, the upper surfaces of n ⁺ -type silicon carbide semiconductor substrate 1 and n ⁻ -type silicon carbide epitaxial layer 2 are
It may be an a-plane. In other words, when the (0001) Si plane is used, a low surface state density is obtained, and when the (1120) a plane is used, a crystal having a low surface state density and completely having no screw dislocation is obtained.

N^-In the surface layer of silicon carbide epilayer 2
In a predetermined area, p having a predetermined depth ^-Type silicon carbide base
Regions 3a and p^-Type silicon carbide base region 3b is separated
It is formed. Also, p^--Type silicon carbide base region 3
a in a predetermined region in the surface layer portion of the base region 3a
Also shallow n⁺The type source region 4a also has p^-Type silicon carbide
A predetermined area in the surface portion of the base area 3b includes a base
N shallower than region 3b ⁺Mold source region 4b is formed
I have. Furthermore, n⁺Mold source regions 4a and n⁺Type source area
N between region 4b^--Type silicon carbide epilayer 2 and p
^-N is provided on the surface of silicon-type silicon carbide base regions 3a and 3b.^-Type
The SiC layer 5 extends. That is, the base region 3
Source regions 4a, 4b and n at the surface portions of a, 3b^-
N so as to connect with silicon carbide epilayer 2^-Type SiC layer 5
Are located. This n^-Type SiC layer 5 is formed by epitaxy
Epitaxial film
The crystal of 4H, 6H, 3C is used. In addition, Epita
The crystal layer can form various crystals regardless of the underlying substrate.
It can be. When the device is operating, it
And functions as a channel formation layer. Hereinafter, n^-Type Si
The C layer 5 is called a surface channel epi layer.

Here, the dopant concentration of the surface channel epi layer 5 is as low as about 1 × 10 ¹⁵ cm ⁻³ to 1 × 10 ¹⁷ cm ⁻³ , and the n ⁻ type silicon carbide epi layer 2 and p ^-
Or lower than the dopant concentration of base type silicon carbide base regions 3a and 3b. Thereby, low on-resistance is achieved.

Further, p ^- type silicon carbide base regions 3a, 3
b, n ⁺ -type source region 4a, the surface portion of the 4b recess 6
a, 6b are formed. A gate insulating film (silicon oxide film) 7 is formed on the upper surface of the surface channel epi layer 5 and the upper surfaces of the n ⁺ -type source regions 4a and 4b. Further, a polysilicon gate electrode 8 is formed on the gate insulating film 7.
Are formed. The polysilicon gate electrode 8 is covered with an insulating film 9. LTO (Low T) as the insulating film 9
emperature oxide) film is used. A source electrode 10 is formed thereon, and the source electrode 10 includes n ⁺ type source regions 4a and 4b and p ⁻ type silicon carbide base region 3.
a, 3b. Drain electrode layer 11 is formed on back surface 1b of n ⁺ -type silicon carbide semiconductor substrate 1.

Next, a manufacturing process of the power planar type MOSFET will be described with reference to FIGS. First, as shown in FIG. 2, an n-type 4H or 6H or 3C-SiC substrate, that is, an n ⁺ -type silicon carbide semiconductor substrate 1 is prepared. Here, n ⁺ type silicon carbide semiconductor substrate 1 has a thickness of 400
μm, and the main surface 1a is (0001) Si plane or
The (1120) a plane. An n ^-- type silicon carbide epilayer 2 having a thickness of 5 μm is epitaxially grown on main surface 1a of substrate 1. In this example, the same crystal as that of the underlying substrate (1) is obtained from the n ⁻ -type silicon carbide epilayer 2, which becomes an n-type 4H or 6H or 3C—SiC layer.

Then, as shown in FIG. 3, an LTO film 20 is arranged in a predetermined region on n ⁻ -type silicon carbide epilayer 2, and Al (aluminum) is ion-implanted using this as a mask to form a p ⁻ -type film. Silicon carbide base regions 3a and 3b are formed.
The ion implantation conditions at this time are a temperature of 700 ° C. and a dose of 1 × 10 ¹⁶ cm ⁻² .

Further, after removing the LTO film 20, FIG.
As shown in, n ^- on the type silicon carbide epitaxial layer 2 n ^- the surface channel epi-layer 5 of the type epitaxially grown. The growth conditions at this time are as follows: SiH ₄ , C ₃ H
₈ , the growth temperature is 1600 ° C. using H ₂ .

Subsequently, as shown in FIG. 5, an LTO film 21 is disposed in a predetermined region on the surface channel epi layer 5, and N ₂ is ion-implanted using the LTO film 21 as a mask to form n ⁺ type source regions 4a and 4b. To form The ion implantation conditions at this time are 700 ° C. and the dose is 1 × 10 ¹⁶ cm ⁻² .

Then, after removing the LTO film 21, FIG.
As shown in FIG. 7, an LTO film 22 is arranged in a predetermined region on the surface channel epi layer 5 by using a photoresist method, and the n ⁺ -type source regions 4a, 4
The recesses 6a and 6b are formed by etching a part of b and the p ^- type silicon carbide base regions 3a and 3b. At this time,
CF ₄ + O ₂ is used as the RIE gas.

Further, after removing the LTO film 22, FIG.
As shown in FIG. 7, a gate insulating film (gate oxide film) 7 is formed on a substrate by wet oxidation. At this time, the ambient temperature is 1080 ° C.

Thereafter, as shown in FIG. 8, a polysilicon gate electrode 8 is deposited on the gate insulating film 7 by LPCVD. The film formation temperature at this time is 600 ° C. Subsequently, as shown in FIG. 9, after removing unnecessary portions of the gate insulating film 7, an insulating film 9 made of LTO is formed to cover the gate insulating film 7. More specifically, the film formation temperature is 425 ° C., and annealing is performed at 1000 ° C. after the film formation.

Then, as shown in FIG. 1, a source electrode 10 and a drain electrode 11 are arranged by metal sputtering at room temperature. After film formation, annealing at 1000 ° C. is performed.

As described above, the power planar type MOS
The FET is completed. Next, this power planar type MOS
The operation (operation) of the FET will be described. This MOSFET operates in the accumulation mode, and carriers in the surface channel epi layer 5 are p ⁻ -type silicon carbide base regions 3.
It is depleted by a potential generated by a difference in electrostatic potential between the a, 3b and the surface channel epi layer 5 and a difference in work function between the surface channel epi layer 5 and the polysilicon gate electrode 8. By applying a voltage to the polysilicon gate electrode 8, a potential caused by a difference in work function between the surface channel epi layer 5 and the polysilicon gate electrode 8 is changed. As a result, the state of the channel can be controlled.

That is, the work function potential of the polysilicon gate electrode 8 is set to the first work function potential, the work function potential of the p ^- type silicon carbide base regions 3a and 3b is set to the second work function potential, and the surface channel epi layer Assuming that the work function potential of No. 5 is the third work function potential, the first to third work function potentials can be adjusted so that n-type carriers are confined in the surface channel epilayer 5. That is, the first to third work function potentials are set so that n-type carriers (electrons) are confined in the surface channel epilayer 5 when the polysilicon gate electrode 8 is at a zero potential with respect to the drain region. That is, the surface channel epi layer 5 is depleted.

Returning to the description of the operation, in the off state, a depletion region is formed in surface channel epilayer 5 by the electric field created by p ⁻ -type silicon carbide base regions 3 a and 3 b and polysilicon gate electrode 8. When a positive bias is supplied to the polysilicon gate electrode 8 from this state, the n ⁺ -type source regions 4a and 4b switch to the n ⁻ -type at the interface between the gate insulating film (SiO ₂ ) 7 and the surface channel epi layer 5. A channel region extending in the direction of the drift region 2 is formed, and is switched on. At this time, electrons flow from the n ⁺ -type source regions 4 a and 4 b via the surface channel epi-layer 5 to the n ⁻ -type silicon carbide epi-layer 2 from the surface channel epi-layer 5. Then, n ^- type silicon carbide epilayer 2
When reaching the (drift region), the electrons flow vertically to n ⁺ -type silicon carbide semiconductor substrate 1 (n ⁺ drain).

As described above, by applying a positive voltage to the gate electrode 8, a storage channel is induced in the surface channel epilayer 5, and carriers flow between the source electrode 10 and the drain electrode 11.

The operation principle of this device is similar to that of a vertical channel JFET (BJ Baliga, “M.
odem Power Devices ", Kreiger Press, Malaba
r, Florida, 1992).

The device in the normally-off accumulation mode can withstand an avalanche breakdown state.
In this structure, in order to obtain a sufficient barrier height to prevent conduction between the source and the drain, the epitaxial layer 5 forming the channel must have a small thickness (on the order of submicron) or a concentration. Must be low. In other words, considering the ease of fabrication, the thickness is desirably thick from the point of uniformity, and the concentration is desirably high because impurities cannot be avoided in the apparatus. The maximum thickness of the epitaxial growth layer 5 used in the normally-off planar MOSFET design depends on its impurity concentration, Si
It depends on the O ₂ film thickness and the conductivity type of polysilicon used as the gate electrode.

[0049] To a 1000 volt minimize the on-resistance under the breakdown voltage of the device structure parameters, i.e., the thickness and the impurity concentration of the n-type surface channel epi-layer 5, p ^- type silicon carbide base regions 3a, 3b and the n ^- A two-dimensional element simulation was performed to optimize the impurity concentration of the type silicon carbide epilayer 2, and will be described below.

FIG. 10 shows the correlation between the breakdown voltage, the thickness of the n-type surface channel epilayer 5, and the impurity concentration. FIG.
0, a case where the polysilicon gate electrode 8 is doped with a p-type impurity and a case where the polysilicon gate electrode 8 is doped with an n-type impurity.
In the case where the polysilicon gate electrode 8 is doped with a p-type impurity,
1 × 10 ¹⁷ cm ⁻³ , 1 × 10 ¹⁶ c
m ⁻³ , 1 × 10 ¹⁵ cm ^−3, and when the polysilicon gate electrode 8 is doped with an n-type impurity, the impurity concentration of the surface channel epi layer 5 is 1 × 10 ¹⁶ cm ^−3.
-3 .

FIG. 10 shows that the breakdown voltage depends on the thickness of the surface channel epi layer 5. The voltage is
Depending on the conductivity type of the polysilicon used for the gate electrode 8, if the surface channel epi layer 5 has the same impurity concentration, the p-type polysilicon gate electrode 8 is superior to the n-type polysilicon gate electrode 8. (If the same withstand voltage and the same impurity concentration are used, the surface channel epi layer 5 can be made thicker.) That is, the withstand voltage is better when the conductivity type is opposite to that of the surface channel epilayer 5. This is because the expansion of the depletion layer can be promoted.

As described above, in this embodiment, most of the unresolved problems relating to the MOS interface, that is, the trench MOSFE
High surface state density at T, low channel mobility and high electric field can be accommodated. Also, since the electron mobility of the device operating in the accumulation mode is much higher than that of the device in the inversion layer mode, the on-resistance can be significantly reduced (SC Sun and JD Plummer, IEEE.T.
rans. Electron Device DE-27, 1497 (19
80)).

Further, by using n-type surface channel epilayer 5, the impurity concentration of the channel region and the impurity concentration of p ⁻ -type silicon carbide base regions 3a and 3b can be individually controlled. Therefore, a power MOSFET having a high withstand voltage, a low on-resistance, and a low threshold voltage can be obtained by individually controlling the impurity concentrations in different regions. That is,
In the design of the conventional SiC MOSFET shown in FIGS. 30 and 32, in order to obtain a power MOSFET having a high withstand voltage, a low on-resistance, and a low threshold voltage, the impurity concentration of the channel and the p base region cannot be individually controlled. However, this is possible in the device of the present embodiment.

Referring further to this point, in the planar MOSFET using the SiC material shown in FIG. 32, the base region 72 and the source region 73 are formed by ion implantation because the diffusion process cannot be applied. SiC / SiO ₂ formed by oxidizing oxidized SiC
At the interface, damage during ion implantation remains, the interface state density is high, and the channel mobility is low. In addition, since the p ⁻ type base region 72 serving as an inversion layer is ion-implanted with aluminum, its quality is low and improvement in mobility cannot be expected. On the other hand, in the present embodiment shown in FIG. 1, a clean interface can be obtained by forming the channel layer with the high-quality epitaxial layer 5.

In the above-described example, the case where the present invention is applied to an n-channel vertical MOSFET is described in addition to the structure of the present embodiment described above. However, in FIG. 1, the p-type and the n-type are replaced. The same effect can be obtained in a p-channel vertical MOSFET.

In place of the surface channel epi layer 5, an SiC layer by ion implantation may be used. That is, in FIG. 4, the epitaxial layer 5 was formed on the substrate. At this time, as shown in FIG. 11, N ₂ was ion-implanted into the SiC substrate, and the n ⁻ -type channel forming Si was formed in the surface layer of the substrate.
The C layer 25 may be formed. (Second Embodiment) Next, a second embodiment will be described with reference to the first embodiment.
The following description focuses on the differences from this embodiment.

FIG. 12 shows an n-channel type planar MOSFET (vertical power MOS) in this embodiment.
FET). In FIG. 12, n ⁻ -type silicon carbide epitaxial layer 2 having a lower dopant concentration than substrate 1 is stacked on main surface 1 a of n ⁺ -type silicon carbide semiconductor substrate 1. In a predetermined region in the surface portion of n ^-- type silicon carbide epilayer 2, ap ^-- type silicon carbide base region 3a and a p ^-- type silicon carbide base region 3b having a predetermined depth are formed separately. A predetermined region in the surface layer portion of p ⁻ -type silicon carbide base region 3a includes base region 3a
An n ⁺ -type source region 4a shallower than the base region 3b and an n ⁺ -type source region 4b shallower than the base region 3b are formed in a predetermined region in the surface portion of the p ^-- type silicon carbide base region 3b. Here, a part of the thickness is increased in the base regions 3a and 3b. That is, the deep base regions 30a and 30b are formed. This base area 3
a, 3b (deep base region 3
0a, 30b) is higher than the impurity concentration of the thin portion. The deep base regions 30a and 30b are formed below the source regions 4a and 4b.

[0058] Further, n between the n ⁺ -type source region 4a and the n ⁺ -type source region 4b ^- -type silicon carbide epitaxial layer 2 of the surface portion and p ^- type silicon carbide base region 3a, n on the surface of the 3b ^{A −} type SiC layer (surface channel epi layer) 5 is extended. n ^- type SiC layer (surface channel epi layer)
5 is formed by epitaxial growth,
When the device operates, it functions as a channel forming layer on the device surface.

Here, semiconductor substrate 1, n ⁻ -type silicon carbide epilayer 2, base regions 3a and 3b, and source regions 4a and 4b
6H-SiC is used for silicon carbide, and 3C-SiC is used for surface channel epilayer 5.

Further, p ^- type silicon carbide base regions 3a, 3
The concave portions 6 are provided on the surface portions of the b, n ⁺ type source regions 4a, 4b.
a, 6b are formed. A gate insulating film (silicon oxide film) 7 is formed on the upper surface of the surface channel epi layer 5 and the upper surfaces of the n ⁺ -type source regions 4a and 4b. Further, a polysilicon gate electrode 8 is formed on the gate insulating film 7.
Is formed, and the polysilicon gate electrode 8 is covered with an insulating film 9. A source electrode 10 is formed thereon,
The source electrode 10 has n ⁺ type source regions 4a, 4b and p
^- type silicon carbide base regions 3a, is in contact with 3b. Drain electrode layer 11 is formed on back surface 1b of n ⁺ -type silicon carbide semiconductor substrate 1.

Next, this power planar type MOSFET
Will be described with reference to FIGS. First, as shown in FIG. 13, an n-type 6H—SiC substrate, that is, an n ⁺ -type silicon carbide semiconductor substrate 1 is prepared.
A 5 μm-thick n ⁻ -type silicon carbide epilayer 2 is epitaxially grown on main surface 1a of FIG. In this example, the n ⁻ -type silicon carbide epi layer 2 has the same crystal as that of the underlying substrate (1) and becomes an n-type 6H—SiC layer.

Then, as shown in FIG. 14, an LTO film 20 is arranged in a predetermined region on n ⁻ -type silicon carbide epilayer 2,
Using this as a mask, Al (aluminum) is ion-implanted to form p ⁻ -type silicon carbide base regions 3a and 3b.

Further, after removing the LTO film 20, FIG.
As shown in FIG. 5, an n ⁻ type surface channel epi layer 5 is epitaxially grown on the n ⁻ type silicon carbide epi layer 2 using a CVD apparatus. The growth conditions at this time are as follows: SiH ₄ , C ₃ H ₈ , H ₂ are used as source gases, and SiH _4
The flow rate ratio of ₄ / C ₃ H ₆ is set to “0.5”. The growth temperature is set to 1300 ° C. Thus, a 3C-SiC surface channel epilayer 5 is obtained. That is, the temperature is lowered to 1300 ° C. from 1500 ° C., and SiH ₄ / C
_The 3C—SiC surface channel epilayer 5 is obtained by forming the film while setting the flow rate ratio of ₃ H ₆ to “0.5”, which is usually “1”. That is, the 3C-SiC {111} plane is formed on the {0001} plane of 6H-SiC.

Subsequently, as shown in FIG. 16, aluminum is ion-implanted in a state in which a mask (LTO film or the like) 31 is arranged on the surface channel epilayer 5 and the deep base region 3 is formed.
0a and 30b are formed.

Further, as shown in FIG. 17, N ₂ is ion-implanted using the aforementioned mask 31 to form n ⁺ -type source regions 4a and 4b. Then, after removing the mask 31, as shown in FIG. 18, the LTO film 22 is formed in a predetermined region on the surface channel epi layer 5 by using a photoresist method.
Are used as a mask, and a part of n ⁺ -type source regions 4a and 4b and p ⁻ -type silicon carbide base regions 3a and 3b are etched by RIE to form concave portions 6a and 6b.

Further, after removing the LTO film 22, FIG.
As shown in FIG. 9, a gate insulating film (gate oxide film) 7 is formed on the substrate by wet oxidation. Thereafter, a polysilicon gate electrode 8 is formed on the gate insulating film 7 by LPCVD.
Is deposited.

Subsequently, as shown in FIG. 20, after removing unnecessary portions of the gate insulating film 7, an insulating film 9 made of LTO is formed to cover the polysilicon gate electrode 8. And
As shown in FIG. 12, a source electrode 10 and a drain electrode 11 are arranged by metal sputtering at room temperature. After film formation, annealing at 1000 ° C. is performed.

As described above, the power planar type MOS
The FET is completed. This power planar type MOSFET
Is turned off, the work function difference between the polysilicon gate electrode 8 and the surface channel epi layer 5 and the depletion due to the pn junction between the p ^- type silicon carbide base regions 3a and 3b and the surface channel epi layer 5 cause pinch off.

On the other hand, when a voltage is applied to the polysilicon gate electrode 8, the transistor is turned on in the accumulation mode in which carriers are accumulated in the surface channel epi layer 5. In the ON state, electrons flow from n ⁺ type source regions 4a and 4b via surface channel epi layer 5 to n ⁻ type silicon carbide epi layer 2 from surface channel epi layer 5, and n ⁻ type silicon carbide epi layer 2 (Drift region), the electrons are transferred to the n ⁺ type silicon carbide semiconductor substrate 1.
It flows vertically to (n ⁺ drain).

At this time, in this embodiment, the substrate side Si
Since 3C-SiC having high mobility is used as the surface channel epilayer 5 separately from C, the transistor characteristics (on-resistance) of the FET can be remarkably improved. Loss can be greatly reduced.

That is, when a surface channel epilayer 5 of the same polymorph / crystal system is grown on the substrate-side SiC (for example, a 6H-SiC epitaxial layer is formed on a 6H-SiC substrate, or a 4H-SiC 4H-Si on the substrate
In the case of forming a C epitaxial layer), generally, 4H-SiC having good characteristics is used.
The quality of the substrate is poor and the quality of even the epitaxial layer deteriorates. On the other hand, by using a polymorph / crystal system of the surface channel epilayer 5 different from that of the substrate side, a SiC semiconductor device having high characteristics and high reliability can be obtained.

The substrate side SiC (1, 2, 3a, 3b,
4a, 4b) and the polymorph / crystal combination of the surface channel epilayer 5 include a 6H-SiC substrate and a 3C-SiC
In addition to the combination of the epitaxial layers 5, for example, 6
H-SiC substrate and 4H-SiC epitaxial layers 5, 4
Various combinations such as an H-SiC substrate and a 3C-SiC epitaxial layer 5 are possible.

In the base regions 3a and 3b,
Base regions 30a and 30b are formed and the base region 3
a, 3b is partly thicker,
N below base regions 30a, 30b^-Type silicon carbide epilayer
2 becomes thinner (n ⁺Type silicon carbide semiconductor substrate
1 and the distance between the deep base regions 30a and 30b are short.
No, it becomes easier to break down. Also, deep
Impurity concentration of the source regions 30a and 30b
Is higher than the impurity concentration of
It becomes easy to go down. Further, the deep base region 30
a and 30b are formed below the source regions 4a and 4b.
Therefore, as shown in FIGS.
Can be achieved.

As described above, this embodiment has the following features. (A) The silicon carbide forming the semiconductor substrate 1, the n ⁻ -type silicon carbide epilayer 2, the base regions 3a and 3b, and the source regions 4a and 4b is 6H, and the silicon carbide of the surface channel epilayer 5 is 3H.
C. That is, silicon carbide forming semiconductor substrate 1, n ⁻ -type silicon carbide epilayer 2, base regions 3a and 3b, and source regions 4a and 4b is hexagonal and surface channel epilayer 5
Is cubic. In other words, the semiconductor substrate 1
And silicon carbide forming n ⁻ -type silicon carbide epilayer 2, base regions 3a and 3b and source regions 4a and 4b, and polymorph of silicon carbide in surface channel epilayer 5 are different.

As described above, the polymorphism of the surface channel epi layer 5
By using a crystal system different from that on the substrate side, a SiC semiconductor device having high characteristics and high reliability can be obtained. (B) Since the deep base regions 30a and 30b in which the thicknesses of the base regions 3a and 3b are partially increased are provided, breakdown becomes easy. (C) Since the impurity concentration of the deep base regions 30a and 30b is higher than the impurity concentration of the thin portion, the breakdown is further facilitated. (D) Since the deep base regions 30a and 30b (the portions where the thickness of the base region is increased) are formed below the source regions 4a and 4b, a deep base as shown in FIGS. The mask 31 in which the region forming mask and the source region forming mask are shared can be used, and the planar MOSFET shown in FIG.
Can be manufactured.

In other words, n ^- type silicon carbide epilayer 2 is formed on main surface 1a of semiconductor substrate 1 as shown in FIG.
As described above, base regions 3a and 3b having a predetermined depth are formed in predetermined regions of the surface layer portion of n ^- type silicon carbide epilayer 2. Then, surface channel epilayer 5 is arranged on n ⁻ -type silicon carbide epilayer 2 as shown in FIG. 15, and base region 3 is formed in predetermined regions in base regions 3a and 3b as shown in FIG.
Deep base regions 30a, 30b deeper than a, 3b
Further, using the deep base region forming mask 31 as shown in FIG. 17, source regions 4a, 4b shallower than the depths of the base regions 3a, 3b are formed in predetermined regions of the surface portions of the base regions 3a, 3b. To form Thereafter, a gate electrode 8 is formed on the surface of the surface channel epi layer 5 with a gate insulating film 7 interposed therebetween, and a source electrode 10 is formed in contact with the base regions 3a, 3b and the source regions 4a, 4b.

In this manner, the source regions 4a and 4b are formed using the deep base region forming mask 31, and the mask can be shared. (Third Embodiment) Next, a third embodiment will be described with reference to a second embodiment.
The following description focuses on the differences from this embodiment.

FIG. 21 shows an n-channel type planar MOSFET (vertical power MOS) according to this embodiment.
FET). In FIG. 21, portions where the thicknesses of the base regions 3a and 3b are increased, that is, the deep base regions 30c and 30d are formed at positions not overlapping with the source regions 4a and 4b. This makes it difficult to break.

The reason will be described. The breakdown occurs in the deep base regions 30c and 30d, and a breakdown current flows between the source electrode 10 and the drain electrode 11. At this time, the source region in the path of flow of the breakdown current is present, a voltage drop occurs in the source region, p-type base region 3a, the pn junction between 3b is forward biased, thereby the n ^- type silicon carbide epitaxial layer 2 An npn transistor including the base region 3a (3b) and the source region 4a (4b) operates to generate a large current, and the element may be heated, resulting in a state unfavorable in reliability.
Therefore, such a situation can be avoided by removing the source regions 4a and 4b from the path where the breakdown current mainly flows as in the present embodiment.

As described above, this embodiment has the following features. (A) The thickened portions (deep base regions 30c, 30d) of the base regions 3a, 3b are provided at locations that do not overlap with the source regions 4a, 4b, so that they are not easily broken. Can be. (Fourth Embodiment) Next, a fourth embodiment will be described with reference to the first embodiment.
The following description focuses on the differences from this embodiment.

FIG. 22 shows an n-channel type planar MOSFET (vertical power MOS) in this embodiment.
FET). In FIG. 22, n ⁻ -type SiC layer 40 extends on the surface of n ⁻ -type silicon carbide epilayer 2. In other words, n ⁻ -type SiC layer 40 is arranged so as to connect source regions 4a, 4b and n ⁻ -type silicon carbide epitaxial layer 2 on the surface portions of base regions 3a, 3b. The n ⁻ -type SiC layer 40 is formed by epitaxial growth, and the crystal of the epitaxial film is 3C. Further, the n ⁻ -type SiC layer 40 functions as a channel forming layer on the device surface during operation of the device. This n ⁻ -type SiC layer 40 is called a surface channel epi layer.

As described above, the surface channel epi layer 40 overlaps the partial region S of the source regions 4a and 4b. More precisely, the surface channel epilayer 40 comprises the source region 4
a, 4b are not covered entirely.

The other configuration is the same as that of FIG. 1, and the description thereof will be omitted by retaining the same reference numerals. Next, a manufacturing process of the power planar type MOSFET will be described with reference to FIGS.

First, as shown in FIG. 23, n-type 6H-S
An iC substrate, that is, an n ⁺ -type silicon carbide semiconductor substrate 1 is prepared, and a 5 μm-thick n ⁻ -type silicon carbide epitaxial layer 2 is epitaxially grown on main surface 1 a of this substrate 1. In this example, n
^The- type silicon carbide epilayer 2 has the same crystal as that of the underlying substrate (1) and becomes an n-type 6H-SiC layer.

Then, as shown in FIG. 24, LTO film 20 is arranged in a predetermined region on n ⁻ -type silicon carbide epilayer 2,
Using this as a mask, Al (aluminum) is ion-implanted to form p ⁻ -type silicon carbide base regions 3a and 3b.

Further, after removing the LTO film 20, FIG.
As shown in FIG. 5, an LTO film 41 is arranged in a predetermined region on the n ⁻ -type silicon carbide epilayer 2, and N ₂ is ion-implanted using the LTO film 41 as a mask to form n ⁺ -type source regions 4a and 4b. .

Then, after removing the LTO film 41, FIG.
As shown in 6, n ^- on the type silicon carbide epitaxial layer 2 n ^- type surface channel epi-layer 40 is epitaxially grown.
The growth conditions at this time are as follows: SiH ₄ , C
₃ H ₈ and H ₂ are used, and the flow rate ratio of SiH ₄ / C ₃ H ₆ is set to “0.5”. The growth temperature is set to 1300 ° C. Thereby, the 3C-SiC surface channel epilayer 40
Get.

Subsequently, as shown in FIG. 27, the unnecessary surface channel epi layer 40 is removed. That is, a mask material M such as a photoresist material, a SiO ₂ film, and a SiN film is formed, and the unnecessary surface channel epi layer 40 is removed by dry etching (for example, RIE). Further, the surface channel epi layer 40 can be converted to an oxide film by thermal oxidation and removed by using the mask material M as a SiN film. Also,
When the surface channel epi layer 40 is removed by dry etching, the n ⁺ -type source region 4 exposed by etching is removed.
Although the surfaces of a, 4b and p ⁻ type silicon carbide base regions 3a, 3b are roughened by dry etching, such roughened surfaces can be removed by thermal oxidation.

After that, as shown in FIG. 22, a gate insulating film (gate oxide film) 7 is formed. Thereafter, a polysilicon gate electrode 8 is deposited on the gate insulating film 7 by LPCVD. Subsequently, an insulating film 9 made of LTO is formed to cover the gate insulating film 7. Then, the source electrode 10 and the drain electrode 11 are formed by metal sputtering at room temperature.
Place. After film formation, annealing at 1000 ° C. is performed.

As described above, the power planar type MOS
The FET is completed. This power planar type MOSFET
Is turned off due to a work function difference between the polysilicon gate electrode 8 and the surface channel epi layer 40 and depletion due to a pn junction between the p ⁻ -type silicon carbide base regions 3a and 3b and the surface channel epi layer 40.

On the other hand, when a voltage is applied to the polysilicon gate electrode 8, it is turned on in an accumulation mode in which carriers are accumulated in the surface channel epi layer 40. In the on state, electrons flow from n ⁺ -type source regions 4a and 4b through surface channel epi layer 40 to n ⁻ -type silicon carbide epi layer 2 from surface channel epi layer 40, and n ⁻ -type silicon carbide epi layer 2 When reaching the (drift region), the electrons flow vertically to n ⁺ -type silicon carbide semiconductor substrate 1 (n ⁺ drain).

Here, the contact area S between the source regions 4a and 4b and the surface channel epi layer 40 is the contact area, and the contact area to the surface channel epi layer 40 can be increased as compared with the structure of FIG.

As described above, this embodiment has the following features. (A) The surface channel epi layer 40 is formed of the source regions 4a and 4b.
, The contact area from the source regions 4a and 4b to the surface channel epi layer 40 can be increased. As a method for producing (ii) In this case, on the main surface of the semiconductor substrate 1 as shown in FIG. 23, n ^- -type silicon carbide epitaxial layer 2 is formed, the n as shown in Figure 24 ^- type silicon carbide epitaxial layer 2 Base regions 3a and 3b having a predetermined depth are formed in predetermined regions of the surface layer portion, and as shown in FIG.
Source regions 4a and 4b shallower than the depths of the base regions 3a and 3b are formed in a predetermined region of the surface layer portion b. And
A surface channel epilayer 40 is epitaxially grown on n ⁻ -type silicon carbide epilayer 2 as shown in FIG. 26, and surface channel epilayer 40 is left partially on source regions 4a and 4b as shown in FIG. Unnecessary surface channel epilayer 40 in the state
Is removed. Further, as shown in FIG. 22, a gate electrode 8 is formed on the surface of the surface channel epi layer 40 with a gate insulating film 7 interposed therebetween, and a source electrode 10 which is in contact with the base regions 3a, 3b and the source regions 4a, 4b is formed. .
By doing so, the semiconductor device (a) is manufactured.

The following may be applied as an application example of the present embodiment. As shown in FIG.
In a and 3b, a part of the thickness is increased. That is, the deep base regions 50a and 50b are formed. The impurity concentration of the thickened base regions 3a and 3b (deep base regions 50a and 50b) is higher than the impurity concentration of the thinned portions. The deep base regions 50a and 50b are formed below the source regions 4a and 4b.

Further, similarly to the first and second embodiments, recesses 6a and 6b may be formed in the source regions 4a and 4b to make contact with the source electrode 10.
By doing so, the contact area with the electrode is increased by the amount of the recesses 6a and 6b.

Alternatively, as shown in FIG. 29, in base regions 3a and 3b, deep base regions 50c and 50d having a partly large thickness are formed, and deep base regions 50c and 50d are formed in source regions 4a and 50b. 4b is formed at a location that does not overlap with 4b. This makes it difficult to break.

Also, the crystal system and polymorph of silicon carbide forming semiconductor substrate 1, n ⁻ -type silicon carbide epilayer 2, base regions 3a and 3b and source regions 4a and 4b, and silicon carbide of surface channel epilayer 40 May have the same crystal system and polymorph.

[Brief description of the drawings]

FIG. 1 is a schematic cross-sectional view of a power planar type MOSFET according to a first embodiment.

FIG. 2 is a cross-sectional view for explaining a manufacturing process of the power planar type MOSFET.

FIG. 3 is a cross-sectional view for explaining a manufacturing process of the power planar MOSFET.

FIG. 4 is a cross-sectional view for explaining a manufacturing process of the power planar MOSFET.

FIG. 5 is a sectional view for explaining a manufacturing process of the power planar type MOSFET.

FIG. 6 is a cross-sectional view for explaining a manufacturing process of the power planar MOSFET.

FIG. 7 is a sectional view for explaining a manufacturing process of the power planar type MOSFET.

FIG. 8 is a sectional view for explaining a manufacturing process of the power planar type MOSFET.

FIG. 9 is a cross-sectional view for explaining a manufacturing process of the power planar MOSFET.

FIG. 10 is an explanatory diagram showing the relationship between the thickness of the surface channel epi layer and the breakdown voltage.

FIG. 11 is a cross-sectional view for explaining a manufacturing process of another example of the power planar MOSFET in the first embodiment.

FIG. 12 is a schematic sectional view of a power planar type MOSFET according to a second embodiment.

FIG. 13 is a cross-sectional view for explaining a manufacturing process of the power planar MOSFET.

FIG. 14 is a cross-sectional view for explaining a manufacturing process of the power planar MOSFET.

FIG. 15 is a cross-sectional view for explaining a manufacturing process of the power planar MOSFET.

FIG. 16 is a cross-sectional view for explaining a manufacturing process of the power planar MOSFET.

FIG. 17 is a cross-sectional view for explaining a manufacturing process of the power planar MOSFET.

FIG. 18 is a cross-sectional view for explaining a manufacturing process of the power planar MOSFET.

FIG. 19 is a cross-sectional view for explaining a manufacturing step of the power planar MOSFET.

FIG. 20 is a cross-sectional view for explaining a manufacturing process of the power planar MOSFET.

FIG. 21 is a schematic sectional view of a power planar MOSFET according to a third embodiment.

FIG. 22 is a schematic cross-sectional view of a power planar MOSFET according to a fourth embodiment.

FIG. 23 is a cross-sectional view for explaining a manufacturing process of the power planar MOSFET.

FIG. 24 is a cross-sectional view for explaining a manufacturing step of the power planar MOSFET.

FIG. 25 is a cross-sectional view for explaining a manufacturing step of the power planar MOSFET.

FIG. 26 is a cross-sectional view for explaining a manufacturing step of the power planar MOSFET.

FIG. 27 is a cross-sectional view for explaining a manufacturing process of the power planar MOSFET.

FIG. 28 is a sectional view for explaining a manufacturing process of another example of the power planar MOSFET in the fourth embodiment;

FIG. 29 is a cross-sectional view for explaining a manufacturing process of another power planar MOSFET according to the fourth embodiment;

FIG. 30 shows a trench type MO for explaining the prior art.
FIG. 2 is a schematic cross-sectional view of an SFET.

FIG. 31 is an explanatory diagram showing a relationship between an electric field and a distance.

FIG. 32 is a planer-type MO for explaining a conventional technique.
FIG. 2 is a schematic cross-sectional view of an SFET.

[Explanation of symbols]

 1 ... n⁺Type silicon carbide semiconductor substrate, 2 ... n^-Type silicon carbide
P layer, 3a, 3b ... p ^-Type silicon carbide base region, 4a,
4b ... n⁺Type source region, 5 ... surface channel epi layer, 7
... gate insulating film, 8 ... polysilicon gate electrode, 10 ...
Source electrode, 11 ... Drain electrode, 30a, 30b, 3
0c, 30d: deep base region, 31: mask, 4
0: surface channel epi layer, 50a, 50b, 50c, 5
0d: Deep base area.

 ────────────────────────────────────────────────── ─── Continuing on the front page (72) Kunihiko Hara 1-1-1, Showa-cho, Kariya-shi, Aichi Prefecture Inside DENSO Corporation

Claims (18)

[Claims] 1. A semiconductor substrate of a first conductivity type having a main surface and a back surface opposite to the main surface and made of single-crystal silicon carbide; and a semiconductor substrate formed on the main surface of the semiconductor substrate, A first conductivity type silicon carbide epitaxial layer having a low dopant concentration; a second conductivity type base region formed in a predetermined region of a surface portion of the silicon carbide epitaxial layer and having a predetermined depth; A source region of a first conductivity type formed in a predetermined region of a surface layer portion and shallower than a depth of the base region; and connecting the source region and the silicon carbide epitaxial layer of the first conductivity type at a surface portion of the base region. A first conductivity type surface channel layer made of silicon carbide, a gate insulating film formed on the surface of the surface channel layer, and formed on the gate insulating film. A silicon carbide semiconductor device comprising: a gate electrode, a source electrode formed in contact with the base region and the source region, and a drain electrode formed on a back surface of the semiconductor substrate. 2. The silicon carbide semiconductor device according to claim 1, wherein said gate electrode is a polysilicon gate electrode, and said polysilicon gate electrode is of a conductivity type opposite to said surface channel layer. 3. The silicon carbide semiconductor device according to claim 1, wherein a main surface of said silicon carbide semiconductor substrate is a (0001) Si plane having a low surface state density or a low surface state density, and A silicon carbide semiconductor device having a (112 bar 0) a-plane which is a crystal having no screw dislocation. 4. The silicon carbide semiconductor device according to claim 1, wherein a dopant concentration of said surface channel layer is lower than a dopant concentration of said silicon carbide epitaxial layer and a base region. 5. The silicon carbide semiconductor device according to claim 1, wherein said gate electrode has a first work function potential, said base region has a second work function potential, and said surface channel layer is A silicon carbide semiconductor device having a third work function potential, wherein the first, second, and third work function potentials are set so as to confine carriers of a first conductivity type in the surface channel layer. 6. The silicon carbide semiconductor device according to claim 5, wherein said first, second and third work function potentials are different from each other when said gate electrode is at zero potential with respect to a drain region. A silicon carbide semiconductor device configured to contain a carrier of the first conductivity type in a layer. 7. The silicon carbide semiconductor device according to claim 1, wherein said surface channel layer is formed by epitaxial growth or ion implantation. 8. The silicon carbide semiconductor device according to claim 1, wherein said surface channel layer is formed by epitaxial growth, and said semiconductor substrate, silicon carbide epitaxial layer, silicon carbide forming base region and source region, A silicon carbide semiconductor device in which the surface channel layer has a different silicon carbide crystal system. 9. The silicon carbide semiconductor device according to claim 8, wherein the semiconductor substrate, the silicon carbide epitaxial layer, the silicon carbide forming the base region and the source region are hexagonal, and the silicon carbide of the surface channel layer is A cubic silicon carbide semiconductor device. 10. The silicon carbide semiconductor device according to claim 1, wherein said surface channel layer is formed by epitaxial growth, and said semiconductor substrate, a silicon carbide epitaxial layer, a silicon carbide forming a base region, and a source region. A silicon carbide semiconductor device in which the surface channel layer has different polymorphs of silicon carbide. 11. The silicon carbide semiconductor device according to claim 1, wherein said surface channel layer is formed by epitaxial growth, and silicon carbide forming said semiconductor substrate, silicon carbide epitaxial layer, base region and source region is formed. 6H, wherein the silicon carbide of the surface channel layer is 3C. 12. The silicon carbide semiconductor device according to claim 1, wherein a thickness of a part of said base region is increased. 13. The silicon carbide semiconductor device according to claim 12, wherein an impurity concentration of a portion where the thickness of the base region is increased is set to:
A silicon carbide semiconductor device having a higher impurity concentration than a thin portion. 14. The silicon carbide semiconductor device according to claim 12, wherein a portion where the thickness of said base region is increased is formed below said source region. 15. The silicon carbide semiconductor device according to claim 12, wherein a portion where the thickness of the base region is increased is formed at a portion that does not overlap with the source region. 16. The silicon carbide semiconductor device according to claim 1, wherein said surface channel layer overlaps a partial region of said source region. 17. A step of forming a first conductivity type silicon carbide epitaxial layer having a lower dopant concentration than a semiconductor substrate on a main surface of a first conductivity type semiconductor substrate made of single crystal silicon carbide; In a predetermined region of the surface portion of the silicon epitaxial layer,
Forming a first base region of a second conductivity type having a predetermined depth; disposing a surface channel layer of a first conductivity type made of silicon carbide on the silicon carbide epitaxial layer; Forming a second base region of a second conductivity type deeper than the first base region in a predetermined region in the first base region; and forming the first base region using the second base region forming mask.
Forming a first conductivity type source region shallower than a depth of the first base region in a predetermined region of a surface layer portion of the base region; and forming a gate electrode on a surface of the surface channel layer via a gate insulating film. And forming a source electrode in contact with the base region and the source region. 18. A step of forming a first conductivity type silicon carbide epitaxial layer having a lower dopant concentration than a semiconductor substrate on a main surface of a first conductivity type semiconductor substrate made of single crystal silicon carbide; In a predetermined region of the surface portion of the silicon epitaxial layer,
Forming a second conductivity type base region having a predetermined depth, and forming a first conductivity type source region shallower than a depth of the base region in a predetermined region of a surface layer portion of the base region; A step of epitaxially growing a surface channel layer of the first conductivity type made of silicon carbide on the silicon carbide epitaxial layer of the one conductivity type; Removing a channel layer; forming a gate electrode on the surface of the surface channel layer via a gate insulating film; and forming a source electrode in contact with the base region and the source region. Manufacturing method of a semiconductor device.