JP2016152319A - Power semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a power semiconductor device such as a MOSFET, achieving a low on-resistance and a high withstand voltage.SOLUTION: First to third drain regions 101, 103, 102 having a first conductivity type are formed of first to third semiconductor materials, respectively. The second drain region 103 and the third drain region 102 are provided, in the order, on the first drain region 101. When the first conductivity type is an n-type, energy at a conduction band end of the second semiconductor material is lower than that at a conduction band end of the first semiconductor material, and energy at a conduction band end of the third semiconductor material is lower than that at a conduction band end of the second semiconductor material.SELECTED DRAWING: Figure 5

Description

  The present invention relates to a power semiconductor device, and more particularly to a power semiconductor device having a heterojunction.

  In designing a power semiconductor device such as a MOSFET (Metal Oxide Semiconductor Field Effect Transistor), there is usually a trade-off between two characteristics of a low on-resistance and a high breakdown voltage. Since both characteristics are important characteristics for the power semiconductor device, methods for obtaining both excellent characteristics at the same time have been actively studied. As one of typical methods, a semiconductor material that constitutes a part responsible for a switching function according to application of a gate voltage and a semiconductor material that constitutes an important part for obtaining a high breakdown voltage are individually selected and There is a method in which two different semiconductor materials are joined by a heterojunction.

  For example, according to Japanese Patent Application Laid-Open No. 2004-327891, a semiconductor device has first and second field effect transistors. The first field effect transistor includes a first drain region, a first source region, and a first gate region formed in the first semiconductor layer. The second field effect transistor includes a second drain region, a second source region, and a second gate region formed in a second semiconductor layer having a band gap different from that of the first semiconductor layer. Silicon is used for the material of the second semiconductor layer forming the second field effect transistor responsible for the switching function, while the material of the first semiconductor layer forming the first field effect transistor is carbonized having excellent breakdown voltage characteristics. Silicon is used. The first source region and the second drain region form a heterojunction. The heterojunction is made ohmic by sufficiently increasing the impurity concentration.

JP 2004-327891 A

  Although details will be described later, according to the study of the present inventor, if the impurity concentration of the heterojunction becomes excessively high, the adverse effect on the breakdown voltage increases. In the technique of the above publication, the on-resistance is increased because the withstand voltage is greatly reduced due to the excessively high impurity concentration or the ohmic junction cannot be obtained due to the insufficient impurity concentration. It could have become.

  The present invention has been made to solve the above-described problems, and an object thereof is to provide a power semiconductor device having both a low on-resistance and a high breakdown voltage.

  The power semiconductor device of the present invention includes a semiconductor substrate, a drain electrode, a semiconductor layer, a source electrode, a gate insulating film, and a gate electrode. The semiconductor substrate is provided with a first surface and a second surface opposite to the first surface, and has a first conductivity type. The drain electrode is provided on the first surface of the semiconductor substrate. The semiconductor layer is provided with a third surface in contact with the second surface of the semiconductor substrate and a fourth surface opposite to the third surface. The semiconductor layer includes a first drain region, a well region, a second drain region, a third drain region, a channel region, and a source region. The source electrode is provided on the source region. The gate insulating film covers the channel region. The gate electrode is provided on the channel region through a gate insulating film.

  The first drain region is made of a first semiconductor material having a first conductivity type. The well region narrows the first drain region in the width direction parallel to the second surface, and has a second conductivity type different from the first conductivity type. The second drain region is provided on a portion of the first drain region confined by the well region, and is made of a second semiconductor material having the first conductivity type. The third drain region is provided on the second drain region and is made of a third semiconductor material having the first conductivity type. The channel region is located in a portion of the fourth surface of the semiconductor layer above the well region and includes a portion made of a third semiconductor material. The source region is connected to the third drain region through the channel region and has the first conductivity type.

  When the first conductivity type is n-type, the energy of the conduction band edge in the band gap of the second semiconductor material is lower than the energy of the conduction band edge in the band gap of the first semiconductor material, and The energy of the conduction band edge in the band gap of the third semiconductor material is lower than the energy of the conduction band edge in the band gap of the second semiconductor material. When the first conductivity type is p-type, the energy of the valence band edge in the band gap of the second semiconductor material is higher than the energy of the valence band edge in the band gap of the first semiconductor material. And the energy of the valence band edge in the band gap of the third semiconductor material is higher than the energy of the valence band edge of the second semiconductor material.

  According to the present invention, the first semiconductor material is selected to be suitable for improving the breakdown voltage, and the third semiconductor material is selected to be suitable for reducing the channel resistance. Can be reduced. A second drain region is provided on the first drain region, and a third drain region is provided on the second drain region. In other words, a heterojunction between the first semiconductor material and the second semiconductor material and a heterojunction between the second semiconductor material and the third semiconductor material are provided. Thereby, compared with the case where a heterojunction is provided directly between 1st semiconductor material and 3rd semiconductor material, the band offset in each heterojunction can be relieve | moderated. Therefore, the impurity concentration necessary to make each heterojunction ohmic can be reduced. Therefore, it is possible to suppress a decrease in breakdown voltage due to the high impurity concentration. From the above, a power semiconductor device having both a low on-resistance and a high breakdown voltage can be obtained.

It is sectional drawing which shows roughly the structure of the semiconductor device for electric power in a comparative example. It is a graph which shows the example of the relationship between the impurity concentration in a heterojunction surface, and contact resistance. It is a graph which shows the example of the relationship between the impurity concentration in a heterojunction surface, and a dielectric breakdown voltage. It is a graph which shows the example of the relationship between the gate voltage and drain current in the power semiconductor device of a comparative example. 1 is a cross-sectional view schematically showing a configuration of a power semiconductor device according to a first embodiment of the present invention. It is a schematic diagram of the band offset of the conduction band of the semiconductor layer in the power semiconductor device according to the first embodiment of the present invention. It is a graph which shows the example of the relationship between the impurity concentration in a heterojunction surface, and contact resistance. FIG. 5 is graphs (A) to (C) showing examples of the relationship between the impurity concentration and the dielectric breakdown voltage at the heterojunction surface for each of band offsets of 0.93 eV, 0.465 eV, and 0.31 eV. It is sectional drawing which shows schematically the 1st process of the manufacturing method of the semiconductor device which concerns on Embodiment 1 of this invention. It is sectional drawing which shows schematically the 2nd process of the manufacturing method of the semiconductor device which concerns on Embodiment 1 of this invention. FIG. 6 is a cross-sectional view schematically showing a configuration of a modified example of the power semiconductor device of FIG. 5. It is sectional drawing which shows schematically the structure of the semiconductor device for electric power which concerns on Embodiment 2 of this invention. It is a schematic diagram of the band offset of the conduction band of the semiconductor layer in the power semiconductor device according to the second embodiment of the present invention. It is a graph which shows the example of the relationship between the gate voltage and drain current in the power semiconductor device which concerns on Embodiment 2 of this invention. It is a graph which shows the example of the relationship between the impurity concentration in a heterojunction surface, and a dielectric breakdown voltage. It is sectional drawing which shows schematically the structure of the semiconductor device for electric power which concerns on Embodiment 3 of this invention. It is sectional drawing which shows schematically the 1st process of the manufacturing method of the semiconductor device which concerns on Embodiment 3 of this invention. It is sectional drawing which shows schematically the 2nd process of the manufacturing method of the semiconductor device which concerns on Embodiment 3 of this invention. It is sectional drawing which shows roughly the structure of the semiconductor device for electric power which concerns on Embodiment 4 of this invention. It is sectional drawing which shows roughly the structure of the semiconductor device for electric power which concerns on Embodiment 5 of this invention. It is sectional drawing which shows roughly the 1st process of the manufacturing method of the semiconductor device which concerns on Embodiment 5 of this invention. It is sectional drawing which shows schematically the 2nd process of the manufacturing method of the semiconductor device which concerns on Embodiment 5 of this invention. It is sectional drawing which shows schematically the 3rd process of the manufacturing method of the semiconductor device which concerns on Embodiment 5 of this invention. It is sectional drawing which shows schematically the 4th process of the manufacturing method of the semiconductor device which concerns on Embodiment 5 of this invention.

  Hereinafter, embodiments of the present invention and comparative examples thereof will be described with reference to the drawings. In the following drawings, the same or corresponding parts are denoted by the same reference numerals, and description thereof will not be repeated.

(Comparative example)
Prior to description of each embodiment of the present invention, first, a comparative example will be described below.

  Referring to FIG. 1, MOSFET 900 (power semiconductor device) of this comparative example includes a substrate 1 (semiconductor substrate), a drain electrode 11, a semiconductor layer 200, a source electrode 10, a gate insulating film 9, and a gate. It has an electrode 8 and an interlayer insulating film 7. The substrate 1 is provided with a surface S1 (first surface) and a surface S2 (second surface opposite to the first surface). The substrate 1 has n-type (first conductivity type). The drain electrode 11 is provided on the surface S <b> 1 of the substrate 1.

  The semiconductor layer 200 is provided with a surface S3 (third surface) in contact with S2 of the substrate 1 and a surface S4 (fourth surface opposite to the third surface). The semiconductor layer 200 includes a main drain region 2, a lower drain region 101, a well region 4, an upper drain region 102, a channel region CR, a source region 6, and a high concentration contact region 5.

  The main drain region 2 is provided on the surface S2 of the substrate 1. The main drain region 2 has an n-type and has a lower impurity concentration than the impurity concentration of the substrate 1. In this specification, “impurity concentration” means the concentration of a conductive impurity (donor or acceptor) unless otherwise specified.

  The lower drain region 101 is provided on the main drain region 2. Lower drain region 101 has an n-type and has a higher impurity concentration than that of main drain region 2. Lower drain region 101 is made of the same semiconductor material as main drain region 2. The well region 4 narrows the lower drain region 101 in the width direction (lateral direction in the drawing) parallel to the surface S2, and has a p-type (second conductivity type different from the first conductivity type).

  In this comparative example, the upper drain region 102 is directly provided on a portion (JFET (Junction Field Effect Transistor) region) constricted by the well region 4 in the lower drain region 101. Upper drain region 102 has an n-type and has a higher impurity concentration than that of main drain region 2. The semiconductor material of the lower drain region 101 and the semiconductor material of the upper drain region 102 have different band gaps. Therefore, the interface between the lower drain region 101 and the upper drain region 102 forms a heterojunction with a band offset. The impurity concentration of each of the lower drain region 101 and the upper drain region 102 is sufficiently high so that the heterojunction becomes an ohmic junction.

  The channel region CR is located in a portion on the well region 4 in the surface S4 of the semiconductor layer 200. In other words, the channel region CR is located above the well region 4 in the surface S4 of the semiconductor layer 200. Here, “upward” means the thickness direction of the semiconductor layer from the surface S3 to the surface S4. In this comparative example, the channel region CR is constituted by the well region 4. The channel region CR includes a portion made of the semiconductor material of the upper drain region 102.

The source region 6 is connected to the upper drain region 102 through the channel region CR. Source region 6 has n-type. The impurity concentration of the source region is, for example, 1 × 10 ¹⁸ cm ⁻³ or more and 5 × 10 ²¹ cm ⁻³ or less. The high concentration contact region 5 is provided on the well region 4 and is in contact with the source electrode 10. The source electrode 10 is provided on the source region 6. The gate insulating film 9 covers the channel region CR. The gate electrode 8 is provided on the channel region CR via the gate insulating film 9. The interlayer insulating film 7 covers the gate electrode 8.

FIG. 2 is a simulation result showing an example of the relationship between the impurity concentration at the heterojunction between the lower drain region 101 and the upper drain region 102 and the contact resistance. As simulation conditions, the lower drain region 101 is made of polytype 4H SiC (silicon carbide), and the upper drain region 102 is made of polytype 3C SiC. The energy at the conduction band edge of 3C-SiC was 0.93 eV lower than the energy at the conductor edge of 4H-SiC. The impurity concentration of 3C—SiC was fixed at 1 × 10 ¹⁶ cm ^−3, and the length of 4H—SiC was set to 40 nm as a length sufficient for the discussion of ohmic contact. When the contact resistance is calculated for the impurity concentration of 4H—SiC in the range of 5 × 10 ¹⁸ cm ⁻³ to 1 × 10 ²⁰ cm ⁻³ , the contact resistance of the heterojunction surface decreases as the impurity concentration of 4H—SiC increases. I understood.

FIG. 3 is a simulation result showing an example of the relationship between the impurity concentration of the lower drain region 101 and the dielectric breakdown voltage at the interface between the lower drain region 101 and the main drain region 2. As simulation conditions, the impurity concentration of the main drain region 2 was fixed at 1 × 10 ¹⁶ cm ⁻³ . From this result, it was found that the impurity concentration of the lower drain region 101 needs to be 5 × 10 ¹⁸ cm ⁻³ or less in order to avoid a rapid decrease in the dielectric breakdown voltage. Referring to FIG. 2, in this case, the contact resistance becomes a high value exceeding 10 Ω · cm ² .

FIG. 4 is a simulation result of the drain current in the comparative example MOSFET 900 (FIG. 1) and still another comparative example MOSFET (not shown) having no semiconductor heterojunction surface. For MOSFET 900, the results are shown for cases where the impurity concentration in the lower drain region 101 is 1 × 10 ²⁰ cm ⁻³ , 2 × 10 ¹⁹ cm ⁻³ , and 1 × 10 ¹⁹ cm ⁻³ . From this result, it was found that the drain current decreases as the impurity concentration of the lower drain region 101 decreases. When the gate voltage is 15 V, the MOSFET 900 having the lower drain region 101 having an impurity concentration of 1 × 10 ¹⁹ cm ⁻³ has a lower drain current than a MOSFET having no semiconductor heterojunction surface. From this, it was found that the impurity concentration of the lower drain region 101 needs to be 1 × 10 ¹⁹ cm ⁻³ or more in order to sufficiently obtain the effect of reducing the on-resistance by providing the hetero junction.

However, as shown in FIG. 3 described above, it has been found that when the impurity concentration of the lower drain region 101 is higher than 5 × 10 ¹⁸ cm ⁻³ , the dielectric breakdown voltage rapidly decreases. For this reason, in the structure of MOSFET900, it turned out that utilization of a heterojunction has hardly contributed to elimination of the trade-off between low on-resistance and high withstand voltage. Based on this result, the present inventor has studied a method for obtaining both low on-resistance and high breakdown voltage by a heterojunction, and has come up with the configuration of each embodiment described below.

(Embodiment 1)
Referring to FIG. 5, MOSFET 901 (power semiconductor device) of the present embodiment includes semiconductor layer 201 instead of semiconductor layer 200 in MOSFET 900 (FIG. 1). Since other configurations are substantially the same as the configurations of the comparative example described above, the same or corresponding elements are denoted by the same reference numerals, and the description thereof will not be repeated. Hereinafter, although there is a part overlapping with the description of the comparative example, the structure of the semiconductor layer 201 will be described in detail.

  Similar to the semiconductor layer 200, the semiconductor layer 201 is provided with a surface S 3 in contact with the surface S 2 of the substrate 1 and a surface S 4. The semiconductor layer 201 includes a main drain region 2, a lower drain region 101 (first drain region), a well region 4, an intermediate drain region 103 (second drain region), and an upper drain region 102 (third drain region). Drain region), a channel region CR, a source region 6, and a high concentration contact region 5.

The main drain region 2 is provided on the surface S2 of the substrate 1. The main drain region 2 is made of a first semiconductor material having n-type (first conductivity type). The impurity concentration of the main drain region 2 is lower than the impurity concentration of the substrate 1. The impurity concentration of the main drain region 2 is, for example, 1 × 10 ¹⁴ cm ⁻³ or more and 1 × 10 ¹⁷ cm ⁻³ or less.

The lower drain region 101 is provided on the main drain region 2. Similar to the main drain region 2, the lower drain region 101 is made of a first semiconductor material having n-type (first conductivity type). The impurity concentration of the lower drain region 101 is higher than the impurity concentration of the main drain region 2 and is high enough for the heterojunction between the lower drain region 101 and the intermediate drain region 103 to be ohmic. The impurity concentration of the lower drain region 101 is, for example, 1 × 10 ¹⁴ cm ⁻³ or more and 5 × 10 ¹⁸ cm ⁻³ or less. The first semiconductor material is preferably a wide band gap semiconductor material, and more preferably silicon carbide. Thereby, the breakdown voltage of the lower drain region 101 can be increased.

The well region 4 narrows the lower drain region 101 in the width direction parallel to the surface S2. The impurity concentration of the well region 4 is, for example, 1 × 10 ¹⁵ cm ⁻³ or more and 1 × 10 ¹⁹ cm ⁻³ or less.

  The intermediate drain region 103 is provided on a portion of the lower drain region 101 constricted by the well region 4. The intermediate drain region 103 is made of a second semiconductor material having n-type. The impurity concentration of the intermediate drain region 103 is higher than the impurity concentration of the main drain region 2 and is sufficient for the heterojunction between each of the lower drain region 101 and the upper drain region 102 and the intermediate drain region 103 to be ohmic. Has a height.

  The upper drain region 102 is provided on the intermediate drain region 103. That is, unlike the comparative example (FIG. 1), in this embodiment, the upper drain region 102 is indirectly provided on the lower drain region 101 through the intermediate drain region 103. The upper drain region 102 is made of a third semiconductor material having n-type. The impurity concentration of the upper drain region 102 is higher than the impurity concentration of the main drain region 2 and is high enough for the heterojunction between the upper drain region 102 and the intermediate drain region 103 to be ohmic.

  Note that the impurity concentrations of the lower drain region 101, the intermediate drain region 103, and the upper drain region 102 need not be the same. In addition, in each of the lower drain region 101, the intermediate drain region 103, and the upper drain region 102, the impurity concentration does not need to be uniform.

  The channel region CR is located on the surface of the semiconductor layer 201 on the well region 4 in the surface S4. In other words, the channel region CR is located above the well region 4 in the surface S4 of the semiconductor layer 201. The channel region CR is made of the third semiconductor material. When the first semiconductor material forming the lower drain region 101 is silicon carbide, the third semiconductor material may be silicon carbide having a polytype different from that of the first semiconductor material. Thus, a polytype suitable for reducing channel resistance can be used as the third semiconductor material. For example, the lower drain region 101 is made of polytype 4H SiC, and the upper drain region 102 and the channel region CR are made of polytype 3C SiC. Thus, the channel resistance can be reduced by using the polytype 3C while increasing the breakdown voltage of the drain region 1 by using the polytype 4H. In the present embodiment, the surface of the channel region CR is composed of a well region 4 having a p-type, and thus the channel region CR has a p-type.

  When SiC regions having different polytypes are provided on the substrate 1 as described above, the substrate 1 is preferably made of SiC having a hexagonal crystal structure, and its surface S2 is substantially in relation to the c-axis. It is a surface (just surface) perpendicular to the surface. This facilitates the growth of different polytypes on the substrate 1. The “surface substantially perpendicular to the c-axis” is, for example, a surface whose inclination from the surface perpendicular to the c-axis is within 4 °.

Referring to FIG. 6, when the MOSFET is n-type (when the first conductivity type is n-type) as in the present embodiment, the energy at the conduction band edge in the band gap of the first semiconductor material. The conduction band edge energy in the band gap of the second semiconductor material is lower than the band gap of the second semiconductor material and in the band gap of the third semiconductor material compared to the energy of the conduction band edge in the band gap of the second semiconductor material. The energy at the conduction band edge is lower. In other words, there is a negative band offset dE _{13 in the} conduction band from the lower drain region 101 to the intermediate drain region 103, and a negative band offset dE _{32 in the} conduction band from the intermediate drain region 103 to the upper drain region 102. For example, dE ₁₃ is preferably 30% to 70% of dE ₁₃ + dE ₃₂ . FIG. 6 shows the case where the energy at the conduction band edge in the band gap is constant in the intermediate drain region 103, but this is not necessarily the case. The energy at the conduction band edge in the band gap may change continuously between the energy at the conduction band edge of the lower drain region 101 and the energy at the conduction band edge of the upper drain region 102 in the intermediate drain region 103.

  For example, there are the following three types of specific combinations that satisfy the above-described characteristics related to the energy at the conduction band edge, in other words, the characteristics related to the conduction band offset.

In the first combination, 4H—SiC is used as the first and second semiconductor materials, and 3C—SiC is used as the third semiconductor material. Nonconductive impurities for band offset control are added to the second semiconductor material. This non-conductive impurity added to SiC does not contribute to the n-type or p-type conductivity, but contributes to modulating the band offset to satisfy the above-described characteristics. As the non-conductive impurity, at least one of carbon, silicon, germanium, tin, and lead can be used. The band offset is considered to change due to the change in the lattice spacing due to the addition of non-conductivity type impurities. The concentration of the nonconductive impurity is, for example, 1 × 10 ¹⁶ cm ⁻³ or more and 1 × 10 ²² cm ⁻³ or less. The concentration distribution of the non-conductive impurities does not need to be uniform and may have a peak concentration. In that case, the peak concentration is preferably 1 × 10 ¹⁷ cm ⁻³ or more. Note that a non-conductive impurity may be added to the first semiconductor material, but its concentration is lower than that in the second semiconductor material.

  As the second combination, 4H—SiC can be used as the first semiconductor material, 15R—SiC can be used as the second semiconductor material, and 3C—SiC can be used as the third semiconductor material. When the first semiconductor material and the third semiconductor material have different polytypes in this way, the intermediate drain region 103 may not clearly have a single polytype. A transition between the polytype of the first semiconductor material and the polytype of the third semiconductor material may occur. In this case, the layer made of the second semiconductor material can be formed when switching from the step of depositing the first semiconductor material to the step of depositing the third semiconductor material. Thereby, a process can be simplified.

As a third combination, GaN is used as the _first semiconductor material, Al _1-x Ga _x N (0 <x <1) is used as the second semiconductor material, and Al _1-y is used as the third semiconductor material. Ga _y N (0 <y <x) may be used. Thus, when the second semiconductor material has a composition between the composition of the first semiconductor material and the composition of the third semiconductor material, the third semiconductor material is deposited from the step of depositing the first semiconductor material. A layer made of the second semiconductor material may be formed when switching to the process of performing the process. Thereby, a process can be simplified.

  According to the present embodiment, the MOSFET 901 (FIG. 5) is selected by selecting the first semiconductor material suitable for improving the breakdown voltage and selecting the third semiconductor material suitable for reducing the channel resistance. ) Can be reduced. An intermediate drain region 103 is provided on the lower drain region 101, and an upper drain region 102 is provided on the intermediate drain region 103. In other words, a heterojunction between the first semiconductor material and the second semiconductor material and a heterojunction between the second semiconductor material and the third semiconductor material are provided. As a result, the band offset at each heterojunction is reduced as compared with the case where the heterojunction is provided directly between the first semiconductor material and the third semiconductor material as in the MOSFET 900 of the comparative example (FIG. 1). be able to. Therefore, the impurity concentration necessary to make each heterojunction ohmic can be reduced. Therefore, it is possible to suppress a decrease in breakdown voltage due to an increase in electric field strength due to the high impurity concentration. From the above, a MOSFET having both a low on-resistance and a high breakdown voltage can be obtained.

The reason why the impurity concentration necessary to make each heterojunction ohmic in the MOSFET 901 compared to the MOSFET 900 (FIG. 1) can be described below. FIG. 7 is a simulation result showing an example of the relationship between the impurity concentration and the contact resistance at the heterojunction surface of n-type 4H—SiC and n-type 3C—SiC. The impurity concentration of 3C—SiC was fixed at 1 × 10 ¹⁶ cm ⁻³ , and the length of 4H—SiC was 40 nm. Calculations were made for each of band offsets 0.93 eV, 0.465 eV and 0.31 eV of the conduction band at the heterojunction surface. As a result, the contact resistance at the heterojunction surface greatly decreased nonlinearly as the band offset decreased. This is because the band offset of the conduction band from the lower drain region 101 to the upper drain region 102 is gradually reduced instead of in one step while maintaining a desired low contact resistance, so that the impurity concentration at the heterojunction surface is reduced. It is possible to reduce

FIG. 8 is a graph (A) to (C) showing an example of the relationship between the impurity concentration at the heterojunction surface and the breakdown voltage for each of band offsets dE = 0.93 eV, 0.465 eV, and 0.31 eV. ). From this simulation result, it was found that when the impurity concentration of the lower drain region 101 is 5 × 10 ¹⁸ cm ⁻³ or less, the breakdown voltage increases rapidly regardless of the band offset. From this, it was found that the impurity concentration of the lower drain region 101 is 5 × 10 ¹⁸ cm ⁻³ or less in order to maintain the breakdown voltage of the MOSFET 901.

  As described above, by introducing the intermediate drain region 103 in the MOSFET 901, it is possible to reduce the impurity concentration for ohmic connection of the heterojunction surface to the same extent as in the MOSFET 900 (FIG. 1). Therefore, the MOSFET 901 can suppress the on-resistance as much as the MOSFET 900 and can increase the dielectric breakdown voltage more than the MOSFET 900.

  Next, a method for manufacturing MOSFET 901 will be described below.

  Referring to FIG. 9, main drain region 2 is formed on substrate 1 by epitaxial growth. Next, a lower drain region 101, an intermediate drain region 103, and an upper drain region 102 are formed on the main drain region 2. Each of the lower drain region 101, the intermediate drain region 103, and the upper drain region 102 can be formed by epitaxial growth. The intermediate drain region 103 may be formed as a transition layer when the growth condition is switched from the epitaxial growth of the lower drain region 101 to the epitaxial growth of the upper drain region 102.

  The intermediate drain region 103 or the upper drain region 102 may be formed by adding the aforementioned non-conductive impurities to the lower drain region 101 made of SiC. Note that the lower drain region 101 may also contain non-conductive impurities. The addition of non-conductive impurities may be performed during epitaxial growth, or may be performed by ion implantation or diffusion treatment after growth. Both addition during epitaxial growth and addition after growth may be performed.

  Alternatively, after the growth of the lower drain region 101, the intermediate drain region 103 and the upper drain region 102 may be provided using a semiconductor substrate bonding technique.

  The lower drain region 101, the intermediate drain region 103, and the upper drain region 102 are ohmicly connected between the lower drain region 101 and the intermediate drain region 103 and between the intermediate drain region 103 and the upper drain region 102. Conductive impurities are doped so as to provide a simple impurity profile. This doping may be performed during epitaxial growth or may be performed by ion implantation after epitaxial growth. The ion implantation may be performed on the entire surface of the substrate 1 or may be performed locally.

  Referring to FIG. 10, well region 4 is formed by ion implantation. The well region 4 extends to a lower drain region 101 made from a first semiconductor material, an intermediate drain region 103 made from a second semiconductor material, and an upper drain region 102 made from a third semiconductor material. Formed by ion implantation. For this reason, in the well region 4, the energy at the conduction band edge in the band gap changes in the depth direction. The order of this ion implantation and the ion implantation in the step of FIG. 9 is arbitrary.

  Referring to FIG. 5 again, high concentration contact region 5 and source region 6 are formed by ion implantation. The order of this ion implantation and the ion implantation in the steps of FIGS. 9 and 10 is arbitrary. Thereafter, the implanted impurities are activated by activation annealing. Note that the activation annealing is not necessarily performed all at once, and may be performed every ion implantation. Thereafter, the gate insulating film 9, the gate electrode 8, the interlayer insulating film 7, the source electrode 10 and the drain electrode 11 are formed. As a result, a MOSFET 901 is obtained.

  In the MOSFET 901 (FIG. 5), the lower drain region 101 is provided between the main drain region 2 and the intermediate drain region 103. However, the main drain region 2 and the intermediate drain region 103 are not directly connected to the lower drain region 101. If the contact resistance does not matter even if contact is made, a semiconductor layer 201V from which the lower drain region 101 is omitted can be used, such as a MOSFET 901V (power semiconductor device) shown in FIG.

(Embodiment 2)
Referring to FIG. 12, in semiconductor layer 202 of MOSFET 902 (power semiconductor device) of the present embodiment, instead of single intermediate drain region 103 (FIG. 1) made of the second semiconductor material, A plurality of intermediate drain regions 104 and 105 (second drain regions) are used. The intermediate drain region 104 is made of a fourth semiconductor material different from the first and third semiconductor materials described above, and the intermediate drain region 105 is a fifth different from the first, third, and fourth semiconductor materials. Made from semiconductor materials. The intermediate drain region 104 is provided on the lower drain region 101. The intermediate drain region 105 is provided on the intermediate drain region 104. The upper drain region 102 is provided on the intermediate drain region 105.

Referring to FIG. 13, when the MOSFET is n-type as in the present embodiment (when the first conductivity type is n-type), the energy at the conduction band edge in the band gap of the first semiconductor material. The conduction band edge energy in the band gap of the fourth semiconductor material is lower than that of the fourth semiconductor material, and in the band gap of the fifth semiconductor material compared to the energy of the conduction band edge in the band gap of the fourth semiconductor material. The energy of the conduction band edge is lower, and the energy of the conduction band edge in the band gap of the second semiconductor material is lower than the energy of the conduction band edge in the band gap of the fifth semiconductor material. In other words, there is a negative band offset dE _{14 in the} conduction band from the lower drain region 101 to the intermediate drain region 104, and there is a negative band offset dE _{45 in the} conduction band from the intermediate drain region 104 to the intermediate drain region 105, In addition, a negative band offset dE ₅₂ of the conduction band exists from the intermediate drain region 105 to the upper drain region 102.

For example, when the lower drain region 101 is made of 4H—SiC and the upper drain region 102 is made of 3C—SiC, each of the band offsets dE ₁₄ , dE ₄₅ and dE ₅₂ can be equal to 0.31 eV. . FIG. 14 is a simulation result showing an example of the relationship between the gate voltage and the drain current in this case (solid line in the drawing) together with an example of the relationship in the comparative example having no heterostructure (broken line in the drawing). . Note that the impurity concentration of each of the lower drain region 101, the intermediate drain regions 104 and 105, and the upper drain region 102 in the MOSFET 902 is 3 × 10 ¹⁷ cm ⁻³ . The influence of resistance due to the spread of the depletion layer from the well region 4 was also taken into consideration. From the simulation results, it was found that the MOSFET 902 of this embodiment has a lower on-resistance than that of the comparative example.

  Since the configuration other than the above is substantially the same as the configuration of the first embodiment described above, the same or corresponding elements are denoted by the same reference numerals, and description thereof is not repeated.

FIG. 15 is a simulation result showing an example of the relationship between the impurity concentration of the lower drain region 101 and the breakdown voltage. As the fourth and fifth semiconductor materials, 3C—SiC was used instead of 4H—SiC in order to perform simulation under conditions where dielectric breakdown is more likely to occur. From the results of this simulation, it was found that when the impurity concentration of the lower drain region 101 and the intermediate drain regions 104 and 105 is 3 × 10 ¹⁷ cm ⁻³ , the breakdown voltage equivalent to that of the conventional semiconductor device can be maintained. .

  From the above, it has been found that the on-resistance can be reduced in the MOSFET 902 of the present embodiment while maintaining the same breakdown voltage as the conventional one.

(Embodiment 3)
Referring to FIG. 16, in semiconductor layer 203 of MOSFET 903 (power semiconductor device) of the present embodiment, n-type intermediate drain region 103 and upper drain region 102 are sequentially positioned on well region 4. Thus, the channel region CRa of the MOSFET 903 is constituted by the n-type intermediate drain region 103 and the upper drain region 102. That is, the channel region CRa of the MOSFET 903 has an n type. Note that the well region 4 is formed of only the first semiconductor material in the present embodiment, unlike the first and second embodiments.

  By selecting the thickness and impurity concentration of the intermediate drain region 103 and the upper drain region 102, the channel region CRa is depleted by the extension of the depletion layer from the well region 4 even when no electric field is applied from the gate electrode 8. It can be. Thereby, the MOSFET 903 can be a normally-off type.

  Since the configuration other than the above is substantially the same as the configuration of the first embodiment described above, the same or corresponding elements are denoted by the same reference numerals, and description thereof is not repeated.

  Next, a method for manufacturing MOSFET 903 will be described below.

  Referring to FIG. 17, main drain region 2 is formed on substrate 1 by epitaxial growth. Further, the lower drain region 101 is formed by epitaxial growth or ion implantation. The well region 4 is formed by ion implantation. The order in which the lower drain region 101 and the well region 4 are formed is arbitrary.

  Referring to FIG. 18, intermediate drain region 103 and upper drain region 102 are sequentially formed by epitaxial growth. The well region 4 may be formed after the intermediate drain region 103 is formed on the lower drain region 101.

  Referring to FIG. 16 again, high concentration contact region 5 and source region 6 are formed by ion implantation. Thereafter, the implanted impurities are activated by activation annealing. Note that the activation annealing is not necessarily performed all at once, and may be performed every ion implantation. Thereafter, the gate insulating film 9, the gate electrode 8, the interlayer insulating film 7, the source electrode 10 and the drain electrode 11 are formed. Thereby, a MOSFET 903 is obtained.

  According to the present embodiment, the channel region CRa can be configured from the layer obtained by the film formation for the upper drain region 102 having the n-type without changing the conductivity type by ion implantation. Therefore, an increase in channel resistance due to damage to the channel region due to ion implantation can be avoided.

(Embodiment 4)
Referring to FIG. 19, n-type upper drain region 102 is located on well region 4 in semiconductor layer 204 of MOSFET 904 (power semiconductor device) of the present embodiment. Thus, the channel region CRb of the MOSFET 904 is constituted by the n-type upper drain region 102. That is, the channel region CRb of the MOSFET 904 has an n type. In this embodiment, the well region 4 is formed of the first and second semiconductor materials, unlike the first to third embodiments.

  Since the configuration other than the above is substantially the same as the configuration of the third embodiment described above, the same or corresponding elements are denoted by the same reference numerals, and description thereof will not be repeated. Also according to the present embodiment, substantially the same effect as in the third embodiment can be obtained.

(Embodiment 5)
Referring to FIG. 20, in semiconductor layer 205 of MOSFET 905 (power semiconductor device) of the present embodiment, upper drain region 102 made of a third semiconductor material is made of a material different from that of the third semiconductor material. It has a portion located in a trench TR made of a second semiconductor material. Further, the intermediate drain region 103 made of the second semiconductor material has a portion located in the trench TS made of the first semiconductor material which is a different material from the second semiconductor material.

  Since the configuration other than the above is substantially the same as the configuration of the third embodiment described above, the same or corresponding elements are denoted by the same reference numerals, and description thereof will not be repeated.

  Next, a method for manufacturing MOSFET 905 will be described below.

  Referring to FIG. 21, main drain region 2 is formed on substrate 1 by epitaxial growth of a first semiconductor material. Next, the lower drain region 101 and the well region 4 are formed as shown in FIG. Lower drain region 101 and well region 4 constitute trench TS. The trench TS has a bottom part constituted by the lower drain region 101 and a side wall part constituted by the well region 4. There are several ways to obtain the configuration shown in FIG. As a first example, after the epitaxial growth of the main drain region 2 on the substrate 1, first, a trench TS is formed in the main drain region 2 by etching. Next, the lower drain region 101 is formed by ion implantation into the bottom of the trench TS, and the well region 4 is formed by ion implantation into the sidewall of the trench TS. The order of these ion implantations is arbitrary. As a second example, the lower drain region 101 is formed on the main drain region 2 by epitaxial growth of the first semiconductor material at a higher impurity concentration after the epitaxial growth of the main drain region 2 on the substrate 1. Next, the trench TS is formed in the lower drain region 101 by etching, and the well region 4 is formed in the sidewall portion of the trench TS by ion implantation. The order of this etching and ion implantation is arbitrary.

  Referring to FIG. 22, the intermediate drain region 103 is formed by epitaxial growth of the second semiconductor material so as to fill the trench TS made of the first semiconductor material. At this time, the presence of the trench TS further promotes the growth in the trench TS as compared with the outside of the trench TS. That is, so-called selective growth is performed.

  Referring to FIG. 23, trench TR is formed in intermediate drain region 103 by etching. In other words, the trench TR made of the second semiconductor material is formed. Next, epitaxial growth of the third semiconductor material is performed so as to fill the trench TR. At this time, the presence of the trench TR further promotes the growth in the trench TR as compared with the outside of the trench TR. That is, so-called selective growth is performed. Although FIG. 23 shows the case where the sidewall portion of the trench TR is constituted by the intermediate drain region 103, the sidewall portion of the trench TR may be constituted by the well region 4. In this case, the side wall of the trench TR is made of the first semiconductor material.

  Referring to FIG. 24, the upper drain region 102 is formed by epitaxial growth of the third semiconductor material so as to fill the trench TR. At this time, the presence of the trench TR further promotes the growth in the trench TR as compared with the outside of the trench TR. That is, so-called selective growth is performed.

  Referring to FIG. 20 again, high concentration contact region 5 and source region 6 are formed by ion implantation. Thereafter, the implanted impurities are activated by activation annealing. Note that the activation annealing is not necessarily performed all at once, and may be performed every ion implantation. Thereafter, the gate insulating film 9, the gate electrode 8, the interlayer insulating film 7, the source electrode 10 and the drain electrode 11 are formed. Thereby, MOSFET 905 is obtained.

  According to the present embodiment, the selective growth in the trench TR occurs, so that the growth of the upper drain region 102 can be promoted. Further, the selective growth in the trench TS occurs, so that the growth of the intermediate drain region 103 can be promoted.

  It should be noted that the present invention can be freely combined with each other within the scope of the invention, and each embodiment can be appropriately modified or omitted.

  For example, in each of the above-described embodiments, the case where an n-type MOSFET having electrons as carriers by configuring the first conductivity type as n-type and the second conductivity type as p-type has been described in detail. A p-type MOSFET having holes as carriers may be configured by setting the first conductivity type to be p-type and the second conductivity type to be n-type. In this case, the first to third semiconductor materials constituting each of the lower drain region 101, the intermediate drain region 103, and the upper drain region 102 are characterized by the band structure as the carriers become holes instead of electrons. Instead of the above-described characteristics relating to the band offset of the conduction band, the characteristics relating to the band offset of the valence band are provided. Specifically, the energy of the valence band edge in the band gap of the second semiconductor material is higher than the energy of the valence band edge in the band gap of the first semiconductor material, and Compared to the energy at the valence band edge, the energy at the valence band edge in the band gap of the third semiconductor material is higher. In other words, a valence band positive band offset exists from the lower drain region 101 to the intermediate drain region 103, and a valence band positive band offset exists from the intermediate drain region 103 to the upper drain region 102.

  In each of the above embodiments, the MOSFET has been described. However, an insulating film other than an oxide film may be used as the gate insulating film 9. Thus, a MISFET (Metal Insulated Semiconductor Field Effect Transistor) is configured.

  The power semiconductor device is not limited to the MISFET. For example, in each of the above embodiments, the drain electrode 11 may be provided on the surface S1 of the substrate 1 via the collector layer of the second conductivity type. Thereby, an IGBT (Insulated Gate Bipolar Transistor) is configured instead of the MISFET.

  CR, CRa, CRb channel region, TR, TS groove, 1 substrate (semiconductor substrate), 2 main drain region, 4 well region, 5 high concentration contact region, 6 source region, 7 interlayer insulating film, 8 gate electrode, 9 gate Insulating film, 10 source electrode, 11 drain electrode, 101 lower drain region (first drain region), 102 upper drain region (third drain region), 103 to 105 intermediate drain region (second drain region), 200 , 201, 201V, 202-205 semiconductor layer, 900, 901, 901V, 902-905 MOSFET (power semiconductor device).

Claims (13)

A power semiconductor device comprising:
A semiconductor substrate provided with a first surface and a second surface opposite to the first surface and having a first conductivity type;
A drain electrode provided on the first surface of the semiconductor substrate;
A semiconductor layer provided with a third surface in contact with the second surface of the semiconductor substrate and a fourth surface opposite to the third surface, the semiconductor layer comprising:
A first drain region made of a first semiconductor material having the first conductivity type;
A well region having a second conductivity type different from the first conductivity type, constricting the first drain region in a width direction parallel to the second surface;
A second drain region provided on a portion of the first drain region constricted by the well region and made of a second semiconductor material having the first conductivity type;
A third drain region provided on the second drain region and made of a third semiconductor material having the first conductivity type, wherein the first conductivity type is n-type The energy of the conduction band edge in the band gap of the second semiconductor material is lower than the energy of the conduction band edge in the band gap of the first semiconductor material, and in the band gap of the second semiconductor material The energy of the conduction band edge in the band gap of the third semiconductor material is lower than the energy of the conduction band edge, and when the first conductivity type is p-type, the band of the first semiconductor material The energy of the valence band edge in the band gap of the second semiconductor material is higher than the energy of the valence band edge in the gap, and the energy of the second semiconductor material The energy of the valence band edge in the band gap of the third semiconductor material is higher than the energy of the electron band edge, and the semiconductor layer is further above the well region of the fourth surface of the semiconductor layer. A channel region including a portion made of the third semiconductor material, connected to the third drain region via the channel region, and including a source region having the first conductivity type. The power semiconductor device further includes a source electrode provided on the source region,
A gate insulating film covering the channel region;
A power semiconductor device comprising: a gate electrode provided on the channel region with the gate insulating film interposed therebetween.   The power semiconductor device according to claim 1, wherein a surface of the channel region is formed of the well region.   The power semiconductor device according to claim 1, wherein a surface of the channel region has the first conductivity type.   4. The power semiconductor device according to claim 1, wherein the third drain region has a portion located in a groove made of a material different from the third semiconductor material. 5.   5. The power semiconductor device according to claim 1, wherein the second drain region has a portion located in a groove made of a material different from the second semiconductor material. 6.   The power semiconductor device according to claim 1, wherein the first semiconductor material is a wide band gap semiconductor material.   The power semiconductor device according to claim 6, wherein the first semiconductor material is silicon carbide.   The power semiconductor device according to claim 7, wherein the third semiconductor material is silicon carbide having a polytype different from that of the first semiconductor material.   9. The power semiconductor device according to claim 8, wherein the first semiconductor material has polytype 4H, and the third semiconductor material has polytype 3C.   10. The semiconductor substrate according to claim 7, wherein the semiconductor substrate is made of silicon carbide having a hexagonal crystal structure, and the second surface of the semiconductor substrate is a surface perpendicular to the c-axis. The power semiconductor device described.   11. The power semiconductor device according to claim 7, wherein the second semiconductor material is silicon carbide to which at least one of carbon, silicon, germanium, tin, and lead is added.   The first semiconductor material and the third semiconductor material have different polytypes, and in the second drain region, the polytype of the first semiconductor material and the polytype of the third semiconductor material are The power semiconductor device according to any one of claims 1 to 11, wherein a transition between is generated.   The power semiconductor device according to any one of claims 1 to 11, wherein the second semiconductor material has a composition between the composition of the first semiconductor material and the composition of the third semiconductor material. .

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