JP2005353877A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a normally-off vertical power MOSFET where on-resistance equivalent to a conduction loss can be reduced. <P>SOLUTION: A semiconductor device 100 is provided with a semiconductor layer 2 consisting of a first semiconductor; second conductive well areas 6 which are formed at the semiconductor layer 2 so as to include the surface of the semiconductor 2; a first conductive conduction area 2a formed in the semiconductor layer 2 extending the whole thickness of the semiconductor layer 2 in contact with the well areas 6; a channel layer 3 formed on at least a part of the well areas 6 and at least a part of the conduction area 2a, and consisting of a semiconductor; and a gate electrode 12 formed on the channel layer 3. At least a part of the channel layer 3 positioned under the gate electrode 12 consists of a second semiconductor, and the band gap of the first semiconductor is larger than that of the second semiconductor. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a semiconductor device, and more particularly to a semiconductor device as a vertical power MOSFET that controls a high voltage and a large current.

  In conventional vertical silicon (Si) power MOSFETs, the dielectric breakdown performance is inferior, and a region doped with a low concentration of impurities (drift region) may be formed in a thick film of a predetermined thickness or more in order to obtain a withstand voltage characteristic. is necessary. However, this increases the drift resistance of the Si power MOSFET, which in turn increases the on-resistance (on-resistance = channel resistance + drift resistance) corresponding to the conduction loss of the MOSFET. Further, the current capacity of the Si power MOSFET is restricted by a temperature rise that leads to deterioration of the characteristics of the Si element. For these reasons, it can be said that Si power MOSFETs are seeing limitations in improving the characteristics of semiconductor elements determined by current capacity and on-resistance.

  Thus, silicon carbide (silicon carbide; 4H—SiC), which is a wide band gap semiconductor, has attracted attention as a semiconductor material that overcomes the limitations of conventional Si power MOSFETs. SiC is a material suitable for power MOSFETs, having physical properties excellent in high withstand voltage resistance, heat conduction characteristics and high temperature resistance. More specifically, in the SiC power MOSFET, the drift region can be thinned and the impurity density in the region can be increased due to the high withstand voltage of SiC, which can significantly reduce the drift resistance. Moreover, since SiC power MOSFET can operate | move in a high temperature state and is excellent in thermal conductivity, the improvement of the current capacity is easy.

On the other hand, in the SiC power MOSFET, when a SiO ₂ layer as a gate insulating layer is laminated on the surface of the SiC layer by thermal oxidation, an interface state that traps many carriers at the interface between the SiC layer and the SiO ₂ layer. As a result, the channel state (carrier mobility in the channel) is not achieved due to the high density of interface states, which is a factor in increasing the on-resistance (channel resistance) of the SiC power MOSFET. It has become.

As a countermeasure for this, an attempt to alleviate the influence of the interface state by separating the channel through which the current flows from the SiC layer / SiO ₂ layer interface has been studied. A power MOSFET has not been developed.

Under such circumstances, a technique has been proposed in which a Si layer is heteroepitaxially grown on a SiC substrate, and then a SiO ₂ layer is stacked on the Si layer (see Patent Document 1 as a conventional example).
JP-A-11-121748

Certainly, if the SiO ₂ layer is formed on the Si layer by thermal oxidation like the power MOSFET described in the above-mentioned conventional example, interface contamination due to carbon impurities at the SiC layer / SiO ₂ layer interface is avoided. In this MOSFET, it is expected that the increase in the interface state can be effectively suppressed. However, in this MOSFET, the pn junction exposed to a high electric field (the interface between the p-type well region and the n-type Si layer) The inventor of the present application considers that the characteristics of SiC excellent in high withstand voltage resistance are not utilized effectively because the depletion layer of (1) is inherent in the region of the Si layer having inferior dielectric breakdown performance.

  The present invention has been made in view of such circumstances, and has a channel region capable of realizing high channel mobility and a drift region excellent in high withstand voltage, and both channel resistance and drift resistance are provided. It is an object of the present invention to provide a normally-off type vertical power MOSFET that can reduce the on-resistance corresponding to conduction loss. In addition, another object of the present invention is to provide a normally-off vertical power MOSFET that can operate at a high temperature and has excellent thermal conductivity (heat dissipation).

  A semiconductor device according to the present invention includes a semiconductor layer made of a first semiconductor, a second conductivity type well region formed in the semiconductor layer so as to include the surface of the semiconductor layer, and in contact with the well region. A conductive region of a first conductivity type formed in the semiconductor layer over the entire thickness of the semiconductor layer, and a semiconductor formed on at least a portion of the well region and at least a portion of the conductive region. A channel layer, and a gate electrode formed on the channel layer, wherein at least a part of the channel layer located below the gate electrode is configured by a second semiconductor, The band gap of the semiconductor is larger than the band gap of the second semiconductor. Here, the first semiconductor is, for example, any one of silicon carbide, gallium nitride, and diamond. The second semiconductor is, for example, any one of silicon, gallium arsenide, a compound containing silicon and germanium, and a compound containing silicon, germanium, and carbon.

  As a result, it has a channel region (channel layer) that can achieve high channel mobility and a drift region (semiconductor layer) with high withstand voltage resistance, lowering both channel resistance and drift resistance, and conducting loss Thus, a normally-off vertical power MOSFET that can reduce the on-resistance corresponding to is obtained.

  Here, the substrate may have a first conductivity type made of the first semiconductor, and the semiconductor layer may be formed on the substrate, and the channel layer may be configured as the second semiconductor. You may comprise by.

  Further, in the conductive region, in order to obtain a predetermined withstand voltage characteristic, it is desirable to function as a high resistance layer by reducing the concentration of the added impurity compared to the substrate.

  In addition, the channel layer has the second conductivity type, and includes a main body portion including a channel region, and a region extending from the main body portion and having a higher concentration of additive impurities than the main body portion. The first electrode that contacts the region may be arranged.

  Then, on the upper surface of the conductive region in contact with the channel layer, if the interval between adjacent well regions exceeds 0% and not more than 50% of the thickness of the semiconductor layer, the entire region between adjacent well electrodes Is closed by a depletion layer, and the narrow band gap semiconductor (channel layer) stacked on the upper surface of the conductive region can be reliably prevented from being exposed to a high electric field.

  More specifically, a second electrode that contacts the back surface of the substrate and the adjacent well region that sandwiches the conductive region located below the top surface are disposed, and the first electrode and the second electrode The conductive region between the adjacent well regions is depleted in a state where the potential difference applied between the adjacent well regions is not more than a predetermined value. At this time, the predetermined value of the potential difference is more than 0V and not more than 40V.

  According to the present invention, a channel region capable of realizing high channel mobility and a drift region excellent in high withstand voltage resistance, both channel resistance and drift resistance are lowered, and on-resistance corresponding to conduction loss is achieved. A normally-off vertical power MOSFET that can be reduced is obtained.

  A power MOSFET according to an embodiment of the present invention will be described with reference to the drawings.

  In the following description and the accompanying drawings, “n” or “p” indicates a conductivity type, and the layer or region in which these are described means that electrons or holes are carriers, respectively.

  FIG. 1 is a cross-sectional view of an n-channel type power MOSFET (semiconductor device) according to an embodiment of the present invention. A large number of well regions 6 having a substantially square planar shape or a substantially hexagonal planar shape including the high-concentration contact layer 7 are arranged side by side while sharing the drain electrode 5. Is omitted.

  As shown in FIG. 1, a SiC growth layer 2 (semiconductor layer) made of SiC is formed on the surface of a semiconductor substrate 1 made of SiC (first semiconductor) by epitaxial growth. This SiC growth layer 2 is formed on the surface layer of SiC growth layer 2 other than the n-type drift layer body 2a (conductive region) containing impurities (nitrogen) and through which drift current flows and the region of drift surface 2b through which drift current passes. On the other hand, p-type well region 6 formed by implanting impurity ions (aluminum ions) from above, and impurity ions (aluminum ions) at a higher concentration in the region of well region 6 than SiC. And a p-type high-concentration contact layer 7 formed by being implanted into the surface layer of the growth layer 2.

  On the other hand, a drain electrode 5 made of aluminum metal in ohmic contact is disposed on the back surface of the semiconductor substrate 1.

  On the surface of the SiC growth layer 2, a Si growth layer 3 (channel layer) made of Si (second semiconductor) is formed by heteroepitaxial growth so as to extend to the well region 6 in contact with the drift surface 2b. The Si growth layer 3 includes an Si growth layer main body 3 a containing an n-type impurity (nitrogen) and having a channel region 10, and an Si growth layer main body 3 a extending from the Si growth layer main body 3 a to above the well region 6. and a region having an increased n-type impurity concentration. This region constitutes the source region 9.

  A well electrode 8 made of aluminum metal that is in ohmic contact with the high-concentration contact layer 7 is disposed. The potential of the well region 6 is fixed by the well electrode 8 (grounded state), whereby the channel region 10 can be depleted when the gate voltage is turned off, and the charge accumulated in the well region 6 by the switching operation of the MOSFET 100. Can be released to the well electrode 8 in the grounded state. In this case, the impurity concentration of the high concentration contact layer 7 is higher than that of the well region 6 in order to reliably obtain ohmic contact with the well electrode 8, but this concentration condition is not essential.

In addition, a gate insulating layer 4 (SiO ₂ layer) formed by thermal oxidation is in contact with the Si growth layer 3 so as to cover the entire area of the Si growth layer main body 3a and a part of the source region 9. Is arranged.

  Further, a source electrode 11 made of aluminum metal that is in ohmic contact with the source region 9 is disposed. Here, in order to reliably obtain ohmic contact with the source electrode 11, the source region 9 has an impurity concentration higher than that of the Si growth layer main body 3a, but this concentration condition is not essential.

  Further, by bringing the well electrode 8 and the high concentration contact layer 7 into direct contact, a predetermined potential can be reliably applied to the high concentration contact layer 7. Similarly, a predetermined potential can be reliably applied to the source region 9 by bringing the source electrode 11 and the source region 9 into direct contact.

  On the gate insulating layer 4, a gate electrode 12 made of aluminum metal is disposed so as to cover the entire region of the Si growth layer main body 3 a and a part of the source region 9 via the gate insulating layer 4. . As shown in FIG. 1, the channel region 10 corresponds to a layer sandwiched between the gate electrode 12 and the well region 6 and adjacent to the gate insulating layer 4. The channel region 10 includes the gate electrode 12 and the drain electrode 5. The impurity density is such that it is depleted when the potential difference between and is zero volts.

  Here, the SiC growth layer 2 has a wider band gap than that of a silicon semiconductor (band gap: 1.11 eV) or a GaAs semiconductor (band gap: 1.43 eV). Here, the SiC growth layer 2 may be replaced with a wide band gap semiconductor other than silicon carbide.

  A wide band gap semiconductor is a generic term for a material having a larger energy band gap (usually a band gap of 2 eV or more) than a silicon semiconductor or a GaAs semiconductor, which is a material parameter that characterizes the properties of the semiconductor.

  Examples of wide bandgap semiconductor materials include silicon carbide (bandgap: 3.26 eV), gallium nitride (bandgap: 3.39 eV), and diamond. Here, silicon with high dielectric strength and thermal conductivity is excellent. Carbide is used.

  The Si growth layer 3 is composed of a narrow band gap semiconductor having a narrow band gap (less than 2 eV) as typified by a silicon semiconductor. Examples of narrow band gap semiconductor materials include silicon, gallium arsenide, a compound containing silicon and germanium, or a compound containing silicon, germanium, and carbon.

  Further, the width L of the drift surface 2b (that is, the interval between adjacent wells 6) exceeds 0% of the thickness W of the SiC growth layer 2 and 50% or less (L / W ≦ 0.5), preferably The interval L between adjacent well regions 6 is adjusted to be sufficiently narrow so that it exceeds 0% and is 30% or less (L / W ≦ 0.3).

  Thus, when the gate voltage of the MOSFET 100 is turned off, the entire region between the well regions 6 in a state where a predetermined voltage (potential difference between the source electrode 11 and the drain electrode 5: more than 0 V and 40 V or less) is applied to the drain electrode 5 ( The conductive region under the drift surface 2b can be depleted.

  Thus, the narrow band gap semiconductor (Si growth layer 3) that can be closed between the well regions 6 by the depletion layer and stacked on the drift surface 2b is prevented from being exposed to a high electric field based on the voltage of the drain electrode 5. In addition, avalanche breakdown due to application of a high electric field can be effectively avoided.

  Of course, when the gate voltage of the MOSFET 100 is turned on, it can be said that the space between the well regions 6 needs to be wide enough to open the depletion layer between the well regions 6, but the pn junction depends on the impurity concentration of the drift layer body 2a. Therefore, the lower limit of the interval between the well regions 6 is appropriately designed according to the impurity concentration condition and the like.

  In addition to the control of the distance L between the well regions 6, an n-type region or a p-type region having a low doping density is separately disposed between the well regions 6 by doping impurities. May be depleted.

  Thus, the MOSFET 100 constituted by the semiconductor substrate 1, the SiC growth layer 2, the Si growth layer 3, the gate insulating layer 4, the drain electrode 5, the well electrode 8, the source electrode 11, and the gate electrode 12. Is obtained.

  In such a MOSFET 100, when a positive voltage is applied to the gate electrode 12, electrons are attracted to the channel region 10 by the electric field, and the portion becomes n-type, thereby turning on the channel region 10.

  In this way, electrons can move from the source region 9 to the channel region 10, the Si growth layer main body 3a, and the drift layer main body 2a toward the drain electrode 5, and the drift current is generated in the drift layer main body 2a. Flows vertically in the interior. That is, this device is a vertical power MOSFET that can control the drift current by applying a gate voltage.

  Of course, a lateral power MOSFET in which the drain electrode 5 is disposed on the surface layer of the SiC growth layer 2 may be used.

  According to the MOSFET 100 configured as described above, the depletion layer at the pn junction (the interface between the p-type well region 6 and the n-type drift layer body 2a) causes avalanche breakdown even in a high electric field application state. It exists in the area | region of the wide band gap semiconductor (SiC) which can suppress this. Therefore, the thickness of the drift layer body 2a can be reduced as compared with the conventional MOSFET in which the pn junction is arranged in the Si layer (because it is not necessary to increase the width of the depletion layer in consideration of dielectric breakdown). As a result, the drift resistance of MOSFET 100 can be reduced.

  In addition, since the channel region 10 exists in the Si growth layer main body 3a that improves the influence of the interface state and enables high channel mobility, the channel resistance of the MOSFET 100 can be reduced.

  If the drift resistance and the channel resistance of MOSFET 100 can be reduced, the conduction loss due to the on-resistance is improved, which effectively contributes to the suppression of heat generation of MOSFET 100.

  In addition, by using a SiC material having a wide band gap for the drift layer body 2a, generation of electron / hole pairs can be suppressed in the high temperature state of the MOSFET 100. In addition, by using a SiC material having excellent thermal conductivity (heat dissipation), even if the current capacity of the MOSFET 100 is increased, the thermal problem of the MOSFET 100 can be appropriately dealt with and a sufficient current capacity can be obtained. .

  Next, a method for manufacturing MOSFET 100 configured as described above will be described in detail with reference to the drawings.

  FIG. 2A to FIG. 2E are cross-sectional views illustrating each manufacturing process of the MOSFET according to the embodiment of the present invention.

First, in the step of FIG. 2A, the SiC growth layer 2 (n-type impurity semiconductor) is epitaxially grown on the semiconductor substrate 1 while performing in-situ doping of the added impurity (nitrogen) by the CVD method. . The thickness of the SiC growth layer 2 is about 10 μm, and the impurity concentration is about 5 × 10 ¹⁵ cm ⁻³ . As the semiconductor substrate 1, for example, a 4H—SiC substrate having a main surface of 75 mm in diameter with an off angle of 8 degrees in the [11-20] direction from (0001) is used. The impurity concentration in the semiconductor substrate 1 is about 1 × 10 ¹⁸ cm ⁻³ .

  Here, SiC growth layer 2 is formed by epitaxial growth, but if a SiC substrate having a low impurity concentration is obtained, a drift region may be formed in such a SiC substrate.

  Next, in the step of FIG. 2B, a well region forming implantation mask (not shown) made of, for example, nickel (Ni) metal is formed on the surface of the SiC growth layer 2. This Ni implantation mask covers the surface of the SiC growth layer 2 so that only a portion functioning as the well region 6 (p-type impurity semiconductor) is opened by implantation of Al ions (addition impurities).

  In this state, Al ion implantation is performed in multiple stages from above the Ni implantation mask into the SiC growth layer 2. Thereafter, the Ni implantation mask is removed by an appropriate method, and activation annealing treatment for crystal recovery is performed on the SiC growth layer 2 under a temperature condition of about 1500 ° C. to 1800 ° C.

Thereby, as shown in FIG. 2B, a part of the SiC growth layer 2 is converted into the well region 6 having an impurity concentration of 1 × 10 ¹⁸ cm ⁻³ . Further, in the SiC growth layer 2, a region excluding the well region 6 becomes the drift layer body 2 a. The impurity concentration of the drift layer body 2a is about 5 × 10 ¹⁵ cm ⁻³ as described above.

  Subsequently, an implantation mask (not shown) for a high concentration contact layer made of, for example, aluminum (Al) metal is formed on the surface of the SiC growth layer 2. This Al implantation mask covers the surface of the SiC growth layer 2 so that only a portion functioning as the high-concentration contact layer 7 (p-type impurity semiconductor) is opened by implantation of Al ions (addition impurities). In this state, Al ion implantation is performed in multiple stages from above the Al implantation mask into the SiC growth layer 2.

  Thereafter, the Al implantation mask is removed by an appropriate method, and activation annealing treatment for crystal recovery is performed on the SiC growth layer 2 under a temperature condition of about 1500 ° C. to 1800 ° C.

As a result, as shown in FIG. 2B, a part of the SiC growth layer 2 in the region of the well region 6 is converted into a high concentration contact layer 7 having an impurity concentration of 1 × 10 ¹⁹ cm ⁻³ .

  Next, in the step of FIG. 2C, the Si growth layer 3 (n-type impurity semiconductor) is heterogeneously formed on the entire surface of the SiC growth layer 2 while performing in-situ doping of the added impurity (nitrogen) by the CVD method. Epitaxially grown.

  Instead of the Si growth layer 3, a polysilicon layer or an amorphous silicon layer may be formed.

The thickness of the Si growth layer 3 is about 0.2 μm, and the impurity concentration of the Si growth layer 3 is about 1 × 10 ¹⁴ cm ⁻³ .

  Next, in the step of FIG. 2D, a source region implantation mask (not shown) made of, for example, nickel (Ni) metal is formed on the surface of the Si growth layer 3. This Ni implantation mask covers the surface of the Si growth layer 3 so that only a portion functioning as the source region 9 (n-type impurity semiconductor) is opened by implantation of phosphorous ions of added impurities. In this state, phosphorus ion implantation is performed in multiple stages from above the Ni implantation mask into the Si growth layer 3.

  Thereafter, the Ni implantation mask is removed by an appropriate method, and an activation annealing process for crystal recovery is performed on the Si growth layer 3 under a temperature condition of about 800 ° C.

  Subsequently, the Si growth layer 3 existing above the high concentration contact layer 7 is removed by patterning by etching.

Thereby, as shown in FIG. 2D, a part of the Si growth layer 3 above the well region 6 is converted into the source region 9 having an impurity concentration of 1 × 10 ¹⁹ cm ⁻³ . In the Si growth layer 3, the region excluding the source region 9 becomes the Si growth layer main body 3a.

Next, in the step of FIG. 2E, the surface of the Si growth layer 3 is thermally oxidized at a temperature of about 900 ° C., thereby forming the gate insulating layer 4 made of a SiO ₂ layer on the entire surface of the Si growth layer 3. After that, a part of the gate insulating layer 4 is removed by etching so as to expose the source region 9 in contact with the source electrode 11 (see FIG. 1).

The gate insulating layer 4 has a thickness of about 80 nm. Here, although a thermal oxidation technique is used as a method for forming the gate insulating layer, a CVD method may be used. Further, the gate insulating layer is not limited to the SiO ₂ layer, and may be, for example, a SiN layer.

  Thereafter, an aluminum metal layer is formed on the entire front and back surfaces of the substrate 1 by electron beam (EB) vapor deposition, and patterning treatment and ohmic contact between the metal and the semiconductor are performed on the aluminum metal layer by an appropriate method. By performing this heat treatment, a gate electrode 12, a source electrode 11, a well electrode 8, and a drain electrode 5 are formed as shown in FIG.

  The width t of the channel region 10 of the MOSFET 100 (FIG. 1) fabricated in this way was 1 μm, and the interval L between adjacent well regions 6 was 2 μm.

  The depth d1 of the well region 6 was 1 μm, the depth d2 of the high concentration contact layer 7 was 0.2 μm, and the thickness d3 of the source region 9 was 0.2 μm.

Then, 3 mΩcm ² was achieved as the on-resistance of the MOSFET 100, and a high withstand voltage characteristic (1000 V) was obtained.

  Note that, up to this point, an n-channel MOSFET has been described as an example, but a similar effect can be obtained even with a p-channel MOSFET. In this case, since the heterojunction between the n-type Si growth layer and the n-type SiC growth layer has no rectifying property, the well electrode for the well region can be disposed on the surface of the Si growth layer. Thus, the manufacturing process can be simplified by omitting the etching process of removing a part of the Si growth layer above the well region.

  Further, a MOSFET is fabricated by epitaxially growing a SiC growth layer of the same conductivity type on a SiC semiconductor substrate of a predetermined conductivity type, but SiC growth of a different conductivity type is performed on a SiC semiconductor substrate of a predetermined conductivity type. Even if an IGBT is manufactured by the method of forming a layer, the effect of the present invention can be obtained.

  In addition, although the substrate whose main surface is the 4H—SiC (0001) off surface is used, a substrate whose main surface is a surface other than the 4H—SiC (0001) off surface may be used. A SiC substrate made of a type may be used.

  According to the present invention, a semiconductor device capable of reducing on-resistance corresponding to conduction loss can be obtained, and can be applied to a power semiconductor device and the like that realize energy saving.

It is sectional drawing of the structure of n channel type power MOSFET which concerns on embodiment of this invention. It is sectional drawing explaining each step of the manufacturing process of the semiconductor device which concerns on embodiment of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 2 SiC growth layer 3 Si growth layer 4 Gate insulating layer 5 Drain electrode 6 Well region 7 High concentration contact layer 8 Well electrode 9 Source region 10 Channel region 11 Source electrode 12 Gate electrode

Claims (10)

A semiconductor layer made of a first semiconductor;
A second conductivity type well region formed so as to include the surface of the semiconductor layer in the semiconductor layer;
A conductive region of a first conductivity type formed in the semiconductor layer over the entire thickness of the semiconductor layer in contact with the well region;
A channel layer made of a semiconductor formed on at least a part of the well region and at least a part of the conductive region;
A gate electrode formed on the channel layer,
A semiconductor device in which at least a part of the channel layer located below the gate electrode is made of a second semiconductor, and the band gap of the first semiconductor is larger than the band gap of the second semiconductor.   The semiconductor device according to claim 1, further comprising a first conductivity type substrate made of the first semiconductor, wherein the semiconductor layer is formed on the substrate.   The semiconductor device according to claim 1, wherein the channel layer is composed of the second semiconductor.   The semiconductor device according to claim 2, wherein the concentration of the added impurity is lower in the conductive region than in the substrate.   The semiconductor device according to claim 1, wherein the first semiconductor is any one of silicon carbide, gallium nitride, and diamond.   2. The semiconductor device according to claim 1, wherein the second semiconductor is one of silicon, gallium arsenide, a compound containing silicon and germanium, and a compound containing silicon, germanium, and carbon.   The channel layer has the first conductivity type, and includes a main body portion including a channel region, and a region extending from the main body portion and having a higher concentration of additive impurities than the main body portion, The semiconductor device according to claim 1, wherein a first electrode that contacts the region is disposed.   The semiconductor device according to claim 7, wherein an interval between the adjacent well regions on the upper surface of the conductive region in contact with the channel layer is greater than 0% and less than or equal to 50% of the thickness of the semiconductor layer.   A second electrode that contacts the back surface of the substrate, and the adjacent well region that sandwiches the conductive region located below the top surface are disposed, and between the first electrode and the second electrode The semiconductor device according to claim 8, wherein the conductive region between the adjacent well regions is depleted in a state where the applied potential difference is equal to or less than a predetermined value.   The semiconductor device according to claim 9, wherein the predetermined value of the potential difference exceeds 0 V and is 40 V or less.

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