JP7106882B2 - Semiconductor device and method for manufacturing semiconductor device - Google Patents

Description

The present invention relates to a semiconductor device and a method of manufacturing a semiconductor device.

Conventionally, silicon (Si) has been used as a constituent material of power semiconductor devices that control high voltages and large currents. There are multiple types of power semiconductor devices, including bipolar transistors, IGBTs (Insulated Gate Bipolar Transistors), and MOSFETs (Metal Oxide Semiconductor Field Effect Transistors). It is

For example, bipolar transistors and IGBTs have higher current densities than MOSFETs and can handle large currents, but cannot be switched at high speed. Specifically, bipolar transistors are limited to use at a switching frequency of about several kHz, and IGBTs are limited to use at a switching frequency of about several tens of kHz. On the other hand, a power MOSFET has a lower current density than a bipolar transistor or an IGBT, making it difficult to increase the current, but it is capable of high-speed switching operation up to several MHz.

However, there is a strong demand in the market for power semiconductor devices that combine large current and high speed, and efforts have been made to improve IGBTs and power MOSFETs. . From the viewpoint of power semiconductor devices, semiconductor materials that can replace silicon are being investigated, and silicon carbide (SiC) is a semiconductor material that can be used to fabricate (manufacture) next-generation power semiconductor devices with excellent low on-voltage, high-speed characteristics, and high-temperature characteristics. is attracting attention.

Silicon carbide is a chemically very stable semiconductor material, has a wide bandgap of 3 eV, and can be extremely stably used as a semiconductor even at high temperatures. In addition, since silicon carbide has a maximum electric field strength that is one order of magnitude higher than that of silicon, silicon carbide is expected as a semiconductor material capable of sufficiently reducing the on-resistance. Such features of silicon carbide also apply to other wide bandgap semiconductors, such as gallium nitride (GaN), which have a wider bandgap than silicon. Therefore, by using a wide bandgap semiconductor, it is possible to increase the breakdown voltage of the semiconductor device.

FIG. 20 is a cross-sectional view showing the structure of a conventional silicon carbide semiconductor device. As shown in FIG. 20, a general trench gate structure is provided on the front surface (the surface on the side of p ⁻ -type silicon carbide epitaxial layer 103) of a semiconductor substrate (hereinafter referred to as silicon carbide semiconductor substrate) 200 made of silicon carbide. of MOS gates. A silicon carbide semiconductor substrate (semiconductor chip) 200 includes an n ⁻ -type silicon carbide epitaxial layer 102 on an n ⁺ -type support substrate (hereinafter referred to as an n ⁺ -type silicon carbide substrate) 101 made of silicon carbide, n Each silicon carbide layer to be type high concentration region 106 and p ⁻ type silicon carbide epitaxial layer 103 is epitaxially grown in order.

A first p ⁺ -type base region 104 is selectively provided between adjacent trenches 118 (mesa portion) in the n-type high-concentration region 106 . A second p ⁺ -type base region 105 that partially covers the bottom surface of the trench 118 is selectively provided in the n-type high-concentration region 106 . First p ⁺ -type base region 104 is provided in contact with p ⁻ -type silicon carbide epitaxial layer 103 . Second p ⁺ -type base region 105 is provided at a depth that does not reach n ⁻ -type silicon carbide epitaxial layer 102 . The second p ⁺ -type base region 105 and the first p ⁺ -type base region 104 may be formed at the same time.

Reference numerals 107 to 112 denote n ⁺ -type source regions, p ⁺ -type contact regions, gate insulating films, gate electrodes, interlayer insulating films and source electrodes, respectively. A back electrode (not shown) is provided on the back side of n ⁺ -type silicon carbide substrate 101 .

In addition, regarding the reduction of the on-resistance of a trench-type silicon carbide semiconductor device, by forming a bulging portion in the vicinity of the bottom of the trench and filling it with a buried insulating film, strain is applied to the SiC crystal of the channel portion, and the on-resistance is reduced. is reduced, the distance between adjacent bulges is shortened, and the saturation current is suppressed (for example, see Patent Document 1 below).

JP 2016-213374 A

Here, in the trench-type silicon carbide semiconductor device, the on-resistance (RonA) is the resistance of the n ⁺ -type silicon carbide substrate 101, the resistance of the n ⁻ -type silicon carbide epitaxial layer 102, the resistance of the n-type heavily doped region 106, and the p It consists of a resistance of ⁻ type silicon carbide epitaxial layer 103 (hereinafter referred to as a channel resistance) and a resistance of n ⁺ type source region 107 . Since the impurity concentration of p ⁻ -type silicon carbide epitaxial layer 103 is low, the on-resistance can be efficiently lowered by lowering the channel resistance. The channel resistance can be reduced, for example, by shortening the cell pitch (distance w between trenches 118) or channel length (thickness h of p ⁻ -type silicon carbide epitaxial layer 103).

FIG. 21 is a graph showing the relationship between drain voltage and drain current in a conventional silicon carbide semiconductor device. In FIG. 21, the horizontal axis indicates the drain voltage, and the vertical axis indicates the drain current. As shown in FIG. 21, when the drain voltage is increased and the drain voltage reaches the pinch-off voltage, the width of the channel becomes 0 or the charge in the channel becomes 0, thereby increasing the drain voltage. Also, the drain current hardly increases.

On the other hand, until the pinch-off voltage is reached, the drain current increases depending on the on-resistance. Therefore, when the channel resistance is decreased and the on-resistance is decreased, the value at which the drain current hardly increases (hereinafter referred to as saturation current (Isat)) increases. In FIG. 21, line A indicates a case where the on-resistance is large, and line B indicates a case where the on-resistance is small, and the smaller the on-resistance, the larger the saturation current.

Here, FIG. 22 is a graph showing the relationship between short-circuit breakdown and saturation current in a conventional silicon carbide semiconductor device. In FIG. 22, the horizontal axis indicates time, and the vertical axis indicates drain current. As shown in FIG. 22, the drain current stops increasing when the saturation current is reached. Short-circuit breakdown is determined by the amount of energy obtained by integrating the time during which the saturation current is flowing and the power supply voltage. When the channel resistance is reduced, the saturation current increases, so the amount of energy described above increases, making short-circuit breakdown more likely to occur, and the short-circuit withstand capability lowers. As described above, in the silicon carbide semiconductor device, since the on-resistance and the saturation current are in a trade-off relationship (inversely proportional), there is a problem that if the on-resistance is reduced, the short-circuit withstand capability is lowered.

In order to solve the above-described problems of the prior art, the present invention improves the trade-off between on-resistance and saturation current, and manufactures a semiconductor device in which the rate of decrease in short-circuit resistance is small even if the on-resistance is reduced. The purpose is to provide a method.

In order to solve the above problems and achieve the object of the present invention, a semiconductor device according to the present invention has the following features. A first semiconductor layer of a first conductivity type having an impurity concentration lower than that of the semiconductor substrate is provided on the front surface of the semiconductor substrate of the first conductivity type. A second conductive type second semiconductor layer is provided on the side of the first semiconductor layer opposite to the semiconductor substrate side. A first conductivity type first semiconductor region having an impurity concentration higher than that of the semiconductor substrate is selectively provided inside the second semiconductor layer. A trench is provided through the first semiconductor region and the second semiconductor layer to reach the first semiconductor layer. A gate electrode is provided inside the trench with a gate insulating film interposed therebetween. A second conductive type second semiconductor region is selectively provided inside the first semiconductor layer. A third semiconductor region of a second conductivity type is selectively provided inside the first semiconductor layer and is in contact with the bottom surface of the trench. A first electrode is provided on the surface of the second semiconductor layer and the first semiconductor region. A second electrode is provided on the back surface of the semiconductor substrate. The second semiconductor region and the third semiconductor region each have a protrusion extending in the width direction of the trench, the protrusion being provided closer to the first electrode than the bottom surface of the trench. When the voltage of the second electrode is the operating voltage, the distance between the portions is a first depletion layer between the second semiconductor region and the first semiconductor layer, and a distance between the third semiconductor region and the first semiconductor layer. The first depletion layer and the second depletion layer close when the second depletion layer between the layers does not close and the voltage of the second electrode is higher than the operating voltage and lower than the voltage of the gate electrode. Distance.

In order to solve the above problems and achieve the object of the present invention, a semiconductor device according to the present invention has the following features. A first semiconductor layer of a first conductivity type having an impurity concentration lower than that of the semiconductor substrate is provided on the front surface of the semiconductor substrate of the first conductivity type. A second conductive type second semiconductor layer is provided on the side of the first semiconductor layer opposite to the semiconductor substrate side. A first conductivity type first semiconductor region having an impurity concentration higher than that of the semiconductor substrate is selectively provided inside the second semiconductor layer. A trench is provided through the first semiconductor region and the second semiconductor layer to reach the first semiconductor layer. A gate electrode is provided inside the trench with a gate insulating film interposed therebetween. A second conductive type second semiconductor region is selectively provided inside the first semiconductor layer. A third semiconductor region of a second conductivity type is selectively provided inside the first semiconductor layer and is in contact with the bottom surface of the trench. A first electrode is provided on the surface of the second semiconductor layer and the first semiconductor region. A second electrode is provided on the back surface of the semiconductor substrate. A second conductivity type fourth semiconductor region protruding toward the second semiconductor region is provided on the surface of the third semiconductor region on the second semiconductor layer side. The fourth semiconductor region is provided closer to the first electrode than the bottom surface of the trench. a distance between the fourth semiconductor region and the second semiconductor region is a first depletion layer between the second semiconductor region and the first semiconductor layer when the voltage of the second electrode is an operating voltage; When the second depletion layer between the third semiconductor region and the first semiconductor layer does not close and the voltage of the second electrode is higher than the operating voltage and lower than the voltage of the gate electrode, the first depletion is the close distance between the layer and the second depletion layer.

Moreover, in the semiconductor device according to the present invention, in the invention described above, the distance is 0.5 μm or more and 0.9 μm or less.

In order to solve the above problems and achieve the object of the present invention, a method of manufacturing a semiconductor device according to the present invention has the following features. First, a first step of forming a first semiconductor layer of a first conductivity type having an impurity concentration lower than that of the semiconductor substrate on a front surface of a semiconductor substrate of the first conductivity type is performed. Next, a second step of forming a second conductive type second semiconductor layer on the side of the first semiconductor layer opposite to the semiconductor substrate is performed. Next, a third step of selectively forming a first conductivity type first semiconductor region having a higher impurity concentration than the semiconductor substrate inside the second semiconductor layer is performed. Next, a fourth step of forming a trench penetrating through the first semiconductor region and the second semiconductor layer and reaching the first semiconductor layer is performed. Next, a fifth step of forming a gate electrode inside the trench via a gate insulating film is performed. Next, a sixth step of selectively forming a second conductivity type second semiconductor region inside the first semiconductor layer is performed. Next, a seventh step of selectively forming a third semiconductor region of the second conductivity type in contact with the bottom surface of the trench inside the first semiconductor layer is performed. Next, an eighth step of forming a first electrode on the surfaces of the second semiconductor layer and the first semiconductor region is performed. Next, a ninth step of forming a second electrode on the back surface of the semiconductor substrate is performed. Next, a tenth step of forming protrusions extending in the width direction of the trenches in the second semiconductor region and the third semiconductor region is performed. The protrusion is formed closer to the first electrode than the bottom surface of the trench, and the distance between the protrusions is such that when the voltage of the second electrode is the operating voltage, the distance between the second semiconductor region and the first electrode is the same as that of the second semiconductor region. The first depletion layer between the semiconductor layer and the second depletion layer between the third semiconductor region and the first semiconductor layer are not closed, the voltage of the second electrode is higher than the operating voltage, and the It is the distance at which the first depletion layer and the second depletion layer close when the voltage is lower than the voltage of the gate electrode. In order to solve the above problems and achieve the object of the present invention, a method of manufacturing a semiconductor device according to the present invention has the following features. First, a first step of forming a first semiconductor layer of a first conductivity type having an impurity concentration lower than that of the semiconductor substrate on a front surface of a semiconductor substrate of the first conductivity type is performed. Next, a second step of forming a second conductive type second semiconductor layer on the side of the first semiconductor layer opposite to the semiconductor substrate is performed. Next, a third step of selectively forming a first conductivity type first semiconductor region having a higher impurity concentration than the semiconductor substrate inside the second semiconductor layer is performed. Next, a fourth step of forming a trench penetrating through the first semiconductor region and the second semiconductor layer and reaching the first semiconductor layer is performed. Next, a fifth step of forming a gate electrode inside the trench via a gate insulating film is performed. Next, a sixth step of selectively forming a second conductivity type second semiconductor region inside the first semiconductor layer is performed. Next, a seventh step of selectively forming a third semiconductor region of the second conductivity type in contact with the bottom surface of the trench inside the first semiconductor layer is performed. Next, an eighth step of forming a first electrode on the surfaces of the second semiconductor layer and the first semiconductor region is performed. Next, a ninth step of forming a second electrode on the back surface of the semiconductor substrate is performed. Next, a tenth step of forming a fourth semiconductor region of the second conductivity type protruding toward the second semiconductor region on the surface of the third semiconductor region on the second semiconductor layer side is performed. The fourth semiconductor region is formed closer to the first electrode than the bottom surface of the trench, and the distance between the fourth semiconductor region and the second semiconductor region is set when the voltage of the second electrode is the operating voltage. , a first depletion layer between the second semiconductor region and the first semiconductor layer and a second depletion layer between the third semiconductor region and the first semiconductor layer are not closed, and the second electrode is the distance at which the first depletion layer and the second depletion layer close when the voltage of is higher than the operating voltage and lower than the voltage of the gate electrode.

According to the above invention, the width between the first p ⁺ -type base region (second conductivity type second semiconductor region) and the second p ⁺ -type base region (second conductivity type third semiconductor region) is less than the conventional width It is narrower than the silicon carbide semiconductor device. As a result, the depletion layer closes when the drain voltage is higher than the voltage during normal operation and lower than the gate voltage, and the drain current saturates at a lower drain voltage than conventional, resulting in a low saturation current. Therefore, even if the on-resistance is reduced by reducing the channel resistance, the saturation current does not increase as much as in the conventional case, and the short-circuit withstand capability is less likely to decrease.

According to the semiconductor device and the method for manufacturing a semiconductor device according to the present invention, the trade-off between the on-resistance and the saturation current is improved, and even if the on-resistance is reduced, the rate of decrease in short-circuit withstand capability is small.

1 is a cross-sectional view showing the structure of a silicon carbide semiconductor device according to a first embodiment; FIG. FIG. 10 is a cross-sectional view showing a depletion layer of a conventional silicon carbide semiconductor device; 5 is a graph showing the relationship between drain voltage and drain current in the silicon carbide semiconductor device according to the first embodiment; 7 is a graph showing simulation results of the relationship between drain voltage and drain current in the silicon carbide semiconductor device according to the first embodiment (part 1); 7 is a graph showing simulation results of the relationship between drain voltage and drain current in the silicon carbide semiconductor device according to the first embodiment (part 2); 5 is a graph showing the relationship between saturation current and on-resistance in the silicon carbide semiconductor device according to the first embodiment; FIG. 3 is a cross-sectional view showing a state in the middle of manufacturing the silicon carbide semiconductor device according to the first embodiment (Part 1); FIG. 2 is a cross-sectional view showing a state in the middle of manufacturing the silicon carbide semiconductor device according to the first embodiment (No. 2); 3 is a cross-sectional view showing a state in the middle of manufacturing the silicon carbide semiconductor device according to the first embodiment (No. 3); FIG. FIG. 4 is a cross-sectional view showing a state in the middle of manufacturing the silicon carbide semiconductor device according to the first embodiment (No. 4); FIG. 5 is a cross-sectional view showing a state in the middle of manufacturing the silicon carbide semiconductor device according to the first embodiment (No. 5); FIG. 6 is a cross-sectional view showing a state in the middle of manufacturing the silicon carbide semiconductor device according to the first embodiment (No. 6); FIG. 11 is a cross-sectional view showing a state in the middle of manufacturing the silicon carbide semiconductor device according to the first embodiment (No. 7); It is a cross-sectional view showing the structure of a silicon carbide semiconductor device according to a second embodiment. FIG. 11 is a cross-sectional view schematically showing a state in the middle of manufacturing the silicon carbide semiconductor device according to the second embodiment (No. 1); FIG. 12 is a cross-sectional view schematically showing a state in the middle of manufacturing the silicon carbide semiconductor device according to the second embodiment (No. 2); FIG. 9 is a cross-sectional view schematically showing a state in the middle of manufacturing the silicon carbide semiconductor device according to the second embodiment (No. 3); It is a cross-sectional view showing the structure of a silicon carbide semiconductor device according to a third embodiment. FIG. 11 is a cross-sectional view schematically showing a state in the middle of manufacturing a silicon carbide semiconductor device according to a third embodiment; 5 is a graph showing the relationship between drain voltage and drain current in the silicon carbide semiconductor devices according to the first, second and third embodiments; It is a cross-sectional view showing the structure of a conventional silicon carbide semiconductor device. 7 is a graph showing the relationship between drain voltage and drain current in a conventional silicon carbide semiconductor device; 7 is a graph showing the relationship between short-circuit breakdown and saturation current in a conventional silicon carbide semiconductor device;

Preferred embodiments of a semiconductor device and a method of manufacturing a semiconductor device according to the present invention will be described in detail below with reference to the accompanying drawings. In this specification and the accompanying drawings, layers and regions prefixed with n or p mean that electrons or holes are majority carriers, respectively. Also, + and - attached to n and p mean that the impurity concentration is higher and lower than that of the layer or region not attached, respectively. When the notations of n and p including + and - are the same, it indicates that the concentrations are close, and the concentrations are not necessarily the same. In the following description of the embodiments and the accompanying drawings, the same configurations are denoted by the same reference numerals, and overlapping descriptions are omitted. Also, in this specification, in the notation of the Miller index, "-" means a bar attached to the index immediately after it, and adding "-" before the index indicates a negative index.

(Embodiment 1)
A semiconductor device according to the present invention is configured using a wide bandgap semiconductor. In Embodiment 1, a silicon carbide semiconductor device manufactured using, for example, silicon carbide (SiC) as a wide bandgap semiconductor will be described using a MOSFET as an example. FIG. 1 is a cross-sectional view showing the structure of the silicon carbide semiconductor device according to the first embodiment.

As shown in FIG. 1, the silicon carbide semiconductor device according to the first embodiment includes a first main surface (front surface) of an n ⁺ -type silicon carbide substrate (first conductivity type semiconductor substrate) 1, for example, (0001 ) plane (Si plane), an n ⁻ -type silicon carbide epitaxial layer (first conductivity type first semiconductor layer) 2 is deposited.

The n ⁺ -type silicon carbide substrate 1 is, for example, a silicon carbide single crystal substrate doped with nitrogen (N). The n ⁻ -type silicon carbide epitaxial layer 2 is a low-concentration n-type drift layer doped with, for example, nitrogen at an impurity concentration lower than that of the n ⁺ -type silicon carbide substrate 1 . An n-type high-concentration region 6 is formed on the surface of n ⁻ -type silicon carbide epitaxial layer 2 opposite to n ⁺ -type silicon carbide substrate 1 side. The n-type high-concentration region 6 is a high-concentration n-type drift layer doped with nitrogen, for example, at an impurity concentration lower than that of the n ⁺ -type silicon carbide substrate 1 and higher than that of the n ⁻ -type silicon carbide epitaxial layer 2 . Hereinafter, the n ⁺ -type silicon carbide substrate 1, the n ^- -type silicon carbide epitaxial layer 2, and the later-described p ^- -type silicon carbide epitaxial layer (second conductivity type second semiconductor layer) 3 are collectively referred to as a silicon carbide semiconductor substrate 100. do.

A back surface electrode (second electrode) 14 is provided on the second main surface (back surface, ie, the back surface of the silicon carbide semiconductor substrate) of n ⁺ -type silicon carbide substrate 1 . The back electrode 14 constitutes a drain electrode. A drain electrode pad (not shown) is provided on the surface of the back electrode 14 .

A trench structure is formed on the first main surface side (p ⁻ type silicon carbide epitaxial layer 3 side) of the silicon carbide semiconductor substrate. Specifically, trench 18 is formed from the surface of p ^{− -type} silicon carbide epitaxial layer 3 on the side opposite to n ⁺ -type silicon carbide substrate 1 (the first main surface side of the silicon carbide semiconductor substrate). It penetrates silicon epitaxial layer 3 and reaches n ⁻ -type silicon carbide epitaxial layer 2 . A gate insulating film 9 is formed on the bottom and sidewalls of trench 18 along the inner wall of trench 18 , and gate electrode 10 is formed inside gate insulating film 9 in trench 18 . Gate electrode 10 is insulated from n ⁻ type silicon carbide epitaxial layer 2 and p ⁻ type silicon carbide epitaxial layer 3 by gate insulating film 9 . A portion of the gate electrode 10 protrudes from above the trench 18 (source electrode 12 side) toward the source electrode 12 side.

A first p ^{+ -type} base region ⁽ second conductivity type second semiconductor region) 4 and a second p ⁺ -type base region (second conductivity type third semiconductor region) 5 are selectively provided. The second p ⁺ -type base region 5 is formed under the trench 18 and the width of the second p ⁺ -type base region 5 is wider than the width of the trench 18 . The first p ⁺ -type base region 4 and the second p ⁺ -type base region 5 are doped with aluminum, for example.

A structure in which a part of the first p ⁺ -type base region 4 is extended to the trench 18 side and connected to the second p ⁺ -type base region 5 may be employed. In this case, a part of the first p ⁺ -type base region 4 is oriented in a direction (hereinafter referred to as a first direction) orthogonal to x in which the first p ⁺ -type base region 4 and the second p ⁺ -type base region 5 are arranged. , and the second direction) y, the n-type high-concentration regions 6 may be alternately and repeatedly arranged in a planar layout.

A p ⁻ -type silicon carbide epitaxial layer 3 is provided on the substrate first main surface side of the n ⁻ -type silicon carbide epitaxial layer 2 . Inside p ⁻ -type silicon carbide epitaxial layer 3, n ⁺ -type source region (first conductivity type first semiconductor region) 7 and p ⁺ -type contact region 8 are selectively provided on the first main surface side of the substrate. ing. The n ⁺ -type source region 7 is in contact with the trench 18 . Also, the n ⁺ -type source region 7 and the p ⁺ -type contact region 8 are in contact with each other. Also, a region sandwiched between the first p ⁺ -type base region 4 and the second p ⁺ -type base region 5 in the surface layer of the n ⁻ -type silicon carbide epitaxial layer 1 on the substrate first main surface side, and the p ⁻ -type silicon carbide epitaxial layer 3 and the second p ⁺ -type base region 5, an n-type high-concentration region 6 is provided.

Although only two trench MOS structures are shown in FIG. 1, more trench MOS gate (metal-oxide-semiconductor insulating gate) structures may be arranged in parallel.

Interlayer insulating film 11 is provided all over the first main surface side of the silicon carbide semiconductor substrate so as to cover gate electrode 10 embedded in trench 18 . Source electrode 12 is in contact with n ⁺ -type source region 7 and p ⁺ -type contact region 8 through a contact hole opened in interlayer insulating film 11 . Source electrode 12 is electrically insulated from gate electrode 10 by interlayer insulating film 11 . A source electrode pad (not shown) is provided on the source electrode 12 . A barrier metal (not shown) may be provided between the source electrode 12 and the interlayer insulating film 11 to prevent diffusion of metal atoms from the source electrode 12 to the gate electrode 10 side, for example.

In the silicon carbide semiconductor device of the first embodiment, the width (hereinafter referred to as JFET width) L1 between first p ⁺ -type base region 4 and second p ⁺ -type base region 5 is the JFET width L11 of the conventional silicon carbide semiconductor device. narrower (L1<L11). For example, JFET width L1 can be narrowed by making at least one of the width of first p ⁺ -type base region 4 and the width of second p ⁺ -type base region 5 wider than the conventional silicon carbide semiconductor device.

The JFET width L1 is set so that the depletion layer S does not close at a drain voltage of about 1 V during normal operation in the silicon carbide semiconductor device, and the depletion layer S closes when the drain voltage is higher than the voltage during normal operation and lower than the gate voltage. width. FIG. 1 shows an example in which the depletion layer S is closed. Specifically, when the gate voltage is 20 V, the depletion layer S is closed when the drain voltage is higher than 2 V and lower than 19 V by setting the JFET width L1 to 0.5 μm or more and 0.9 μm or less.

Here, the closure of the depletion layer S means that the depletion layer at the pn interface between the first p ⁺ -type base region 4 and the n-type high concentration region 6 or the n ⁻ -type silicon carbide epitaxial layer 2 and the second p ⁺ -type base region The depletion layer at the pn interface between 5 and n-type high concentration region 6 or n ⁻ -type silicon carbide epitaxial layer 2 comes into contact with each other.

Here, FIG. 2 is a cross-sectional view showing a depletion layer of a conventional silicon carbide semiconductor device. In the conventional silicon carbide semiconductor device, since JFET width L11 is wider than that of the first embodiment, depletion layer S does not close even if the drain voltage becomes approximately the same as the gate voltage. Therefore, the drain current increases according to the drain voltage until pinch-off occurs, and the drain current saturates when the drain voltage becomes approximately the same as the gate voltage.

On the other hand, in Embodiment 1, the depletion layer S closes when the drain voltage is higher than the voltage during normal operation and lower than the gate voltage, so the drain current is saturated at this point. That is, the drain current saturates at a voltage lower than the pinch-off voltage (hereinafter referred to as JFET pinch-off voltage) which is approximately the same as the gate voltage.

FIG. 3 is a graph showing the relationship between drain voltage and drain current in the silicon carbide semiconductor device according to the first embodiment. In FIG. 3, the horizontal axis indicates the drain voltage, the vertical axis indicates the drain current, the line A indicates the relationship between the drain voltage and the drain current in the conventional silicon carbide semiconductor device for comparison, and the line B indicates the relationship between the drain voltage and the drain current in the conventional silicon carbide semiconductor device. It is the relationship between the drain voltage and the drain current when the JFET width L1 of the first embodiment is applied, and the line C shows the drain voltage and the drain current when the JFET width L1 of the first embodiment is applied and the channel resistance is reduced. It is the relationship with current.

As shown in FIG. 3, in the conventional line A, the drain current is saturated at the pinch-off voltage, whereas in the lines B and C, the drain current is saturated at the JFET pinch-off voltage lower than the pinch-off voltage. , the saturation voltage is lower. Since line C reduces the channel resistance, drain current is higher for the same drain voltage, and line C has a higher saturation current.

Here, FIGS. 4A and 4B are graphs showing simulation results of the relationship between drain voltage and drain current in the silicon carbide semiconductor device according to the first embodiment. FIG. 4B is an enlarged view of the low voltage portion of FIG. 4A. 4A and 4B, the horizontal axis indicates drain voltage in units of V, and the vertical axis indicates drain current in units of A/cm ² .

The simulation was performed by applying a gate voltage of 20 V to a 1200 V class silicon carbide semiconductor device. The conventional structure had a cell pitch of 6 μm and an on-resistance of 4.09 mΩcm ² . In Embodiment 1, the JFET width L1 was narrowed, the cell pitch was set to 4 μm, and the on-resistance was 3.39 mΩcm ² . As shown in FIGS. 4A and 4B, the saturation current of the first embodiment is lower than that of the conventional structure.

Next, FIG. 5 is a graph showing the relationship between saturation current and on-resistance in the silicon carbide semiconductor device according to the first embodiment. In FIG. 5, the horizontal axis indicates the ON resistance, and the vertical axis indicates the saturation current. For comparison, the solid line represents the relationship between the saturation current and the on-resistance in the silicon carbide semiconductor device of the conventional structure, and the dotted line represents the relationship between the saturation current and the on-resistance when the JFET width L1 of the first embodiment is applied. .

As shown in FIG. 5, the first embodiment also has a trade-off between the on-resistance and the saturation current as in the conventional structure. However, in the on-resistance region A, the first embodiment has a lower saturation current with the same on-resistance than the conventional structure, and the trade-off between on-resistance and saturation current is improved. Therefore, in the first embodiment, even if the on-resistance is decreased, the short-circuit withstand capability is less likely to decrease. Further, in the first embodiment, since the JFET width L1 is narrowed, the resistance of this portion increases, but the channel resistance can be lowered, so that the on-resistance can be reduced.

(Method for Manufacturing Semiconductor Device According to First Embodiment)
Next, a method for manufacturing the silicon carbide semiconductor device according to the first embodiment will be described. 6 to 12 are cross-sectional views schematically showing states in the middle of manufacturing the silicon carbide semiconductor device according to the first embodiment.

First, an n ⁺ -type silicon carbide substrate 1 made of n-type silicon carbide is prepared. Then, on the first main surface of this n ⁺ -type silicon carbide substrate 1, a first n ⁻ -type silicon carbide epitaxial layer 2a made of silicon carbide while being doped with n-type impurities such as nitrogen atoms is deposited, for example, to a thickness of about 30 μm. Epitaxially grown to a thickness. This first n ⁻ -type silicon carbide epitaxial layer 2 a becomes n ⁻ -type silicon carbide epitaxial layer 1 . The state up to this point is shown in FIG.

Next, an ion implantation mask having a predetermined opening is formed of, for example, an oxide film on the surface of the first n ⁻ -type silicon carbide epitaxial layer 2a by photolithography. Then, a p-type impurity such as aluminum is implanted into the opening of the oxide film to form a lower first p ⁺ -type base region 4a having a depth of about 0.5 μm. A second p ⁺ -type base region 5 that forms the bottom of the trench 18 may be formed at the same time as the lower first p ⁺ -type base region 4a. The distance between adjacent lower first p ⁺ -type base region 4a and second p ⁺ -type base region 5 is formed to be 0.5 μm or more and 0.9 μm or less. As a result, the depletion layer S does not close at a drain voltage of about 1 V during normal operation of the silicon carbide semiconductor device, and the depletion layer S closes when the drain voltage is higher than the voltage during normal operation and equal to or lower than the gate voltage. The impurity concentration of the lower first p ⁺ -type base region 4a and the second p ⁺ -type base region 5 is set to about 5×10 ¹⁸ /cm ³ , for example. The state up to this point is shown in FIG.

Next, part of the ion implantation mask is removed, and an n-type impurity such as nitrogen is ion-implanted into the opening to form a part of the surface region of the first n ⁻ -type silicon carbide epitaxial layer 2a, for example, with a depth of 0. A lower n-type high-concentration region 6a having a thickness of about 0.5 μm is provided. The impurity concentration of the lower n-type high concentration region 6a is set to about 1×10 ¹⁷ /cm ³ , for example.

Next, a second n ^- -type silicon carbide epitaxial layer 2b doped with an n-type impurity such as nitrogen is formed on the surface of the first n ^- -type silicon carbide epitaxial layer 2a to a thickness of about 0.5 μm. The impurity concentration of second n ⁻ -type silicon carbide epitaxial layer 2b is set to about 3×10 ¹⁵ /cm ³ . Thereafter, the n ^{− -type silicon carbide epitaxial layer 2 is formed by combining the first n − -type} silicon carbide epitaxial layer 2a and the second n ⁻ -type silicon carbide epitaxial layer 2b.

Next, an ion implantation mask having a predetermined opening is formed of, for example, an oxide film on the surface of the second n ⁻ -type silicon carbide epitaxial layer 2b by photolithography. Then, a p-type impurity such as aluminum is implanted into the opening of the oxide film to form an upper first p ⁺ -type base region 4b having a depth of about 0.5 μm so as to overlap the lower first p ⁺ -type base region 4a. do. The lower first p ⁺ -type base region 4 a and the upper first p ⁺ -type base region 4 b form a continuous region to become the first p ⁺ -type base region 4 . The impurity concentration of the upper first p ⁺ -type base region 4b is set to about 5×10 ¹⁸ /cm ³ , for example.

Next, a portion of the ion implantation mask is removed, and an n-type impurity such as nitrogen is ion-implanted into the opening to implant a portion of the surface region of the second silicon carbide epitaxial layer 2b to a depth of, for example, 0.5 μm. An upper n-type high-concentration region 6b is provided. The impurity concentration of the upper n-type high concentration region 6b is set to about 1×10 ¹⁷ /cm ³ , for example. The upper n-type high concentration region 6b and the lower n-type high concentration region 6a are formed so as to be in contact with each other at least partially to form the n-type high concentration region 6. As shown in FIG. However, this n-type high-concentration region 6 may or may not be formed over the entire surface of the substrate. The state up to this point is shown in FIG.

Next, on the surface of n ⁻ -type silicon carbide epitaxial layer 2, p ⁻ -type silicon carbide epitaxial layer 3 doped with a p-type impurity such as aluminum is formed to a thickness of about 1.3 μm. The impurity concentration of p ⁻ -type silicon carbide epitaxial layer 3 is set to about 4×10 ¹⁷ /cm ³ . The state up to this point is shown in FIG.

Next, an ion implantation mask having a predetermined opening is formed of, for example, an oxide film on the surfaces of p ⁻ -type silicon carbide epitaxial layer 3 and exposed n ⁻ -type silicon carbide epitaxial layer 1 by photolithography. An n-type impurity such as phosphorus (P) is ion-implanted into this opening to form n ⁺ -type source region 7 in a portion of the surface of p ⁻ -type silicon carbide epitaxial layer 3 . The impurity concentration of n ⁺ -type source region 7 is set to be higher than that of p ⁻ -type silicon carbide epitaxial layer 3 . Next, the ion implantation mask used for forming the n ^{+ -type} source region 7 is removed, and an ion implantation mask having a predetermined opening is formed by the same method. A p-type impurity such as aluminum is ion-implanted into a part of the surface to form a p ⁺ -type contact region 8 . The impurity concentration of p ⁺ -type contact region 8 is set to be higher than that of p ⁻ -type silicon carbide epitaxial layer 3 . The state up to this point is shown in FIG.

Next, heat treatment (annealing) is performed in an inert gas atmosphere at about 1700° C. to activate the first p ⁺ -type base region 4, the second p ⁺ -type base region 5, the n ⁺ -type source region 7, and the p ⁺ -type contact region 8. Transformation processing is carried out. As described above, the ion-implanted regions may be activated collectively by one heat treatment, or may be activated by heat treatment each time ion implantation is performed.

Next, on the surface of p ⁻ -type silicon carbide epitaxial layer 3, a trench forming mask having a predetermined opening is formed of, for example, an oxide film by photolithography. Next, trenches 18 are formed through p ⁻ type silicon carbide epitaxial layer 3 and reaching n ⁻ type silicon carbide epitaxial layer 2 by dry etching. The bottom of trench 18 may reach first p ⁺ -type base region 4 formed in n ⁻ -type silicon carbide epitaxial layer 2 . Next, the trench formation mask is removed. The state up to this point is shown in FIG.

Next, gate insulating film 9 is formed along the surfaces of n ⁺ -type source region 7 and p ⁺ -type contact region 8 and along the bottom and side walls of trench 18 . This gate insulating film 9 may be formed by thermal oxidation by heat treatment at a temperature of about 1000° C. in an oxygen atmosphere. Also, the gate insulating film 9 may be formed by a method of depositing by a chemical reaction such as high temperature oxide (HTO).

Next, a polycrystalline silicon layer doped with, for example, phosphorus atoms is provided on the gate insulating film 9 . This polycrystalline silicon layer may be formed so as to fill the trench 18 . The gate electrode 10 is formed by patterning this polycrystalline silicon layer by photolithography and leaving it inside the trench 18 .

Next, an interlayer insulating film 11 is formed by depositing, for example, phosphorous glass to a thickness of about 1 μm so as to cover the gate insulating film 9 and the gate electrode 10 . Next, a barrier metal (not shown) made of titanium (Ti) or titanium nitride (TiN) may be formed to cover the interlayer insulating film 11 . Interlayer insulating film 11 and gate insulating film 9 are patterned by photolithography to form contact holes exposing n ⁺ -type source region 7 and p ⁺ -type contact region 8 . Thereafter, heat treatment (reflow) is performed to planarize the interlayer insulating film 11 . The state up to this point is shown in FIG.

Next, a conductive film made of nickel (Ni) or the like that becomes the source electrode 12 is provided in the contact hole and on the interlayer insulating film 11 . This conductive film is patterned by photolithography to leave the source electrode 12 only in the contact hole.

Next, on the second main surface of n ⁺ -type silicon carbide semiconductor substrate 1, back surface electrode 14 of nickel or the like is provided. Thereafter, heat treatment is performed in an inert gas atmosphere at about 1000° C. to form n ⁺ -type source region 7 , p ⁺ -type contact region 8 , n ⁺ -type silicon carbide semiconductor substrate 1 and source electrode 12 in ohmic contact with the back surface electrode. Form.

Next, an aluminum film having a thickness of about 5 μm is deposited on the first main surface of n ⁺ silicon carbide semiconductor substrate 1 by sputtering, and aluminum is deposited by photolithography so as to cover source electrode 12 and interlayer insulating film 11 . It is removed to form a source electrode pad (not shown).

Next, a drain electrode pad (not shown) is formed on the surface of the back electrode 14 by laminating titanium (Ti), nickel and gold (Au) in order, for example. As described above, the silicon carbide semiconductor device shown in FIG. 1 is completed.

As described above, according to the silicon carbide semiconductor device of the first embodiment, the width between the first p ⁺ -type base region and the second p ⁺ -type base region is narrower than that of the conventional silicon carbide semiconductor device. there is As a result, the depletion layer closes when the drain voltage is higher than the voltage during normal operation and lower than the gate voltage, and the drain current saturates at a lower drain voltage than conventional, resulting in a low saturation current. Therefore, even if the on-resistance is reduced by reducing the channel resistance, the saturation current does not increase as much as in the conventional case, and the short-circuit withstand capability is less likely to decrease.

(Embodiment 2)
Next, the structure of the silicon carbide semiconductor device according to the second embodiment is described. FIG. 13 is a cross-sectional view showing the structure of the silicon carbide semiconductor device according to the second embodiment. The silicon carbide semiconductor device according to the second embodiment differs from the silicon carbide semiconductor device according to the first embodiment in that the first p ⁺ -type base region 4 and the second p ⁺ -type base region 5 extend in the width direction of the trench 18 . It is a point that it has the projection part 13 which existed.

The resistance of n-type high-concentration region 6 is determined by JFET width L1 and thickness L2 of second p ⁺ -type base region 5 . On the other hand, the JFET pinch-off voltage is determined by the JFET width L1. Therefore, in the second embodiment, the projecting portion 13 provides a narrow portion of the JFET width L1. As in the first embodiment, the JFET width L1 between the protrusions 13 is such that the depletion layer S does not close at a drain voltage of about 1 V during normal operation in the silicon carbide semiconductor device, and the drain voltage is lower than the voltage during normal operation. The width is such that the depletion layer S closes when it is high and lower than the gate voltage. As a result, the drain current saturates at a drain voltage lower than that of the prior art, and the saturation current can be reduced.

Further, in the second embodiment, the resistance of the n-type high-concentration region 6 is lower than that in the first embodiment due to the portions of the first p ⁺ -type base region 4 and the second p ⁺ -type base region 5 where the protrusions 13 are not provided. can be lowered.

(Method for Manufacturing Semiconductor Device According to Second Embodiment)
Next, a method for manufacturing the silicon carbide semiconductor device according to the second embodiment will be described. 14 to 16 are cross-sectional views showing states in the process of manufacturing the silicon carbide semiconductor device according to the second embodiment. First, as in the first embodiment, n ⁺ -type silicon carbide substrate 1 is prepared, and second p ⁺ -type base region 5 and lower first p ⁺ -type base region 4a are formed on the surface layer of lower second p ⁺ -type base region 5a. are sequentially performed (see FIGS. 6 and 7). At this time, the distance between second p ⁺ -type base region 5 and lower second p ⁺ -type base region 4a is approximately the same as that of the conventional silicon carbide semiconductor device, for example, approximately 1.5 μm.

Next, using the oxide film 19 used for selectively forming the second p ⁺ -type base region 5 and the lower first p ⁺ -type base region 4a, a p-type impurity such as aluminum is removed from the opening of the oxide film 19. Inject into the part. At this time, the dose is set higher than the dose for selectively forming the second p ⁺ -type base region 5 and the lower second p ⁺ -type base region 4a so that the p-type impurity such as aluminum spreads laterally. to form the protrusion 13 . The state up to this point is shown in FIG.

At this time, the distance between the protrusions 13 is formed to be 0.5 μm or more and 0.9 μm or less. As a result, the depletion layer S does not close at a drain voltage of about 1 V during normal operation of the silicon carbide semiconductor device, and the depletion layer S closes when the drain voltage is higher than the voltage during normal operation and lower than the gate voltage.

Thereafter, steps after the step of providing upper n-type high concentration region 6b are sequentially performed (see FIGS. 8 to 12) in the same manner as in the first embodiment, thereby completing the silicon carbide semiconductor device shown in FIG.

Moreover, the silicon carbide semiconductor device according to the second embodiment can also be manufactured by the following method. First, as in the first embodiment, n ⁺ -type silicon carbide substrate 1 is prepared and the steps up to formation of first n ^- -type silicon carbide epitaxial layer 2a are sequentially performed (see FIG. 6).

Next, an ion implantation mask having a predetermined opening is formed of an oxide film 19, for example, on the surface of the first n ⁻ -type silicon carbide epitaxial layer 2a by photolithography. Then, a p-type impurity such as aluminum is implanted into the opening of the oxide film to form a lower first p ⁺ -type base region 4a1 and a lower second p ⁺ -type base region 5a that serves as the bottom of the trench . At this time, the distance between lower first p ⁺ -type base region 4a1 and lower second p ⁺ -type base region 5a is approximately the same as in a conventional silicon carbide semiconductor device, for example, approximately 1.5 μm. The state up to this point is shown in FIG.

Next, the ion implantation mask is removed, and a third n ⁻ -type silicon carbide epitaxial layer 2c doped with an n-type impurity such as nitrogen is formed on the surface of the first n ⁻ -type silicon carbide epitaxial layer 2a to a thickness of about 0.1 μm. Form in thickness. The impurity concentration of third n ⁻ -type silicon carbide epitaxial layer 2c is set to about 3×10 ¹⁵ /cm ³ .

Next, on the surface of the third n ^- -type silicon carbide epitaxial layer 2c, an ion implantation mask having a predetermined opening is formed of, for example, an oxide film 19' by photolithography. The oxide film 19 ′ forms a wider opening than the oxide film 19 . Then, a p-type impurity such as aluminum is implanted into the opening of the oxide film 19' to form the lower second first p ⁺ -type base region 4a2 and the upper second p ⁺ -type base region 5b. At this time, the distance between the lower second first p ⁺ -type base region 4a2 and the upper second p ⁺ -type base region 5b is set to 0.5 μm or more and 0.9 μm or less. The state up to this point is shown in FIG.

Thereafter, steps after the step of providing upper n-type high concentration region 6b are sequentially performed (see FIGS. 8 to 12) in the same manner as in the first embodiment, thereby completing the silicon carbide semiconductor device shown in FIG.

As described above, according to the second embodiment, the first p ⁺ -type base region and the second p ⁺ -type base region have protrusions. As a result, the saturation current is low as in the first embodiment, and even if the on-resistance is reduced by reducing the channel resistance, the saturation current does not rise as much as in the conventional case, and the reduction in short-circuit resistance is reduced. . Moreover, in the second embodiment, the resistance of the n-type high concentration region can be lowered by the portions of the first p ⁺ -type base region and the second p ⁺ -type base region where the protrusion is not provided.

(Embodiment 3)
Next, the structure of the silicon carbide semiconductor device according to the third embodiment will be described. FIG. 17 is a cross-sectional view showing the structure of the silicon carbide semiconductor device according to the third embodiment. The silicon carbide semiconductor device according to the third embodiment differs from the silicon ^carbide semiconductor device according ^to the first embodiment in that a first p The difference is that a third p ⁺ -type base region (second conductivity type fourth semiconductor region) 15 protruding toward the ⁺ -type base region 4 side is provided.

Distance L3 between first p ⁺ -type base region 4 and third p ⁺ -type base region 15 is similar to the first embodiment, and depletion layer S is formed at a drain voltage of about 1 V during normal operation of the silicon carbide semiconductor device. The width is such that the depletion layer S is closed when the drain voltage is higher than the voltage during normal operation and lower than the gate voltage. As a result, the drain current saturates at a drain voltage lower than that of the prior art, and the saturation current can be reduced.

Also, the distance between the first p ⁺ -type base region 4 and the second p ⁺ -type base region 5 is the same as in the conventional structure. Therefore, in the third embodiment, the resistance of the n-type high concentration region 6 can be made lower than in the first embodiment.

(Method for Manufacturing Semiconductor Device According to Third Embodiment)
Next, a method for manufacturing the silicon carbide semiconductor device according to the third embodiment will be described. FIG. 18 is a cross-sectional view showing a state in the middle of manufacturing the silicon carbide semiconductor device according to the third embodiment. First, as in the first embodiment, n ⁺ -type silicon carbide substrate 1 is prepared, and second p ⁺ -type base region 5 and lower first p ⁺ -type base region 4a are formed on the surface layer of lower second p ⁺ -type base region 5a. are sequentially performed (see FIGS. 6 and 7). At this time, the distance between second p ⁺ -type base region 5 and lower second p ⁺ -type base region 4a is approximately the same as that of the conventional silicon carbide semiconductor device, for example, approximately 1.5 μm.

Next, the ion implantation mask is removed, and a third n ⁻ -type silicon carbide epitaxial layer 2c doped with an n-type impurity such as nitrogen is formed on the surface of the first n ⁻ -type silicon carbide epitaxial layer 2a to a thickness of about 0.1 μm. Form in thickness. The impurity concentration of third n ⁻ -type silicon carbide epitaxial layer 2c is set to about 3×10 ¹⁵ /cm ³ .

Next, on the surface of the third n ⁻ -type silicon carbide epitaxial layer 2c, an ion implantation mask having a predetermined opening is formed by photolithography, for example, with an oxide film 19″. The oxide film 19″ is the third p ⁺ Portions corresponding to the type base region 15 and the lower second p ⁺ -type base region 4a are opened. Then, a p-type impurity such as aluminum is implanted into the opening of the oxide film 19″ to form the third p ⁺ -type base region 15. At this time, the third p ⁺ -type base region 15 and the second p ⁺ -type base region are formed. The distance from 4a is formed to be 0.5 μm or more and 0.9 μm or less.The state up to this point is shown in FIG.

Thereafter, steps after the step of providing upper n-type high concentration region 6b are sequentially performed (see FIGS. 8 to 12) in the same manner as in the first embodiment, thereby completing the silicon carbide semiconductor device shown in FIG.

FIG. 19 is a graph showing the relationship between drain voltage and drain current in the silicon carbide semiconductor devices according to the first, second and third embodiments. In FIG. 19, the horizontal axis indicates the drain voltage, and the vertical axis indicates the drain current. Line A shows the relationship between drain voltage and drain current in a conventional silicon carbide semiconductor device for comparison, and line C shows the drain voltage when the JFET width L1 of the first embodiment is applied and the channel resistance is reduced. and the drain current, and the line D is the relationship between the drain voltage and the drain current in the second and third embodiments.

As shown in FIG. 19, in the conventional line A, the drain current is saturated at the pinch-off voltage, whereas in the lines C and D, the drain current is saturated at the JFET pinch-off voltage lower than the pinch-off voltage. , the saturation voltage is lower. Line D makes the resistance of the n-type high-concentration region 6 lower than that in the first embodiment, but does not reduce the channel resistance. ing.

As described above, according to the third embodiment, the third p ⁺ -type base region protruding toward the first p ⁺ -type base region is provided on the surface of the second p ⁺ -type base region. As a result, the saturation current is low as in the first embodiment, and even if the on-resistance is reduced by reducing the channel resistance, the saturation current does not rise as much as in the conventional case, and the reduction in short-circuit resistance is reduced. . Further, in the third embodiment, the distance between the first p ⁺ -type base region and the second p ⁺ -type base region is the same distance as in the conventional structure, so the resistance of the n-type high concentration region is lower than that in the first embodiment. can be lowered.

As described above, the present invention can be modified in various ways without departing from the gist of the present invention. Further, in each of the above-described embodiments, the MOSFET is described as an example, but the present invention is not limited to this, and various silicon carbide that conducts and interrupts current by being gate-driven and controlled based on a predetermined gate threshold voltage. It is also widely applicable to semiconductor devices. Silicon carbide semiconductor devices that are gate-driven and controlled include, for example, IGBTs (Insulated Gate Bipolar Transistors). Further, in each of the above-described embodiments, the case where silicon carbide is used as a wide bandgap semiconductor is described as an example, but it is also applicable to wide bandgap semiconductors other than silicon carbide, such as gallium nitride (GaN). is. In each embodiment, the first conductivity type is n-type and the second conductivity type is p-type. It holds.

INDUSTRIAL APPLICABILITY As described above, the semiconductor device and the method for manufacturing a semiconductor device according to the present invention are useful for power semiconductor devices used in power converters and power supply devices for various industrial machines. Suitable for semiconductor devices.

1, 101 n ⁺ type silicon carbide substrate 2, 102 n ⁻ type silicon carbide epitaxial layer 2a 1st n ⁻ type silicon carbide epitaxial layer 2b 2nd n ⁻ type silicon carbide epitaxial layer 2c 3rd n ⁻ type silicon carbide epitaxial layer 3, 103 p ⁻ type silicon carbide epitaxial layer 4, 104 first p ⁺ type base region 4a lower first p ⁺ type base region 4a1 lower first p ⁺ type base region 4a2 lower second first p ⁺ type base region 4b upper first p ⁺ type base region 5 , 105 second p ⁺ -type base region 5a lower second p ⁺ -type base region 5b upper second p ⁺ -type base region 6, 106 n-type high concentration region 6a lower n-type high concentration region 6b upper n-type high concentration region 7, 107 n ⁺ type source regions 8, 108 p ⁺ type contact regions 9, 109 gate insulating films 10, 110 gate electrodes 11, 111 interlayer insulating films 12, 112 source electrode 13 protrusion 14 rear surface electrode 15 third p ⁺ type base regions 18, 118 trenches 19, 19', 19'' oxide films 100, 200 silicon carbide semiconductor substrate

Claims (5)

a first conductivity type semiconductor substrate;
a first semiconductor layer of a first conductivity type provided on the front surface of the semiconductor substrate and having an impurity concentration lower than that of the semiconductor substrate;
a second conductivity type second semiconductor layer provided on the side opposite to the semiconductor substrate side of the first semiconductor layer;
a first semiconductor region of a first conductivity type having an impurity concentration higher than that of the semiconductor substrate, the first semiconductor region being selectively provided inside the second semiconductor layer;
a trench penetrating through the first semiconductor region and the second semiconductor layer and reaching the first semiconductor layer;
a gate electrode provided inside the trench via a gate insulating film;
a second conductivity type second semiconductor region selectively provided inside the first semiconductor layer;
a third semiconductor region of a second conductivity type selectively provided inside the first semiconductor layer and in contact with the bottom surface of the trench;
a first electrode provided on the surface of the second semiconductor layer and the first semiconductor region;
a second electrode provided on the back surface of the semiconductor substrate;
with
the second semiconductor region and the third semiconductor region have protrusions extending in the width direction of the trench;
the protrusion is provided closer to the first electrode than the bottom surface of the trench;
When the voltage of the second electrode is the operating voltage, the distance between the protrusions is a first depletion layer between the second semiconductor region and the first semiconductor layer, and a distance between the third semiconductor region and the third semiconductor region. When the second depletion layer between one semiconductor layer is not closed and the voltage of the second electrode is higher than the operating voltage and lower than the voltage of the gate electrode, the first depletion layer and the second depletion layer is the distance at which A semiconductor device characterized by: a first conductivity type semiconductor substrate;
a first semiconductor layer of a first conductivity type provided on the front surface of the semiconductor substrate and having an impurity concentration lower than that of the semiconductor substrate;
a second conductivity type second semiconductor layer provided on the side opposite to the semiconductor substrate side of the first semiconductor layer;
a first semiconductor region of a first conductivity type having an impurity concentration higher than that of the semiconductor substrate, the first semiconductor region being selectively provided inside the second semiconductor layer;
a trench penetrating through the first semiconductor region and the second semiconductor layer and reaching the first semiconductor layer;
a gate electrode provided inside the trench via a gate insulating film;
a second conductivity type second semiconductor region selectively provided inside the first semiconductor layer;
a third semiconductor region of a second conductivity type selectively provided inside the first semiconductor layer and in contact with the bottom surface of the trench;
a first electrode provided on the surface of the second semiconductor layer and the first semiconductor region;
a second electrode provided on the back surface of the semiconductor substrate;
a second conductivity type fourth semiconductor region protruding toward the second semiconductor region from a surface of the third semiconductor region on the second semiconductor layer side;
with
the fourth semiconductor region is provided closer to the first electrode than the bottom surface of the trench;
a distance between the fourth semiconductor region and the second semiconductor region is a first depletion layer between the second semiconductor region and the first semiconductor layer when the voltage of the second electrode is an operating voltage; When the second depletion layer between the third semiconductor region and the first semiconductor layer does not close and the voltage of the second electrode is higher than the operating voltage and lower than the voltage of the gate electrode, the first depletion A semiconductor device, wherein the distance between the layer and the second depletion layer is close. 3. The semiconductor device according to claim 1, wherein said distance is 0.5 [mu]m or more and 0.9 [mu]m or less. a first step of forming, on a front surface of a semiconductor substrate of a first conductivity type, a first semiconductor layer of a first conductivity type having an impurity concentration lower than that of the semiconductor substrate;
a second step of forming a second semiconductor layer of a second conductivity type on the side of the first semiconductor layer opposite to the semiconductor substrate;
a third step of selectively forming a first semiconductor region of a first conductivity type having an impurity concentration higher than that of the semiconductor substrate inside the second semiconductor layer;
a fourth step of forming a trench penetrating the first semiconductor region and the second semiconductor layer and reaching the first semiconductor layer;
a fifth step of forming a gate electrode inside the trench via a gate insulating film;
a sixth step of selectively forming a second semiconductor region of a second conductivity type inside the first semiconductor layer;
a seventh step of selectively forming a third semiconductor region of a second conductivity type in contact with the bottom surface of the trench inside the first semiconductor layer;
an eighth step of forming a first electrode on the surface of the second semiconductor layer and the first semiconductor region;
a ninth step of forming a second electrode on the back surface of the semiconductor substrate;
a tenth step of forming protrusions extending in the width direction of the trenches in the second semiconductor region and the third semiconductor region;
including
the protrusion is formed closer to the first electrode than the bottom surface of the trench;
When the voltage of the second electrode is the operating voltage, the distance between the protrusions is a first depletion layer between the second semiconductor region and the first semiconductor layer, and a distance between the third semiconductor region and the third semiconductor region. When the second depletion layer between one semiconductor layer is not closed and the voltage of the second electrode is higher than the operating voltage and lower than the voltage of the gate electrode, the first depletion layer and the second depletion layer is a close distance. a first step of forming, on a front surface of a semiconductor substrate of a first conductivity type, a first semiconductor layer of a first conductivity type having an impurity concentration lower than that of the semiconductor substrate;
a second step of forming a second semiconductor layer of a second conductivity type on the side of the first semiconductor layer opposite to the semiconductor substrate;
a third step of selectively forming a first semiconductor region of a first conductivity type having an impurity concentration higher than that of the semiconductor substrate inside the second semiconductor layer;
a fourth step of forming a trench penetrating the first semiconductor region and the second semiconductor layer and reaching the first semiconductor layer;
a fifth step of forming a gate electrode inside the trench via a gate insulating film;
a sixth step of selectively forming a second semiconductor region of a second conductivity type inside the first semiconductor layer;
a seventh step of selectively forming a third semiconductor region of a second conductivity type in contact with the bottom surface of the trench inside the first semiconductor layer;
an eighth step of forming a first electrode on the surface of the second semiconductor layer and the first semiconductor region;
a ninth step of forming a second electrode on the back surface of the semiconductor substrate;
a tenth step of forming a fourth semiconductor region of the second conductivity type protruding toward the second semiconductor region on the surface of the third semiconductor region on the second semiconductor layer side;
including
the fourth semiconductor region is formed closer to the first electrode than the bottom surface of the trench;
a distance between the fourth semiconductor region and the second semiconductor region is a first depletion layer between the second semiconductor region and the first semiconductor layer when the voltage of the second electrode is an operating voltage; When the second depletion layer between the third semiconductor region and the first semiconductor layer does not close and the voltage of the second electrode is higher than the operating voltage and lower than the voltage of the gate electrode, the first depletion A method of manufacturing a semiconductor device, wherein the distance between the layer and the second depletion layer is close.

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