CN117673163A - Super-junction MOSFET with high short-circuit tolerance, preparation method thereof and chip - Google Patents
Super-junction MOSFET with high short-circuit tolerance, preparation method thereof and chip Download PDFInfo
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- 238000002360 preparation method Methods 0.000 title claims abstract description 10
- 210000000746 body region Anatomy 0.000 claims abstract description 44
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 claims abstract description 30
- 229910010271 silicon carbide Inorganic materials 0.000 claims abstract description 29
- 239000000758 substrate Substances 0.000 claims abstract description 24
- 150000002500 ions Chemical class 0.000 claims description 27
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 16
- 229920005591 polysilicon Polymers 0.000 claims description 12
- 239000003989 dielectric material Substances 0.000 claims description 9
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical group O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 7
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 7
- 238000005530 etching Methods 0.000 claims description 3
- 230000000149 penetrating effect Effects 0.000 claims description 2
- 239000000463 material Substances 0.000 description 8
- 230000009286 beneficial effect Effects 0.000 description 7
- 239000002019 doping agent Substances 0.000 description 6
- 238000000034 method Methods 0.000 description 6
- 238000010586 diagram Methods 0.000 description 5
- 239000004065 semiconductor Substances 0.000 description 5
- 230000015556 catabolic process Effects 0.000 description 4
- 238000002513 implantation Methods 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 4
- 230000005684 electric field Effects 0.000 description 3
- 229920006395 saturated elastomer Polymers 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000000779 depleting effect Effects 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
Abstract
The utility model belongs to the technical field of power devices, a super junction MOSFET with high short circuit tolerance and a preparation method thereof are provided, a chip is provided, an N-type drift region with a concave structure is formed on the front surface of a silicon carbide substrate, a P-type doped region is formed at the bottom of a groove of the N-type drift region and on the inner wall of the groove, an insulating medium layer is formed in the groove of the P-type doped region, a first P-type shielding region and a second P-type shielding region are formed on two sides of the insulating medium layer and are contacted with the P-type doped region, a JFET region is formed between the P-type shielding region and a P-type body region, and the first P-type shielding region and the second P-type shielding region extend to the JFET region, so that the current path in the device is reduced, saturation current is reduced, the purpose of improving short circuit tolerance is achieved, the N-type drift region is assisted to be depleted by the P-type doped region, and the on resistance of the device is reduced.
Description
Technical Field
The application belongs to the technical field of power devices, and particularly relates to a super-junction MOSFET with high short-circuit tolerance, a preparation method thereof and a chip.
Background
Silicon carbide (SiC) is also one of the most widely used wide bandgap semiconductor materials at the current level of crystal production technology and device fabrication as a representative of third generation semiconductor materials. Currently, siC has formed a global industry chain of materials, devices and applications. SiC Metal-Oxide-semiconductor field-EffectTransistor, MOSFET (SiC MOSFET) belongs to a novel power semiconductor device, and because the SiC material has a high breakdown electric field and a high saturation drift velocity, the SiC MOSFET has high breakdown voltage and high-frequency characteristics.
However, the current conventional super junction MOSFET device has a problem of high short-circuit tolerance.
Disclosure of Invention
In order to solve the technical problems, the embodiment of the application provides a super-junction MOSFET with high short-circuit tolerance, a preparation method thereof and a chip, which can solve the problem of high short-circuit tolerance of the existing super-junction MOSFET device.
A first aspect of the embodiments of the present application provides a high short-circuit-tolerance superjunction MOSFET, the high short-circuit-tolerance superjunction MOSFET including:
a silicon carbide substrate and a drain layer formed on the back surface of the silicon carbide substrate;
the N-type drift region is formed on the front surface of the silicon carbide substrate, wherein the N-type drift region is of a concave structure;
the P-type doped region is formed at the bottom of the groove of the N-type drift region and the inner wall of the groove, and is of a U-shaped structure;
the insulating medium layer is formed in the groove of the P-type doped region;
the first P type shielding region and the second P type shielding region are respectively formed on two sides of the insulating medium layer and are in contact with the P type doping region;
the grid electrode dielectric layer and the grid electrode polycrystalline silicon layer are formed on the insulating dielectric layer, and the grid electrode dielectric layer wraps the grid electrode polycrystalline silicon layer;
the first P-type base region and the second P-type base region are formed on two sides of the grid dielectric layer;
the first N-type source region and the second N-type source region are formed on two sides of the grid dielectric layer, wherein the first N-type source region is formed on the first P-type base region, and the second N-type source region is formed on the second P-type base region;
the first P type body region and the second P type body region are formed on the N type drift region, the first P type body region is in contact with the first P type base region, and the second P type body region is in contact with the second P type base region;
and the source electrode layer is formed on the first N-type source region, the second N-type source region, the first P-type body region and the second P-type body region.
In some embodiments, the insulating dielectric layer is made of a high-K dielectric material.
In some embodiments, the insulating dielectric layer is silicon oxide.
In some embodiments, the first P-type shielding region is in contact with the gate dielectric layer, the insulating dielectric layer, and extends into the N-type drift region; the second P-type shielding region is in contact with the gate dielectric layer and the insulating dielectric layer and extends into the N-type drift region.
In some embodiments, the width of the first P-type shielding region is greater than the width of the side part of the P-type doped region, and is opposite to the first P-type base region, and an N-type drift region is arranged between the first P-type shielding region and the first P-type base region;
and/or
The width of the second P-type shielding region is larger than that of the side part of the P-type doping region, the second P-type shielding region is opposite to the second P-type base region, and an N-type drift region is arranged between the second P-type shielding region and the second P-type base region.
In some embodiments, the width of the first P-type shielding region is smaller than the width of the first P-type base region; and the width of the second P type shielding region is smaller than that of the second P type base region.
In some embodiments, the first P-type shielding region and the second P-type shielding region are symmetrically arranged with the insulating medium layer as a central axis.
In some embodiments, the doping concentration of the first and second P-type shield regions is greater than the doping concentration of the P-type doped region.
The second aspect of the embodiment of the present application further provides a method for preparing a super junction MOSFET with high short-circuit tolerance, where the method for preparing the super junction MOSFET with high short-circuit tolerance includes:
epitaxially growing a drift layer on the front surface of the silicon carbide substrate, sequentially injecting N-type doping ions and P-type doping ions to form an N-type drift region and a P-type shielding layer, and then continuing to epitaxially grow the drift layer and injecting the N-type doping ions to form an N-type drift region wrapping the P-type shielding layer;
p-type doped ions and N-type doped ions are sequentially injected into the N-type drift region to form a P-type base layer, an N-type source layer, a first P-type body region and a second P-type body region; the first P-type body region and the second P-type body region are positioned on two sides of the P-type base layer;
etching the N-type source layer to form a first deep groove penetrating into the N-type drift region so as to divide the P-type shielding layer into a first P-type shielding region and a second P-type shielding region, divide the P-type base layer into a first P-type base region and a second P-type base region, and divide the N-type source layer into a first N-type source region and a second N-type source region;
forming a P-type doped region at the bottom and the side wall of the first deep groove; the P-type doped region is of a U-shaped structure, and two ends of the P-type doped region are respectively contacted with the first P-type shielding region and the second P-type shielding region;
forming an insulating dielectric layer in the groove of the P-type doped region, and forming a gate dielectric layer and a gate polysilicon layer on the insulating dielectric layer; wherein the gate dielectric layer wraps the gate polysilicon layer;
and forming a source layer on the first N-type source region and the second N-type source region, and forming a drain layer on the back surface of the silicon carbide substrate.
A third aspect of the embodiments of the present application further provides a chip comprising a high short tolerance superjunction MOSFET according to any of the embodiments described above; or include a high short tolerance superjunction MOSFET prepared by the preparation method described in the above examples.
The beneficial effects of the embodiment of the application are that: an N-type drift region with a concave structure is formed on the front surface of a silicon carbide substrate, a P-type doped region is formed at the bottom of a groove of the N-type drift region and on the inner wall of the groove, an insulating medium layer is formed in the groove of the P-type doped region, a first P-type shielding region and a second P-type shielding region which are contacted with the P-type doped region are formed on two sides of the insulating medium layer, a JFET region is formed between the P-type shielding region and a P-type body region, the first P-type shielding region and the second P-type shielding region extend to the JFET region, current paths in a device are reduced, saturated current is reduced, the purpose of improving short circuit tolerance is achieved, the N-type drift region is assisted to be exhausted through the P-type doped region, so that the doping concentration of the N-type drift region is properly improved, and the on-resistance of the device is reduced.
Drawings
Fig. 1 is a schematic structural diagram of a super junction MOSFET with high short-circuit tolerance according to an embodiment of the present application;
fig. 2 is a schematic flow chart of a method for preparing a super junction MOSFET with high short-circuit tolerance according to an embodiment of the present application;
fig. 3 is a schematic diagram of an N-type drift region and a P-type shielding layer after forming according to an embodiment of the present application;
FIG. 4 is a schematic diagram of a P-type base layer, an N-type source layer, a first P-type body region and a second P-type body region according to an embodiment of the present application;
FIG. 5 is a schematic view of a first deep trench formed according to an embodiment of the present application;
FIG. 6 is a schematic diagram of a P-doped region formed according to an embodiment of the present application;
fig. 7 is a schematic diagram of an embodiment of the present application after forming an insulating dielectric layer, a gate dielectric layer, and a gate polysilicon layer.
Detailed Description
In order to make the technical problems, technical schemes and beneficial effects to be solved by the present application more clear, the present application is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the present application.
In order to solve the above technical problem, an embodiment of the present application provides a super-junction MOSFET with high short-circuit tolerance, as shown in fig. 1, where the super-junction MOSFET with high short-circuit tolerance in the embodiment includes: the silicon carbide substrate 100, the drain electrode layer 110, the N-type drift region 200, the P-type doped region 210, the insulating dielectric layer 220, the first P-type shielding region 310, the second P-type shielding region 320, the gate dielectric layer 420, the gate polysilicon layer 430, the first P-type base region 441, the second P-type base region 442, the first N-type source region 451, the second N-type source region 452, the first P-type body region 411, the second P-type body region 412 and the source electrode layer 120, the drain electrode layer 110 is formed on the back surface of the silicon carbide substrate 100, the N-type drift region 200 is formed on the front surface of the silicon carbide substrate 100, wherein the N-type drift region 200 has a concave structure. The P-type doped region 210 is formed at the bottom and the inner wall of the groove of the N-type drift region 200, and the P-type doped region 210 has a U-shaped structure. An insulating dielectric layer 220 is formed in the recess of the P-type doped region 210. The first P-type shielding region 310 and the second P-type shielding region 320 are respectively formed on two sides of the insulating dielectric layer 220 and are in contact with the P-type doped region 210. The gate dielectric layer 420 and the gate polysilicon layer 430 are formed on the insulating dielectric layer 220, and the gate dielectric layer 420 wraps the gate polysilicon layer 430; the first P-type base region 441 and the second P-type base region 442 are formed on two sides of the gate dielectric layer 420. The first N-type source region 451 and the second N-type source region 452 are formed on two sides of the gate dielectric layer 420, wherein the first N-type source region 451 is formed on the first P-type base region 441, and the second N-type source region 452 is formed on the second P-type base region 442. The first P-type body region 411 and the second P-type body region 412 are formed on the N-type drift region 200, and the first P-type body region 411 is in contact with the first P-type base region 441, and the second P-type body region 412 is in contact with the second P-type base region 442; the source layer 120 is formed on the first N-type source region 451, the second N-type source region 452, the first P-type body region 411, and the second P-type body region 412.
In this embodiment, an N-type drift region 200 with a concave structure is formed on the front surface of a silicon carbide substrate 100, a P-type doped region 210 is formed at the bottom of a groove and on the inner wall of the groove of the N-type drift region 200, an insulating dielectric layer 220 is formed in the groove of the P-type doped region 210, and a first P-type shielding region 310 and a second P-type shielding region 320 are formed on two sides of the insulating dielectric layer 220 and are in contact with the P-type doped region 210, so that a JFET region is formed between the P-type shielding region and the P-type body region, and the first P-type shielding region 310 and the second P-type shielding region 320 extend to the JFET region, which is beneficial to reducing the current path in the device, reducing the saturation current, achieving the purpose of improving the short-circuit tolerance, and the P-type doped region 210 is assisted to be depleted by the P-type doped region 210, thereby properly improving the doping concentration of the N-type drift region 200 and reducing the on-resistance of the device.
In some embodiments, insulating dielectric layer 220 is made of a high-K dielectric material.
In this embodiment, the dielectric constant of the high-K dielectric material is greater than that of silicon carbide, which is beneficial for the insulating dielectric layer 220 to absorb the electric field lines and improve the breakdown voltage of the device.
In some embodiments, insulating dielectric layer 220 is silicon oxide.
In this embodiment, the gate-drain capacitance of the device can be advantageously reduced by forming the insulating dielectric layer 220 using a silicon oxide material having a dielectric constant less than that of silicon carbide.
In some embodiments, the first P-type shield region 310 is in contact with the gate dielectric layer 420, the insulating dielectric layer 220, and extends into the N-type drift region 200; the second P-type shield region 320 is in contact with the gate dielectric layer 420, the insulating dielectric layer 220, and extends into the N-type drift region 200.
In this embodiment, a PN junction is formed between the first P-type shielding region 310 and the N-type drift region 200, a PN junction is formed between the first P-type body region 411 and the N-type drift region 200, the first P-type shielding region 310, the first P-type body region 411, and the N-type drift region 200 can form a JFET region, a PN junction is formed between the second P-type shielding region 320 and the N-type drift region 200, a PN junction is formed between the second P-type body region 412 and the N-type drift region 200, and the second P-type shielding region 320, the second P-type body region 412, and the N-type drift region 200 can form a JFET region, which is beneficial to reducing the current path in the device, reducing the saturation current, achieving the purpose of improving the short-circuit tolerance, and the P-type doping region 210 is used up to properly increase the doping concentration of the N-type drift region 200, and reduce the on-resistance of the device.
In some embodiments, the width of the first P-type shielding region 310 is greater than the width of the side portion of the P-type doped region 210, and opposite to the first P-type base region 441, an N-type drift region 200 is disposed between the first P-type shielding region 310 and the first P-type base region 441.
In some embodiments, the width of the second P-type shielding region 320 is greater than the width of the side portion of the P-type doped region 210, and opposite to the second P-type base region 442, an N-type drift region 200 is disposed between the second P-type shielding region 320 and the second P-type base region 442.
In some embodiments, the width of the first P-type shielding region 310 is smaller than the width of the first P-type base region 441; the width of the second P-type shielding region 320 is smaller than the width of the second P-type base region 442.
In some embodiments, the first P-type shielding region 310 and the second P-type shielding region 320 are symmetrically disposed with the insulating dielectric layer 220 as a central axis.
In some embodiments, the doping concentration of the first P-type shielding region 310 and the second P-type shielding region 320 is greater than the doping concentration of the P-type doped region 210.
In order to solve the above technical problems, the embodiments of the present application further provide a method for manufacturing a super junction MOSFET with high short-circuit tolerance, as shown in fig. 2, the method for manufacturing a super junction MOSFET with high short-circuit tolerance includes steps S100 to S600.
In step S100, a drift layer is epitaxially grown on the front surface of the silicon carbide substrate 100, and N-type doping ions and P-type doping ions are sequentially implanted to form an N-type drift region 200 and a P-type shield layer 300, and then the drift layer is epitaxially grown and N-type doping ions are implanted to form an N-type drift region 200 surrounding the P-type shield layer 300.
In this embodiment, as shown in fig. 3, a silicon carbide material is epitaxially grown on the front surface of the silicon carbide substrate 100 to form a drift layer, N-type doping ions are implanted to form an N-type drift region 200, P-type doping ions are implanted in the central region of the N-type drift region 200 to form a P-type shielding layer 300, and finally the drift layer is epitaxially grown and N-type doping ions are implanted to form an N-type drift region 200 surrounding the P-type shielding layer 300.
In some embodiments, the thickness of the N-type drift region 200 above the P-type shield layer 300 is less than the thickness of the N-type drift region 200 below the P-type shield layer 300.
In step S200, P-type dopant ions and N-type dopant ions are sequentially implanted on the N-type drift region 200 to form a P-type base layer 440, an N-type source layer 450, a first P-type body region 411, and a second P-type body region 412.
In this embodiment, as shown in fig. 4, P-type doped ions are implanted on the N-type drift region 200 to form a P-type base layer 440, and N-type doped ions are implanted on the P-type base layer 440 to form an N-type source layer 450, wherein the implantation energy of the N-type doped ions into the P-type base layer 440 is smaller than the implantation energy of the P-type doped ions into the N-type drift region 200 to form the P-type base layer 440. P-type dopant ions are implanted at both sides of the N-type source layer 450, and the implantation energy of the P-type dopant ions is equal to the implantation energy of the P-type dopant ions implanted on the N-type drift region 200 to form the P-type base layer 440, and the first P-type body region 411 and the second P-type body region 412 are located at both sides of the P-type base layer 440.
In step S300, a first deep trench 201 is etched on the N-type source layer 450 to the N-type drift region 200 to divide the P-type shielding layer 300 into a first P-type shielding region 310 and a second P-type shielding region 320, the P-type base layer 440 into a first P-type base region 441 and a second P-type base region 442, and the N-type source layer 450 into a first N-type source region 451 and a second N-type source region 452.
In this embodiment, referring to fig. 5, the first deep trench 201 is formed by etching in the central region of the N-type source layer 450, the first deep trench 201 extends under the P-type shielding layer 300, the P-type shielding layer 300 is divided into a first P-type shielding region 310 and a second P-type shielding region 320, the P-type base layer 440 is divided into a first P-type base region 441 and a second P-type base region 442, and the N-type source layer 450 is divided into a first N-type source region 451 and a second N-type source region 452.
In step S400, a P-type doped region 210 is formed at the bottom and the sidewall of the first deep trench 201; the P-doped region 210 has a U-shaped structure, and two ends of the P-doped region 210 are respectively contacted with the first P-type shielding region 310 and the second P-type shielding region 320.
In this embodiment, as shown in fig. 6, P-type doped ions are implanted into the bottom and the sidewall of the first deep trench 201 by an ion implantation process to form a U-shaped P-type doped region 210.
In some embodiments, P-type dopant ions may be repeatedly implanted at a corner position between the bottom and the sidewall of the first deep trench 201, so that the doping concentration at the corner position is greater than the doping concentration at other positions of the P-type doped region 210, which may help to assist in depleting the N-type drift region 200 and reduce the on-resistance of the device.
In step S500, an insulating dielectric layer 220 is formed in the recess of the P-type doped region 210, and a gate dielectric layer 420 and a gate polysilicon layer 430 are formed on the insulating dielectric layer 220.
In this embodiment, referring to fig. 7, an insulating dielectric material is filled in the groove of the P-type doped region 210 to form an insulating dielectric layer 220, the insulating dielectric layer 220 is in contact with the first P-type shielding region 310 and the second P-type shielding region 320, then a gate dielectric material is deposited on the bottom and the sidewall of the groove on the insulating dielectric layer 220 to form a concave gate dielectric layer 420, and after the gate polysilicon material is filled, the gate dielectric material is deposited again to form the gate dielectric layer 420 including a gate polysilicon layer 430.
In step S600, as shown in fig. 1, a source layer 120 is formed on the first N-type source region 451 and the second N-type source region 452, and a drain layer 110 is formed on the back surface of the silicon carbide substrate 100.
In this embodiment, the source layer 120 further covers the gate dielectric layer 420 and contacts the first P-type body region 411 and the second P-type body region 412.
In some embodiments, insulating dielectric layer 220 is made of a high-K dielectric material.
In this embodiment, the dielectric constant of the high-K dielectric material is greater than that of silicon carbide, which is beneficial for the insulating dielectric layer 220 to absorb the electric field lines and improve the breakdown voltage of the device.
In some embodiments, insulating dielectric layer 220 is silicon oxide.
In this embodiment, the gate-drain capacitance of the device can be advantageously reduced by forming the insulating dielectric layer 220 using a silicon oxide material having a dielectric constant less than that of silicon carbide.
In some embodiments, the gate dielectric layer 420 may be silicon oxide or silicon nitride, and the gate polysilicon layer 430 is connected to an external gate electrode through a via on the gate dielectric layer 420.
The embodiment of the application also provides a chip, which comprises the super junction MOSFET with high short circuit tolerance according to any one of the embodiments.
The embodiment of the application also provides a chip, which comprises the super-junction MOSFET with high short-circuit tolerance prepared by the preparation method of any one of the embodiments.
In this embodiment, the chip includes a chip substrate, and one or more superjunction MOSFETs with high short-circuit tolerance are disposed on the chip substrate, where the superjunction MOSFETs with high short-circuit tolerance may be prepared by the preparation method in any of the foregoing embodiments, or the superjunction MOSFETs with high short-circuit tolerance in any of the foregoing embodiments may be disposed on the chip substrate.
In one embodiment, other related semiconductor devices can be integrated on the chip substrate to form an integrated circuit with the super junction MOSFET with high short circuit tolerance.
In one specific application embodiment, the chip may be a switching chip or a driving chip.
The beneficial effects of the embodiment of the application are that: an N-type drift region with a concave structure is formed on the front surface of a silicon carbide substrate, a P-type doped region is formed at the bottom of a groove of the N-type drift region and on the inner wall of the groove, an insulating medium layer is formed in the groove of the P-type doped region, a first P-type shielding region and a second P-type shielding region which are contacted with the P-type doped region are formed on two sides of the insulating medium layer, a JFET region is formed between the P-type shielding region and a P-type body region, the first P-type shielding region and the second P-type shielding region extend to the JFET region, current paths in a device are reduced, saturated current is reduced, the purpose of improving short circuit tolerance is achieved, the N-type drift region is assisted to be exhausted through the P-type doped region, so that the doping concentration of the N-type drift region is properly improved, and the on-resistance of the device is reduced.
It will be apparent to those skilled in the art that, for convenience and brevity of description, only the above-described division of each doped region and device is illustrated, and in practical application, the above-described function allocation may be performed by different doped regions and devices according to needs, i.e. the internal structure of the device is divided into different doped regions, so as to perform all or part of the above-described functions. The doped regions and the devices in the embodiments can be integrated in one unit, or each unit can exist alone physically, or two or more units can be integrated in one unit.
In addition, the specific names of the doped regions and the devices are only used for distinguishing the doped regions and the devices from each other, and are not used for limiting the protection scope of the application.
In the foregoing embodiments, the descriptions of the embodiments are emphasized, and in part, not described or illustrated in any particular embodiment, reference is made to the related descriptions of other embodiments.
In addition, each doped region in each embodiment of the present application may be integrated in one unit, or each unit may exist alone physically, or two or more units may be integrated in one unit.
The above embodiments are only for illustrating the technical solution of the present application, and are not limiting thereof; although the present application has been described in detail with reference to the foregoing embodiments, it should be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit and scope of the technical solutions of the embodiments of the present application, and are intended to be included in the scope of the present application.
Claims (10)
1. A high short tolerance superjunction MOSFET, the high short tolerance superjunction MOSFET comprising:
a silicon carbide substrate and a drain layer formed on the back surface of the silicon carbide substrate;
the N-type drift region is formed on the front surface of the silicon carbide substrate, wherein the N-type drift region is of a concave structure;
the P-type doped region is formed at the bottom of the groove of the N-type drift region and the inner wall of the groove, and is of a U-shaped structure;
the insulating medium layer is formed in the groove of the P-type doped region;
the first P type shielding region and the second P type shielding region are respectively formed on two sides of the insulating medium layer and are in contact with the P type doping region;
the grid electrode dielectric layer and the grid electrode polycrystalline silicon layer are formed on the insulating dielectric layer, and the grid electrode dielectric layer wraps the grid electrode polycrystalline silicon layer;
the first P-type base region and the second P-type base region are formed on two sides of the grid dielectric layer;
the first N-type source region and the second N-type source region are formed on two sides of the grid dielectric layer, wherein the first N-type source region is formed on the first P-type base region, and the second N-type source region is formed on the second P-type base region;
the first P type body region and the second P type body region are formed on the N type drift region, the first P type body region is in contact with the first P type base region, and the second P type body region is in contact with the second P type base region;
and the source electrode layer is formed on the first N-type source region, the second N-type source region, the first P-type body region and the second P-type body region.
2. The high short tolerance superjunction MOSFET of claim 1, wherein said insulating dielectric layer is made of a high K dielectric material.
3. The high short tolerance superjunction MOSFET of claim 1, wherein said insulating dielectric layer is silicon oxide.
4. The high short tolerance superjunction MOSFET of claim 1, wherein said first P-type shield region is in contact with said gate dielectric layer, said insulating dielectric layer, and extends into said N-type drift region; the second P-type shielding region is in contact with the gate dielectric layer and the insulating dielectric layer and extends into the N-type drift region.
5. The high short tolerance superjunction MOSFET of claim 1, wherein the first P-type shield region has a width greater than the width of the sides of the P-type doped region and opposite the first P-type base region, an N-type drift region being disposed between the first P-type shield region and the first P-type base region;
and/or
The width of the second P-type shielding region is larger than that of the side part of the P-type doping region, the second P-type shielding region is opposite to the second P-type base region, and an N-type drift region is arranged between the second P-type shielding region and the second P-type base region.
6. The high short tolerance superjunction MOSFET of claim 1, wherein said first P-type shield region has a width less than a width of said first P-type base region; and the width of the second P type shielding region is smaller than that of the second P type base region.
7. The high short tolerance superjunction MOSFET of claim 1, wherein said first P-type shield region and said second P-type shield region are symmetrically disposed about said dielectric layer.
8. The high short tolerance superjunction MOSFET of any of claims 1-6, wherein the doping concentration of the first P-type shield region and the second P-type shield region is greater than the doping concentration of the P-type doped region.
9. The preparation method of the super-junction MOSFET with high short-circuit tolerance is characterized by comprising the following steps of:
epitaxially growing a drift layer on the front surface of the silicon carbide substrate, sequentially injecting N-type doping ions and P-type doping ions to form an N-type drift region and a P-type shielding layer, and then continuing to epitaxially grow the drift layer and injecting the N-type doping ions to form an N-type drift region wrapping the P-type shielding layer;
p-type doped ions and N-type doped ions are sequentially injected into the N-type drift region to form a P-type base layer, an N-type source layer, a first P-type body region and a second P-type body region; the first P-type body region and the second P-type body region are positioned on two sides of the P-type base layer;
etching the N-type source layer to form a first deep groove penetrating into the N-type drift region so as to divide the P-type shielding layer into a first P-type shielding region and a second P-type shielding region, divide the P-type base layer into a first P-type base region and a second P-type base region, and divide the N-type source layer into a first N-type source region and a second N-type source region;
forming a P-type doped region at the bottom and the side wall of the first deep groove; the P-type doped region is of a U-shaped structure, and two ends of the P-type doped region are respectively contacted with the first P-type shielding region and the second P-type shielding region;
forming an insulating dielectric layer in the groove of the P-type doped region, and forming a gate dielectric layer and a gate polysilicon layer on the insulating dielectric layer; wherein the gate dielectric layer wraps the gate polysilicon layer;
and forming a source layer on the first N-type source region and the second N-type source region, and forming a drain layer on the back surface of the silicon carbide substrate.
10. A chip comprising the high short tolerance superjunction MOSFET of any of claims 1-8; or a superjunction MOSFET comprising a high short-circuit tolerance prepared by the preparation method of claim 9.
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