CN117673164A - Shielded gate super-junction MOSFET (Metal-oxide-semiconductor field Effect transistor) and preparation method and chip thereof - Google Patents
Shielded gate super-junction MOSFET (Metal-oxide-semiconductor field Effect transistor) and preparation method and chip thereof Download PDFInfo
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- 238000002360 preparation method Methods 0.000 title claims abstract description 11
- 239000004065 semiconductor Substances 0.000 title description 7
- 230000005669 field effect Effects 0.000 title description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 95
- 210000000746 body region Anatomy 0.000 claims abstract description 45
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 claims abstract description 26
- 229910010271 silicon carbide Inorganic materials 0.000 claims abstract description 25
- 239000000758 substrate Substances 0.000 claims abstract description 24
- 229920005591 polysilicon Polymers 0.000 claims description 77
- 150000002500 ions Chemical class 0.000 claims description 25
- 239000000463 material Substances 0.000 claims description 11
- 238000005530 etching Methods 0.000 claims description 3
- 230000000149 penetrating effect Effects 0.000 claims description 2
- 239000002019 doping agent Substances 0.000 description 5
- 238000004519 manufacturing process Methods 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- 238000002513 implantation Methods 0.000 description 4
- 230000009286 beneficial effect Effects 0.000 description 3
- 230000005684 electric field Effects 0.000 description 3
- 238000000034 method Methods 0.000 description 3
- 230000015556 catabolic process Effects 0.000 description 2
- 238000009826 distribution Methods 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 238000009751 slip forming Methods 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
Abstract
The utility model belongs to the technical field of power devices, a shielding grid super junction MOSFET and a preparation method thereof, a chip are provided, an N-type drift region with a concave structure is formed on the front surface of a silicon carbide substrate, a shielding grid polycrystalline silicon layer and a grid polycrystalline silicon layer are formed in a groove of the N-type drift region, the grid polycrystalline silicon layer is positioned above the shielding grid polycrystalline silicon layer, a grid dielectric layer wraps the shielding grid polycrystalline silicon layer and the grid polycrystalline silicon layer respectively, a first P-type shielding region and a second P-type shielding region are formed on two sides of the grid dielectric layer, a JFET region is formed between the P-type shielding region and the P-type body region, and the first P-type shielding region and the second P-type shielding region extend to the JFET region, so that a current path in the device is reduced, saturation current is reduced, and the purpose of improving short circuit tolerance is achieved.
Description
Technical Field
The application belongs to the technical field of power devices, and particularly relates to a shielded gate superjunction MOSFET, a preparation method thereof and a chip.
Background
Silicon carbide (SiC) is also one of the most widely used wide bandgap semiconductor materials at the current level of crystal production technology and device fabrication as a representative of third generation semiconductor materials. Currently, siC has formed a global industry chain of materials, devices and applications. SiC Metal-Oxide-semiconductor field-EffectTransistor, MOSFET (SiC MOSFET) belongs to a novel power semiconductor device, and because the SiC material has a high breakdown electric field and a high saturation drift velocity, the SiC MOSFET has high breakdown voltage and high-frequency characteristics.
However, the current conventional super junction MOSFET device has a problem of high short-circuit tolerance.
Disclosure of Invention
In order to solve the technical problems, the embodiment of the application provides a shielded gate super-junction MOSFET, a preparation method thereof and a chip, which can solve the problem of high short-circuit tolerance of the existing super-junction MOSFET device.
A first aspect of the embodiments of the present application provides a shielded gate superjunction MOSFET, including:
a silicon carbide substrate and a drain layer formed on the back surface of the silicon carbide substrate;
the N-type drift region is formed on the front surface of the silicon carbide substrate, wherein the N-type drift region is of a concave structure;
the grid dielectric layer is formed at the bottom of the groove of the N-type drift region and on the inner wall of the groove;
the shielding gate polysilicon layer and the grid polysilicon layer are formed in the grid dielectric layer, the grid polysilicon layer is positioned above the shielding gate polysilicon layer, and the grid dielectric layer wraps the shielding gate polysilicon layer and the grid polysilicon layer respectively;
the first P type shielding region and the second P type shielding region are formed on two sides of the grid dielectric layer, and extend to the N type drift region;
the first P-type base region and the second P-type base region are formed on two sides of the grid polycrystalline silicon layer;
the first N-type source region and the second N-type source region are formed on two sides of the grid dielectric layer, wherein the first N-type source region is formed on the first P-type base region, and the second N-type source region is formed on the second P-type base region;
the first P type body region and the second P type body region are formed on the N type drift region, the first P type body region is in contact with the first P type base region, and the second P type body region is in contact with the second P type base region;
the source electrode layer is formed on the first N-type source region, the second N-type source region, the first P-type body region and the second P-type body region, and is connected with the shielding gate polysilicon layer.
In some embodiments, the first P-type shield region and the second P-type shield region are respectively positioned at two sides of the gate dielectric layer between the shield gate polysilicon layer and the gate polysilicon layer.
In some embodiments, the first P-type shielding region has a width smaller than a width of the first P-type base region.
In some embodiments, the second P-type shielding region has a width smaller than a width of the second P-type base region.
In some embodiments, the first and second P-type shield regions are in contact with the gate dielectric layer, and the first and second P-type shield regions are disposed horizontally.
In some embodiments, the width of the shield gate polysilicon layer is less than the width of the gate polysilicon layer.
In some embodiments, the first P-type shielding region and the second P-type shielding region are symmetrically arranged with the shielding gate polysilicon layer as a central axis.
In some embodiments, the doping concentration of the first P-type shielding region and the second P-type shielding region is greater than the doping concentration of the first P-type base region and the second P-type base region.
The second aspect of the embodiment of the application also provides a preparation method of the shielded gate superjunction MOSFET, which comprises the following steps:
epitaxially growing a drift layer on the front surface of the silicon carbide substrate, sequentially injecting N-type doping ions and P-type doping ions to form an N-type drift region and a P-type shielding layer, and then continuing to epitaxially grow the drift layer and injecting the N-type doping ions to form an N-type drift region wrapping the P-type shielding layer;
p-type doped ions and N-type doped ions are sequentially injected into the N-type drift region to form a P-type base layer, an N-type source layer, a first P-type body region and a second P-type body region; the first P-type body region and the second P-type body region are positioned on two sides of the P-type base layer;
etching the N-type source layer to form a first deep groove penetrating into the N-type drift region so as to divide the P-type shielding layer into a first P-type shielding region and a second P-type shielding region, divide the P-type base layer into a first P-type base region and a second P-type base region, and divide the N-type source layer into a first N-type source region and a second N-type source region;
forming a gate dielectric layer at the bottom and the side wall of the first deep groove, filling a polysilicon material to form a shielding gate polysilicon layer, and then filling the polysilicon material to form the gate polysilicon layer after continuing to form the gate dielectric layer; the grid electrode polycrystalline silicon layer is positioned above the shielding grid polycrystalline silicon layer, and the grid electrode dielectric layer wraps the shielding grid polycrystalline silicon layer and the grid electrode polycrystalline silicon layer respectively;
forming a source layer on the first N-type source region and the second N-type source region, and forming a drain layer on the back surface of the silicon carbide substrate; the source electrode layer is connected with the shielding gate polycrystalline silicon layer.
The third aspect of the embodiment of the present application further provides a chip, including a shielded gate superjunction MOSFET according to any one of the embodiments above; or includes a shielded gate superjunction MOSFET prepared by the preparation method described in the above examples.
The beneficial effects of the embodiment of the application are that: an N-type drift region with a concave structure is formed on the front surface of the silicon carbide substrate, a shielding gate polysilicon layer and a grid polysilicon layer are formed in a groove of the N-type drift region, the grid polysilicon layer is located above the shielding gate polysilicon layer, a grid dielectric layer wraps the shielding gate polysilicon layer and the grid polysilicon layer respectively, a first P-type shielding region and a second P-type shielding region are formed on two sides of the grid dielectric layer, a JFET region is formed between the P-type shielding region and the P-type body region, the first P-type shielding region and the second P-type shielding region extend to the JFET region, current paths in a device are reduced, saturation current is reduced, the purpose of improving short circuit tolerance is achieved, the N-type drift region is assisted to be exhausted through a P-type doping region, accordingly doping concentration of the N-type drift region is properly improved, and on-resistance of the device is reduced.
Drawings
Fig. 1 is a schematic structural diagram of a shielded gate superjunction MOSFET according to an embodiment of the present disclosure;
fig. 2 is a schematic flow chart of a method for manufacturing a shielded gate superjunction MOSFET according to an embodiment of the present application;
fig. 3 is a schematic diagram of an N-type drift region and a P-type shielding layer after forming according to an embodiment of the present application;
FIG. 4 is a schematic diagram of a P-type base layer, an N-type source layer, a first P-type body region and a second P-type body region according to an embodiment of the present application;
FIG. 5 is a schematic view of a first deep trench formed according to an embodiment of the present application;
fig. 6 is a schematic diagram of a mask gate polysilicon layer, a gate dielectric layer, and a gate polysilicon layer after forming according to an embodiment of the present application.
Detailed Description
In order to make the technical problems, technical schemes and beneficial effects to be solved by the present application more clear, the present application is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the present application.
In order to solve the above technical problem, an embodiment of the present application provides a shielded gate superjunction MOSFET, as shown in fig. 1, where the shielded gate superjunction MOSFET in the embodiment includes: the silicon carbide substrate 100, the drain electrode layer 110, the N-type drift region 200, the shielding gate polysilicon layer 220, the first P-type shielding region 310, the second P-type shielding region 320, the gate dielectric layer 420, the gate polysilicon layer 430, the first P-type base region 441, the second P-type base region 442, the first N-type source region 451, the second N-type source region 452, the first P-type body region 411, the second P-type body region 412, and the source electrode layer 120, the drain electrode layer 110 is formed on the back surface of the silicon carbide substrate 100, the N-type drift region 200 is formed on the front surface of the silicon carbide substrate 100, wherein the N-type drift region 200 has a concave structure. The shielding gate polysilicon layer 220 and the gate polysilicon layer 430 are formed in the grooves of the N-type drift region 200, the gate dielectric layer 420 wraps the shielding gate polysilicon layer 220 and the gate polysilicon layer 430, the gate polysilicon layer 430 is formed on the shielding gate polysilicon layer 220, and the shielding gate polysilicon layer 220 and the gate polysilicon layer 430 are isolated by the gate dielectric layer 420. The shield gate polysilicon layer 220 is connected to the source layer 120. The first P-type shielding region 310 and the second P-type shielding region 320 are respectively formed at two sides of the gate dielectric layer 420. The first P-type base region 441 and the second P-type base region 442 are formed on two sides of the gate dielectric layer 420. The first N-type source region 451 and the second N-type source region 452 are formed on two sides of the gate dielectric layer 420, wherein the first N-type source region 451 is formed on the first P-type base region 441, and the second N-type source region 452 is formed on the second P-type base region 442. The first P-type body region 411 and the second P-type body region 412 are formed on the N-type drift region 200, and the first P-type body region 411 is in contact with the first P-type base region 441, and the second P-type body region 412 is in contact with the second P-type base region 442; the source layer 120 is formed on the first N-type source region 451, the second N-type source region 452, the first P-type body region 411, and the second P-type body region 412.
In this embodiment, an N-type drift region 200 with a concave structure is formed on the front surface of the silicon carbide substrate 100, a groove of the N-type drift region 200 is formed with a shielding gate polysilicon layer 220 and a gate polysilicon layer 430, the shielding gate polysilicon layer 220 is connected with the source layer 120, so that the electric field distribution at the bottom of the N-type drift region can be optimized, the N-type drift region 200 is assisted to be depleted, the effect of reducing the on-resistance of the device is achieved, and a JFET region is formed between the P-type shielding region and the P-type body region by forming a first P-type shielding region 310 and a second P-type shielding region 320 on both sides of the gate dielectric layer 420 and contacting the gate dielectric layer 420, and the JFET region is extended from the first P-type shielding region 310 and the second P-type shielding region 320, so that the current path in the device is reduced, the saturation current is reduced, and the purpose of improving the short circuit tolerance is achieved.
In some embodiments, the first and second P-type shield regions 310, 320 are located on either side of the gate dielectric layer 420 between the shield gate polysilicon layer 220 and the gate polysilicon layer 430, respectively.
In this embodiment, the first P-type shielding region 310 is disposed opposite to the first P-type base region 441, and the first P-type shielding region 310 and the first P-type base region 441 are provided with the N-type drift region 200. The second P-type shielding region 320 is disposed opposite to the second P-type base region 442, and an N-type drift region 200 is disposed between the second P-type shielding region 320 and the second P-type base region 442.
In some embodiments, the first P-type shielding region 310 is disposed parallel to the first P-type base region 441, and the width of the first P-type shielding region 310 is smaller than the width of the first P-type base region 441.
In some embodiments, the second P-type shielding region 320 is disposed parallel to the second P-type base region 442, and the width of the second P-type shielding region 320 is smaller than the width of the second P-type base region 442.
In some embodiments, the first P-type shielding region 310 and the second P-type shielding region 320 are in contact with the gate dielectric layer 420, and the first P-type shielding region 310 and the second P-type shielding region 320 are disposed horizontally.
In some embodiments, the first P-type shield region 310 is in contact with the gate dielectric layer 420 and extends into the N-type drift region 200; the second P-type shield region 320 is in contact with the gate dielectric layer 420 and extends into the N-type drift region 200.
In this embodiment, a PN junction is formed between the first P-type shielding region 310 and the N-type drift region 200, a PN junction is formed between the first P-type body region 411 and the N-type drift region 200, the first P-type shielding region 310, the first P-type body region 411, and the N-type drift region 200 can form a JFET region, a PN junction is formed between the second P-type shielding region 320 and the N-type drift region 200, a PN junction is formed between the second P-type body region 412 and the N-type drift region 200, and the second P-type shielding region 320, the second P-type body region 412, and the N-type drift region 200 can form a JFET region, and the first P-type shielding region 310 and the second P-type shielding region 320 extend to the JFET region, which is advantageous for reducing a current path in the device, reducing a saturation current, and achieving the purpose of improving a short-circuit resistance.
In some embodiments, the first P-type shielding region 310 and the second P-type shielding region 320 are symmetrically disposed about the shielding gate polysilicon layer 220 as a central axis.
In some embodiments, the doping concentration of the first P-type shielding region 310 and the second P-type shielding region 320 is greater than the doping concentration of the first P-type base region 441 and the second P-type base region 442.
In some embodiments, the width of the shield gate polysilicon layer 220 is less than the width of the gate polysilicon layer 430.
In order to solve the above technical problems, the embodiment of the present application further provides a method for manufacturing a shielded gate superjunction MOSFET, as shown in fig. 2, where the method for manufacturing a shielded gate superjunction MOSFET includes steps S100 to S500.
In step S100, a drift layer is epitaxially grown on the front surface of the silicon carbide substrate 100, and N-type doping ions and P-type doping ions are sequentially implanted to form an N-type drift region 200 and a P-type shield layer 300, and then the drift layer is epitaxially grown and N-type doping ions are implanted to form an N-type drift region 200 surrounding the P-type shield layer 300.
In this embodiment, as shown in fig. 3, a silicon carbide material is epitaxially grown on the front surface of the silicon carbide substrate 100 to form a drift layer, N-type doping ions are implanted to form an N-type drift region 200, P-type doping ions are implanted in the central region of the N-type drift region 200 to form a P-type shielding layer 300, and finally the drift layer is epitaxially grown and N-type doping ions are implanted to form an N-type drift region 200 surrounding the P-type shielding layer 300.
In some embodiments, the thickness of the N-type drift region 200 above the P-type shield layer 300 is less than the thickness of the N-type drift region 200 below the P-type shield layer 300.
In step S200, P-type dopant ions and N-type dopant ions are sequentially implanted on the N-type drift region 200 to form a P-type base layer 440, an N-type source layer 450, a first P-type body region 411, and a second P-type body region 412.
In this embodiment, as shown in fig. 4, P-type doped ions are implanted on the N-type drift region 200 to form a P-type base layer 440, and N-type doped ions are implanted on the P-type base layer 440 to form an N-type source layer 450, wherein the implantation energy of the N-type doped ions into the P-type base layer 440 is smaller than the implantation energy of the P-type doped ions into the N-type drift region 200 to form the P-type base layer 440. P-type dopant ions are implanted at both sides of the N-type source layer 450, and the implantation energy of the P-type dopant ions is equal to the implantation energy of the P-type dopant ions implanted on the N-type drift region 200 to form the P-type base layer 440, and the first P-type body region 411 and the second P-type body region 412 are located at both sides of the P-type base layer 440.
In step S300, a first deep trench 201 is etched on the N-type source layer 450 to the N-type drift region 200 to divide the P-type shielding layer 300 into a first P-type shielding region 310 and a second P-type shielding region 320, the P-type base layer 440 into a first P-type base region 441 and a second P-type base region 442, and the N-type source layer 450 into a first N-type source region 451 and a second N-type source region 452.
In this embodiment, referring to fig. 5, the first deep trench 201 is formed by etching in the central region of the N-type source layer 450, the first deep trench 201 extends under the P-type shielding layer 300, the P-type shielding layer 300 is divided into a first P-type shielding region 310 and a second P-type shielding region 320, the P-type base layer 440 is divided into a first P-type base region 441 and a second P-type base region 442, and the N-type source layer 450 is divided into a first N-type source region 451 and a second N-type source region 452.
In step S400, a gate dielectric layer 420 is formed at the bottom and the sidewalls of the first deep trench 201, and a shielding gate polysilicon layer 220 is formed by filling a polysilicon material, and then a gate dielectric layer 420 is continuously formed and then a gate polysilicon layer 430 is formed by filling a polysilicon material.
In this embodiment, the gate dielectric layer 420 wraps the shielding gate polysilicon layer 220 and the gate polysilicon layer 430, the gate polysilicon layer 430 is formed on the shielding gate polysilicon layer 220, and the shielding gate polysilicon layer 220 and the gate polysilicon layer 430 are isolated by the gate dielectric layer 420.
In step S500, as shown in fig. 1, a source layer 120 is formed on the first N-type source region 451 and the second N-type source region 452, and a drain layer 110 is formed on the back surface of the silicon carbide substrate 100.
In this embodiment, the source layer 120 further covers the gate dielectric layer 420 and contacts the first P-type body region 411 and the second P-type body region 412. The shielding gate polysilicon layer 220 is connected with the source layer 120, so that the electric field distribution at the bottom of the N-type drift region can be optimized, the N-type drift region 200 is assisted to be depleted, the on-resistance of the device is reduced, and the JFET region is formed between the P-type shielding region and the P-type body region by forming the first P-type shielding region 310 and the second P-type shielding region 320 which are in contact with the gate dielectric layer 420 at two sides of the gate dielectric layer 420, and the current path in the device is reduced, the saturation current is reduced, and the short-circuit tolerance is improved.
In some embodiments, the gate dielectric layer 420 may be silicon oxide or silicon nitride, and the gate polysilicon layer 430 is connected to an external gate electrode through a via on the gate dielectric layer 420.
The embodiment of the application also provides a chip, which comprises the shielded gate superjunction MOSFET according to any one of the embodiments.
The embodiment of the application also provides a chip, which comprises the shielded gate super junction MOSFET prepared by the preparation method of any one of the embodiments.
In this embodiment, the chip includes a chip substrate, and one or more shielded gate superjunction MOSFETs are disposed on the chip substrate, where the shielded gate superjunction MOSFETs may be prepared by the preparation method in any of the foregoing embodiments, or the shielded gate superjunction MOSFETs in any of the foregoing embodiments may be disposed on the chip substrate.
In one embodiment, other related semiconductor devices can be integrated on the chip substrate to form an integrated circuit with the shielded gate superjunction MOSFET.
In one specific application embodiment, the chip may be a switching chip or a driving chip.
The beneficial effects of the embodiment of the application are that: an N-type drift region with a concave structure is formed on the front surface of the silicon carbide substrate, a shielding gate polysilicon layer and a grid polysilicon layer are formed in a groove of the N-type drift region, the grid polysilicon layer is located above the shielding gate polysilicon layer, a grid dielectric layer wraps the shielding gate polysilicon layer and the grid polysilicon layer respectively, a first P-type shielding region and a second P-type shielding region are formed on two sides of the grid dielectric layer, a JFET region is formed between the P-type shielding region and the P-type body region, the first P-type shielding region and the second P-type shielding region extend to the JFET region, current paths in a device are reduced, saturation current is reduced, the purpose of improving short circuit tolerance is achieved, the N-type drift region is assisted to be exhausted through a P-type doping region, accordingly doping concentration of the N-type drift region is properly improved, and on-resistance of the device is reduced.
It will be apparent to those skilled in the art that, for convenience and brevity of description, only the above-described division of each doped region and device is illustrated, and in practical application, the above-described function allocation may be performed by different doped regions and devices according to needs, i.e. the internal structure of the device is divided into different doped regions, so as to perform all or part of the above-described functions. The doped regions and the devices in the embodiments can be integrated in one unit, or each unit can exist alone physically, or two or more units can be integrated in one unit.
In addition, the specific names of the doped regions and the devices are only used for distinguishing the doped regions and the devices from each other, and are not used for limiting the protection scope of the application.
In the foregoing embodiments, the descriptions of the embodiments are emphasized, and in part, not described or illustrated in any particular embodiment, reference is made to the related descriptions of other embodiments.
In addition, each doped region in each embodiment of the present application may be integrated in one unit, or each unit may exist alone physically, or two or more units may be integrated in one unit.
The above embodiments are only for illustrating the technical solution of the present application, and are not limiting thereof; although the present application has been described in detail with reference to the foregoing embodiments, it should be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit and scope of the technical solutions of the embodiments of the present application, and are intended to be included in the scope of the present application.
Claims (10)
1. A shielded gate superjunction MOSFET, the shielded gate superjunction MOSFET comprising:
a silicon carbide substrate and a drain layer formed on the back surface of the silicon carbide substrate;
the N-type drift region is formed on the front surface of the silicon carbide substrate, wherein the N-type drift region is of a concave structure;
the grid dielectric layer is formed at the bottom of the groove of the N-type drift region and on the inner wall of the groove;
the shielding gate polysilicon layer and the grid polysilicon layer are formed in the grid dielectric layer, the grid polysilicon layer is positioned above the shielding gate polysilicon layer, and the grid dielectric layer wraps the shielding gate polysilicon layer and the grid polysilicon layer respectively;
the first P type shielding region and the second P type shielding region are formed on two sides of the grid dielectric layer, and extend to the N type drift region;
the first P-type base region and the second P-type base region are formed on two sides of the grid polycrystalline silicon layer;
the first N-type source region and the second N-type source region are formed on two sides of the grid dielectric layer, wherein the first N-type source region is formed on the first P-type base region, and the second N-type source region is formed on the second P-type base region;
the first P type body region and the second P type body region are formed on the N type drift region, the first P type body region is in contact with the first P type base region, and the second P type body region is in contact with the second P type base region;
the source electrode layer is formed on the first N-type source region, the second N-type source region, the first P-type body region and the second P-type body region, and is connected with the shielding gate polysilicon layer.
2. The shielded gate superjunction MOSFET of claim 1, wherein the first P-type shield region and the second P-type shield region are each located on either side of a gate dielectric layer between the shield gate polysilicon layer and the gate polysilicon layer.
3. The shielded gate superjunction MOSFET of claim 1, wherein the width of the first P-type shield region is less than the width of the first P-type base region.
4. The shielded gate superjunction MOSFET of claim 1, wherein a width of said second P-type shield region is less than a width of said second P-type base region.
5. The shielded gate superjunction MOSFET of claim 1, wherein said first P-type shielded region and said second P-type shielded region are in contact with said gate dielectric layer, and wherein said first P-type shielded region and said second P-type shielded region are disposed horizontally.
6. The shielded gate superjunction MOSFET of claim 1, wherein a width of the shielded gate polysilicon layer is less than a width of the gate polysilicon layer.
7. The shielded gate superjunction MOSFET of claim 1, wherein said first P-type shield region and said second P-type shield region are symmetrically disposed about said shielded gate polysilicon layer.
8. The shielded gate superjunction MOSFET of any of claims 1-6, wherein the first and second P-type shield regions have a doping concentration greater than the doping concentration of the first and second P-type base regions.
9. The preparation method of the shielded gate super junction MOSFET is characterized by comprising the following steps of:
epitaxially growing a drift layer on the front surface of the silicon carbide substrate, sequentially injecting N-type doping ions and P-type doping ions to form an N-type drift region and a P-type shielding layer, and then continuing to epitaxially grow the drift layer and injecting the N-type doping ions to form an N-type drift region wrapping the P-type shielding layer;
p-type doped ions and N-type doped ions are sequentially injected into the N-type drift region to form a P-type base layer, an N-type source layer, a first P-type body region and a second P-type body region; the first P-type body region and the second P-type body region are positioned on two sides of the P-type base layer;
etching the N-type source layer to form a first deep groove penetrating into the N-type drift region so as to divide the P-type shielding layer into a first P-type shielding region and a second P-type shielding region, divide the P-type base layer into a first P-type base region and a second P-type base region, and divide the N-type source layer into a first N-type source region and a second N-type source region;
forming a gate dielectric layer at the bottom and the side wall of the first deep groove, filling a polysilicon material to form a shielding gate polysilicon layer, and then filling the polysilicon material to form the gate polysilicon layer after continuing to form the gate dielectric layer; the grid electrode polycrystalline silicon layer is positioned above the shielding grid polycrystalline silicon layer, and the grid electrode dielectric layer wraps the shielding grid polycrystalline silicon layer and the grid electrode polycrystalline silicon layer respectively;
forming a source layer on the first N-type source region and the second N-type source region, and forming a drain layer on the back surface of the silicon carbide substrate; the source electrode layer is connected with the shielding gate polycrystalline silicon layer.
10. A chip comprising a shielded gate superjunction MOSFET according to any of claims 1-8; or a shielded gate superjunction MOSFET prepared by the preparation method of claim 9.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202410142405.2A CN117673164A (en) | 2024-02-01 | 2024-02-01 | Shielded gate super-junction MOSFET (Metal-oxide-semiconductor field Effect transistor) and preparation method and chip thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202410142405.2A CN117673164A (en) | 2024-02-01 | 2024-02-01 | Shielded gate super-junction MOSFET (Metal-oxide-semiconductor field Effect transistor) and preparation method and chip thereof |
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| Publication Number | Publication Date |
|---|---|
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| KR20230015774A (en) * | 2021-07-23 | 2023-01-31 | 서강대학교산학협력단 | Mosfet device and method thereof |
| CN116110944A (en) * | 2023-04-12 | 2023-05-12 | 江苏应能微电子股份有限公司 | Shielded gate trench MOSFET device based on Resurf effect and preparation method thereof |
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| KR20220003229A (en) * | 2020-07-01 | 2022-01-10 | 서강대학교산학협력단 | Silicon Carbide Transistor And Fabrication Method Thereof |
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