CN117497568B - SGTMOS device with left and right gate structures, preparation method thereof and chip - Google Patents

SGTMOS device with left and right gate structures, preparation method thereof and chip Download PDF

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CN117497568B
CN117497568B CN202311812524.6A CN202311812524A CN117497568B CN 117497568 B CN117497568 B CN 117497568B CN 202311812524 A CN202311812524 A CN 202311812524A CN 117497568 B CN117497568 B CN 117497568B
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doped region
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CN117497568A (en
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景俊豪
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Sirius Semiconductor Chengdu Co ltd
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Sirius Semiconductor Chengdu Co ltd
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Abstract

The application belongs to the technical field of power devices and provides a SGTMOS device with a left-right gate structure, a preparation method and a chip thereof, wherein a drain electrode layer, an N-type substrate layer and an N-type drift layer are arranged in a stacked mode, the N-type drift layer is in a concave structure, a first P-type heavily doped region and a second P-type heavily doped region which are opposite are formed at the bottom of a groove of the N-type drift layer, the first P-type heavily doped region and the second P-type heavily doped region are respectively arranged below two sides of the N-type drift layer, a depletion layer can be formed at the bottom of the groove, the peak electric field at the round angle position below a shielding gate is reduced, the breakdown voltage of the device is improved, and the width of the depletion region can be reduced by respectively forming the first N-type doped region and the second N-type doped region at two side walls of the groove of the N-type drift layer, so that the purposes of reducing the on resistance and improving the performance of the device are achieved.

Description

SGTMOS device with left and right gate structures, preparation method thereof and chip
Technical Field
The application belongs to the technical field of power devices, and particularly relates to a SGTMOS device with a left-right gate structure, a preparation method thereof and a chip.
Background
The shielded gate trench (SHIELD GATE TRENCH, SGT) structured metal oxide semiconductor (Metal Oxide Semiconductor, MOS) device is widely used as a switching device in a power management system, and is a core power control component. The gate structure of SGTMOS devices includes a shielded polysilicon structure and a polysilicon gate structure in the deep trench, where the shielded polysilicon structure is located in a lower portion of the deep trench and the polysilicon gate structure is located in an upper portion of the deep trench. The shielding polysilicon structure, the polysilicon gate structure and the deep trench are isolated from each other. The top layer of the active region forms a channel region, and the surface layer of the epitaxial layer on the channel region forms the source region. The source electrode is connected with the source region through a contact hole, and a heavily doped contact region is formed around the bottom end of the contact hole for leading out the source electrode, and the heavily doped contact region is in contact with the channel region.
However, the current SGTMOS device has a high peak field strength phenomenon at the bottom of the shielding gate, which can cause the SGTMOS device to break down at the position, reduce the Breakdown Voltage (BV) of the device, and finally cause the device to fail, so that the performance of the device is greatly affected.
Disclosure of Invention
In order to solve the technical problems, embodiments of the present application provide a SGTMOS device with a left-right gate structure, a preparation method thereof, and a chip, which can improve the breakdown voltage of the device while reducing the on-resistance of the device.
A first aspect of an embodiment of the present application provides a SGTMOS device having a left and right gate structure, the SGTMOS device having a left and right gate structure including:
An N-type drift layer formed on the front surface of the N-type substrate layer;
The drain electrode layer is formed on the back surface of the N-type substrate layer;
The first N-type doped region and the second N-type doped region are respectively formed on two side walls of the groove of the N-type drift layer; wherein the N-type drift layer is of a concave structure;
The first P well and the second P well are respectively arranged above two side parts of the N-type drift layer;
The first N-type source region and the second N-type source region are respectively arranged on the first P well and the second P well;
The first P type heavily doped region and the second P type heavily doped region are arranged at the bottom of the N type drift layer and are respectively positioned below two side parts of the N type drift layer;
the grid electrode dielectric layer is used for isolating the shielding grid polycrystalline silicon layer;
The first grid electrode conductive polycrystalline silicon layer and the second grid electrode conductive polycrystalline silicon layer are respectively positioned at two sides of the shielding grid polycrystalline silicon layer and are isolated from the shielding grid polycrystalline silicon layer by the grid electrode dielectric layer;
The shielding gate electrode layer is contacted with the shielding gate polysilicon layer through the packaging layer;
The first grid electrode and the second grid electrode are respectively contacted with the first grid conductive polycrystalline silicon layer and the second grid conductive polycrystalline silicon layer through the packaging layer;
The first source electrode is respectively contacted with the first N-type source region and the first P well through the through hole on the packaging layer; and the second source electrode is respectively contacted with the second N-type source region and the second P well through the through hole on the packaging layer.
In one embodiment, the first N-type doped region and the second N-type doped region are the same in height.
In one embodiment, the length of the shielding gate polysilicon layer is greater than the lengths of the first gate conductive polysilicon layer and the second gate conductive polysilicon layer.
In one embodiment, the length of the shield gate polysilicon layer is at least 2 times the length of the first gate conductive polysilicon layer and the second gate conductive polysilicon layer.
In one embodiment, the first gate conductive polysilicon layer and the second gate conductive polysilicon layer are axisymmetrically arranged with respect to the shield gate polysilicon layer.
In one embodiment, the first P-type heavily doped region and the second P-type heavily doped region are axisymmetrically arranged along a straight extension line of the shielding gate polysilicon layer.
In one embodiment, the widths of the first and second N-type doped regions gradually increase from bottom to top.
In one embodiment, the first N-type doped region and the second N-type doped region have a trapezoid structure.
The second aspect of the embodiment of the application also provides a preparation method of SGTMOS devices with left and right gate structures, which comprises the following steps:
Forming an N-type drift layer on the front surface of an N-type substrate layer, injecting P-type doping ions into two sides of the front surface of the N-type drift layer to form a first P-type heavily doped region and a second P-type heavily doped region respectively, and forming a drain electrode layer on the back surface of the N-type substrate layer;
Continuing to carry out epitaxial growth on the N-type drift layer, and etching to form a groove on the N-type drift layer;
Injecting N-type doping ions into two side walls of the groove of the N-type drift layer to form a first N-type doping region and a second N-type doping region respectively;
Filling a dielectric material into the groove of the N-type drift layer to form a gate dielectric layer, and forming a first deep groove, a second deep groove and a third deep groove in the gate dielectric layer; the third deep groove is positioned between the first deep groove and the second deep groove, and the depth of the third deep groove is larger than the depths of the first deep groove and the second deep groove;
filling a polysilicon material, forming a first grid electrode conductive polysilicon layer and a second grid electrode conductive polysilicon layer in the first deep groove and the second deep groove respectively, and forming a shielding grid polysilicon layer in the third deep groove; the shielding gate polysilicon layer is isolated from the first N-type doped region and the second N-type doped region by the gate dielectric layer;
Forming a first P well and a second P well above two side parts of the N-type drift layer, and forming a first N-type source region and a second N-type source region on the first P well and the second P well respectively;
Depositing packaging materials to form a packaging layer, and forming a plurality of through holes on the packaging layer;
Depositing a metal electrode material, and etching the metal electrode material to form a shielding gate electrode layer, a first gate electrode, a second gate electrode, a first source electrode and a second source electrode; the first grid electrode and the second grid electrode are respectively contacted with the first grid conductive polysilicon layer and the second grid conductive polysilicon layer through the packaging layer, the first source electrode is respectively contacted with the first N-type source region and the first P-well through the through holes on the packaging layer, and the second source electrode is respectively contacted with the second N-type source region and the second P-well through the through holes on the packaging layer.
The third aspect of the embodiment of the present application further provides a chip, which includes a SGTMOS device having a left-right gate structure according to any one of the above embodiments.
The embodiment of the application has the beneficial effects that: the first P type heavy doping region and the second P type heavy doping region are formed at the bottom of the groove of the N type drift layer, the first P type heavy doping region and the second P type heavy doping region are respectively arranged below two sides of the N type drift layer, a depletion layer can be formed at the bottom of the groove, the peak electric field at the round angle position below the shielding grid is reduced, the breakdown voltage of the device is improved, and the first N type doping region and the second N type doping region are respectively formed at two side walls of the groove of the N type drift layer, so that the width of the depletion region can be reduced, and the purposes of reducing on resistance and improving the performance of the device are achieved.
Drawings
Fig. 1 is a schematic structural diagram of a SGTMOS device with a left-right gate structure according to an embodiment of the present application;
fig. 2 is a schematic flow chart of a method for manufacturing SGTMOS devices with left and right gate structures according to an embodiment of the present application;
Fig. 3 is a schematic diagram of a drain layer 110, an N-type substrate layer 120, and an N-type drift layer 130 according to an embodiment of the present application;
Fig. 4 is a schematic diagram of an embodiment of the present application after etching the N-type drift layer 130 and forming the first P-type heavily doped region 210 and the second P-type heavily doped region 220;
Fig. 5 is a schematic diagram of the first N-type doped region 121 and the second N-type doped region 122 according to the embodiment of the present application;
Fig. 6 is a schematic diagram of a shielding gate polysilicon layer 310, a first gate conductive polysilicon layer 321, a second gate conductive polysilicon layer 322, a first P-well 410, a second P-well 420, a first N-type source region 510, a second N-type source region 520, a first source electrode 611, and a second source electrode 612 according to an embodiment of the present application;
110: a drain layer; 120: an N-type substrate layer; 130: an N-type drift layer; 210: a first P-type heavily doped region; 220: a second P-type heavily doped region; 121: a first N-type doped region; 122: a second N-type doped region; 310: a shield gate polysilicon layer; 321: a first gate conductive polysilicon layer; 322: a second gate conductive polysilicon layer; 611: a first source electrode; 612: a second source electrode; 621: a first gate; 622: a second gate; 230: a gate dielectric layer; 201: a groove.
Detailed Description
In order to make the technical problems, technical schemes and beneficial effects to be solved more clear, the application is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the application.
It will be understood that when an element is referred to as being "mounted" or "disposed" on another element, it can be directly on the other element or be indirectly on the other element. When an element is referred to as being "connected to" another element, it can be directly connected to the other element or be indirectly connected to the other element.
It is to be understood that the terms "length," "width," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," and the like are merely for convenience in describing and simplifying the description based on the orientation or positional relationship shown in the drawings, and do not indicate or imply that the devices or elements referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus are not to be construed as limiting the application.
Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include one or more such feature. In the description of the present application, the meaning of "a plurality" is one or more than one unless specifically defined otherwise.
The current SGTMOS device has a phenomenon of high peak field intensity at the bottom of a shielding gate, the phenomenon can cause the SGTMOS device to break down at the position, the Breakdown Voltage (BV) of the device is reduced, and finally the device is invalid, so that the performance of the device is greatly influenced. On the other hand, the N-type drift region in the device has intrinsic resistance caused by the structure and the process, and the excessive intrinsic resistance can increase the loss of the device in the on state and affect the performance of the device. In addition, SGTMOS devices have reverse transmission capacitance due to structural reasons, which can increase switching loss and is unfavorable for practical application of the devices.
In order to solve the above technical problem, an embodiment of the present application provides a SGTMOS device having a left-right gate structure, as shown in fig. 1, a SGTMOS device having a left-right gate structure in this embodiment includes: the drain layer 110, the N-type substrate layer 120, the N-type drift layer 130, the first P-type heavily doped region 210, the second P-type heavily doped region 220, the first N-type doped region 121, the second N-type doped region 122, the shield gate polysilicon layer 310, the first gate conductive polysilicon layer 321, the second gate conductive polysilicon layer 322, the first P-well 410, the second P-well 420, the first N-type source region 510, the second N-type source region 520, the first source electrode 611, the second source electrode 612, the first gate 621, the second gate 622, the gate dielectric layer 230.
In the embodiment, the drain layer 110, the N-type substrate layer 120 and the N-type drift layer 130 are stacked, and the N-type drift layer 130 has a concave structure, the first P-type heavily doped region 210 and the second P-type heavily doped region 220 are respectively formed at the bottom of the N-type drift layer 130, and the first P-type heavily doped region 210 and the second P-type heavily doped region 220 are disposed opposite to each other. As shown in fig. 1, the first P-type heavily doped region 210 and the second P-type heavily doped region 220 are located at the edge of the bottom of the N-type drift layer 130, and the first P-type heavily doped region 210 and the second P-type heavily doped region 220 are not in contact with the N-type substrate layer 120.
The first N-type doped region 121 and the second N-type doped region 122 are respectively formed on two sidewalls of the groove of the N-type drift layer 130; the shielding gate polysilicon layer 310 is formed in the recess of the N-type drift layer 130, and is isolated from the first N-type doped region 121 and the second N-type doped region 122 by the gate dielectric layer 230. The first P-well 410 and the second P-well 420 are respectively disposed above two sides of the N-type drift layer 130, and the first N-type source region 510 and the second N-type source region 520 are respectively disposed on the first P-well 410 and the second P-well 420.
The first gate conductive polysilicon layer 321 and the second gate conductive polysilicon layer 322 are formed on two sides of the shielding gate polysilicon layer 310, and are isolated from the shielding gate polysilicon layer 310, the first P-well 410, the second P-well 420, the first N-type source region 510 and the second N-type source region 520 by the gate dielectric layer 230. The first source electrode 611 and the second source electrode 612 are respectively contacted with the first P-well 410 and the second P-well 420 through the through holes on the first N-type source region 510 and the second N-type source region 520, and the first gate 621 and the second gate 622 are respectively contacted with the first gate conductive polysilicon layer 321 and the second gate conductive polysilicon layer 322.
In this embodiment, the first P-type heavily doped region 210 and the second P-type heavily doped region 220 are disposed opposite to the edge regions of the bottom of the N-type drift layer 130 of the shield gate polysilicon layer 310 and the bottom of the concave structure, and the first P-type heavily doped region 210 and the second P-type heavily doped region 220 are located at two sides of the bottom of the concave groove of the N-type drift layer 130, so that a depletion layer can be formed at the bottom of the concave groove of the N-type drift layer 130, thereby reducing the peak electric field at the bottom of the shield gate polysilicon layer 310 and achieving the purpose of improving the breakdown voltage of the device. On the other hand, the first N-type doped region 121 and the second N-type doped region 122 are formed on two sidewalls of the concave groove of the N-type drift layer 130, respectively, the first N-type doped region 121 and the second N-type doped region 122 are located on two sides of the shielding gate polysilicon layer 310, and the first N-type doped region 121, the second N-type doped region 122 and the shielding gate polysilicon layer 310 are isolated by the gate dielectric layer 230, so as to assist in shielding effect of the first P-type heavily doped region 210 and the second P-type heavily doped region 220, so that electric field distribution in the vertical direction is more uniform, and stability of breakdown voltage of the device is improved.
In one embodiment, the first N-type doped region 121 and the second N-type doped region 122 have the same height.
In this embodiment, the heights of the first N-type doped region 121 and the second N-type doped region 122 are the same, and a uniform electric field can be formed between two sidewalls of the concave groove of the N-type drift layer 130, so as to assist in shielding effect of the first P-type heavily doped region 210 and the second P-type heavily doped region 220, and improve stability of breakdown voltage of the device.
In one embodiment, the length of the shield gate polysilicon layer 310 is greater than the lengths of the first gate conductive polysilicon layer 321, the second gate conductive polysilicon layer 322.
In this embodiment, after the first gate 621 and the second gate 622 are applied with voltages, an electric field is generated between two sidewalls of the concave groove of the N-type drift layer 130, and the length of the shielding gate polysilicon layer 310 is set to be greater than that of the first gate conductive polysilicon layer 321 and the second gate conductive polysilicon layer 322, so that the whole shielding gate polysilicon layer 310 is located in the electric field between two sidewalls of the concave groove of the N-type drift layer 130, and the shapes of the first N-type doped region 121 and the second N-type doped region 122 are designed according to the application scenario of the SGTMOS device with the left-right gate structure, so that the electric field between the first N-type doped region 121 and the second N-type doped region 122 is uniformly distributed.
For example, after the first gate 621 and the second gate 622 of the SGTMOS device having the left and right gate structures are applied with voltages, the electric field intensity between the first N-type doped region 121 and the second N-type doped region 122 and the distance between the position and the first gate conductive polysilicon layer 321 and the second gate conductive polysilicon layer 322 are related, so by designing the shapes of the first N-type doped region 121 and the second N-type doped region 122, the electric field between the first N-type doped region 121 and the second N-type doped region 122 is uniformly distributed, the breakdown voltage of the device can be stabilized within a specific voltage range, and the problem that the device is broken down at any time due to a small electric field or non-uniformity of the electric field at a certain place is avoided.
In one embodiment, the lengths of the first gate conductive polysilicon layer 321 and the second gate conductive polysilicon layer 322 are the same.
In one embodiment, the length of the shield gate polysilicon layer 310 is at least 2 times the length of the first gate conductive polysilicon layer 321 and the second gate conductive polysilicon layer 322.
In one embodiment, the first gate conductive polysilicon layer 321, the second gate conductive polysilicon layer 322 are disposed parallel to the shield gate polysilicon layer 310.
In one embodiment, the first gate conductive polysilicon layer 321 and the second gate conductive polysilicon layer 322 are symmetrically disposed with respect to the shield gate polysilicon layer 310 as a symmetry axis.
In one embodiment, the first P-type heavily doped region 210 and the second P-type heavily doped region 220 are symmetrically disposed with respect to a line extending from a line where the shielding gate polysilicon layer 310 is located as a symmetry axis.
In one embodiment, the widths of the first N-type doped region 121 and the second N-type doped region 122 gradually increase from bottom to top.
In this embodiment, by setting the widths of the first N-type doped region 121 and the second N-type doped region 122 to gradually increase from bottom to top, a uniform electric field can be formed between two sidewalls of the concave groove of the N-type drift layer 130, thereby assisting in shielding effect of the first P-type heavily doped region 210 and the second P-type heavily doped region 220 and improving stability of breakdown voltage of the device.
In one embodiment, the first N-type doped region 121 and the second N-type doped region 122 have a trapezoid structure.
In this embodiment, by setting the first N-type doped region 121 and the second N-type doped region 122 to have trapezoid structures, a uniform electric field can be formed between two sidewalls of the concave groove of the N-type drift layer 130, thereby assisting in shielding effect of the first P-type heavily doped region 210 and the second P-type heavily doped region 220 and improving stability of breakdown voltage of the device.
In one embodiment, the first N-type doped region 121 and the second N-type doped region 122 are disposed in parallel, and the heights of the first N-type doped region 121 and the second N-type doped region 122 are greater than the widths of the first P-type heavily doped region 210 and the second P-type heavily doped region 220.
In one embodiment, the concentration of the N-type doping element in the first N-type doped region 121 and the second N-type doped region 122 is at least 100 times that in the N-type drift layer 130.
In one embodiment, the concentration of the N-type doping element in the N-type substrate is greater than the concentration of the N-type doping element in the N-type drift layer 130 and less than the concentrations of the N-type doping elements in the first N-type doping region 121 and the second N-type doping region 122.
In one embodiment, the concentration gradient of the N-type doping element in the first N-type doped region 121 and the second N-type doped region 122 may be set, so that a uniform electric field is formed between two sidewalls of the concave groove of the N-type drift layer 130, thereby assisting in shielding effect of the first P-type heavily doped region 210 and the second P-type heavily doped region 220, and improving stability of breakdown voltage of the device.
For example, in one embodiment, the doping concentration of the first N-type doped region 121 and the second N-type doped region 122 increases gradually in the direction close to the first gate conductive polysilicon layer 321 and the second gate conductive polysilicon layer 322, so that a uniform electric field is formed between two sidewalls of the concave groove of the N-type drift layer 130, thereby assisting in shielding effect of the first P-type heavily doped region 210 and the second P-type heavily doped region 220, and improving stability of breakdown voltage of the device.
In one embodiment, the concentration of the P-type doping element in the first P-type heavily doped region 210 and the second P-type heavily doped region 220 is greater than the concentration of the P-type doping element in the first P-well 410 and the second P-well 420.
In one embodiment, the first N-type doped region 121 and the second N-type doped region 122 are respectively contacted with two ends of the first P-type heavily doped region 210 and the second P-type heavily doped region 220.
In one embodiment, the first source electrode 611 extends through a via in the first N-type source region 510 to the first P-well 410; the second source electrode 612 penetrates into the second P-well 420 through a via in the second N-type source region 520.
In one embodiment, the widths of the first gate conductive polysilicon layer 321, the second gate conductive polysilicon layer 322 are greater than the width of the shield gate polysilicon layer 310.
In one embodiment, gate dielectric layer 230 may be silicon oxide or silicon nitride.
In one embodiment, the concentration of the P-type doping element in the first P-type heavily doped region 210 and the second P-type heavily doped region 220 is at least 100 times that in the first P-well 410 and the second P-well 420.
In one embodiment, the P-type doping element may be magnesium element, aluminum element, or the like.
In one embodiment, the concentration of the N-type doping element in the first N-type doped region 121 and the second N-type doped region 122 is at least 10 times that in the N-type drift layer 130, and the N-type doping element may be nitrogen or phosphorus.
The embodiment of the application also provides a preparation method of the SGTMOS device with the left and right gate structures, which is shown in fig. 2, and the preparation method in the embodiment comprises the following steps: step S100 to step S800.
In step S100, an N-type drift layer 130 is formed on the front surface of the N-type substrate layer 120, P-type dopant ions are implanted into both sides of the front surface of the N-type drift layer 130 to form a first P-type heavily doped region 210 and a second P-type heavily doped region 220, respectively, and a drain layer 110 is formed on the back surface of the N-type substrate layer 120.
In this embodiment, as shown in fig. 3, the N-type drift layer 130 may be grown on the front surface of the N-type substrate layer 120 by an epitaxial growth process, P-type doped ions may be implanted to both sides of the front surface of the N-type drift layer 130 by a P-type ion implantation process, and the drain layer 110 may be formed on the back surface of the N-type substrate layer 120 by depositing a metal material.
In one embodiment, the depth and width of the first and second P-type heavily doped regions 210 and 220 are the same, and the concentration of the P-type dopant ions doped in the first and second P-type heavily doped regions 210 and 220 is also the same.
In step S200, the N-type drift layer 130 is continuously epitaxially grown, and the recess 201 is etched on the N-type drift layer 130.
Referring to fig. 4, after the epitaxial growth, the thickness of the N-type drift layer 130 is increased, and a portion of the N-type drift layer 130 that is epitaxially grown covers the first P-type heavily doped region 210 and the second P-type heavily doped region 220, and a recess 201 is formed by etching the N-type drift layer 130 through an etching process, where the depth of the recess 201 does not exceed the upper surfaces of the first P-type heavily doped region 210 and the second P-type heavily doped region 220, so as to form a depletion layer in the region between the first P-type heavily doped region 210 and the second P-type heavily doped region 220.
In one embodiment, the center of the recess 201 is located on the middle line between the first P-type heavily doped region 210 and the second P-type heavily doped region 220.
In step S300, N-type doping ions are implanted into two sidewalls of the recess 201 of the N-type drift layer 130 to form the first N-type doped region 121 and the second N-type doped region 122, respectively.
In this embodiment, N-type doped ions may be implanted into two sidewalls of the recess 201 of the N-type drift layer 130 by an ion implantation process, so as to form the first N-type doped region 121 and the second N-type doped region 122 on the two sidewalls of the recess 201, respectively.
In one embodiment, N-type doped ions are implanted into two sidewalls of the recess of the N-type drift layer 130 through an inclined ion implantation process to form a first N-type doped region 121 and a second N-type doped region 122, the doping concentration of the first N-type doped region 121 and the second N-type doped region 122 is greater than the concentration of the N-type doped ions in the N-type drift layer 130, and the heights of the first N-type doped region 121 and the second N-type doped region 122 are the same.
In step S400, a gate dielectric layer 230 is formed by filling a dielectric material into the recess of the N-type drift layer 130, and a first deep trench, a second deep trench, and a third deep trench are formed in the gate dielectric layer 230.
In this embodiment, the third deep groove is located between the first deep groove and the second deep groove, and the depth of the third deep groove is greater than the depths of the first deep groove and the second deep groove. The gate dielectric layer 230 may be first filled in the recess of the N-type drift layer 130.
In step S500, a polysilicon material is filled, a first gate conductive polysilicon layer 321, a second gate conductive polysilicon layer 322 are formed in the first deep trench and the second deep trench, respectively, and a shield gate polysilicon layer 310 is formed in the third deep trench.
In this embodiment, the first gate conductive polysilicon layer 321 and the second gate conductive polysilicon layer 322 are formed by filling gate polysilicon material in the first deep trench and the second deep trench, and the shielding gate polysilicon layer 310 is formed by filling gate polysilicon material in the third deep trench, and the shielding gate polysilicon layer 310 is isolated from the first N-type doped region 121 and the second N-type doped region 122 by the gate dielectric layer 230, as shown in fig. 5. The first gate conductive polysilicon layer 321, the second gate conductive polysilicon layer 322 are isolated from the shielding gate polysilicon layer 310, the first P-well 410, the second P-well 420, the first N-type source region 510, and the second N-type source region 520 by the gate dielectric layer 230.
In one embodiment, the dielectric material may be a silicon nitride material or a silicon oxide material.
In step S600, a first P-well 410 and a second P-well 420 are formed over both sides of the N-type drift layer 130, and a first N-type source region 510 and a second N-type source region 520 are formed on the first P-well 410 and the second P-well 420, respectively.
In this embodiment, as shown in fig. 6, the first and second N-type source regions 510 and 520 may be formed by implanting P-type dopant ions over the two sides of the N-type drift layer 130, forming the first and second P-wells 410 and 420 over the two sides of the N-type drift layer 130, and continuing to implant N-type dopant ions over the two sides of the N-type drift layer 130. The energy of the N-type dopant ions injected when forming the first and second N-type source regions 510, 520 is smaller than the energy of the P-type dopant ions injected when forming the first and second P-wells 410, 420, such that the first and second N-type source regions 510, 520 are formed on the first and second P-wells 410, 420, respectively.
In step S700, an encapsulation material is deposited to form an encapsulation layer 630, and a plurality of through holes are formed on the encapsulation layer 630.
In step S800, a metal electrode material is deposited and etched to form a shield gate electrode layer 330, a first gate electrode 621, a second gate electrode 622, a first source electrode 611, and a second source electrode 612.
As shown in fig. 1, a plurality of through holes are etched on the encapsulation layer 630, then a metal electrode material is deposited, and the metal electrode material is etched to form a shield gate electrode layer 330, a first gate electrode 621, a second gate electrode 622, a first source electrode 611, and a second source electrode 612.
In this embodiment, the shielding gate electrode layer 330 contacts the shielding gate polysilicon layer 310 through the encapsulation layer 630, the first gate electrode 621 and the second gate electrode 622 contact the first gate conductive polysilicon layer 321 and the second gate conductive polysilicon layer 322 through the through holes on the encapsulation layer 630, the first source electrode 611 contacts the first N-type source region 510 and the first P-well 410 through the through holes on the encapsulation layer 630, and the second source electrode 612 contacts the second N-type source region 520 and the second P-well 420 through the through holes on the encapsulation layer 630.
In one embodiment, the order of step S400 and step S500 may be replaced.
In step S600, a first source electrode 611 and a second source electrode 612 are formed on the first N-type source region 510 and the second N-type source region 520, respectively, and a first gate 621 and a second gate 622 are formed on the first gate conductive polysilicon layer 321 and the second gate conductive polysilicon layer 322.
In the present embodiment, the first source electrode 611 and the second source electrode 612 are respectively contacted with the first P-well 410 and the second P-well 420 through the through holes on the first N-type source region 510 and the second N-type source region 520, and the first gate 621 and the second gate 622 are respectively contacted with the first gate conductive polysilicon layer 321 and the second gate conductive polysilicon layer 322.
The embodiment of the application also provides a chip, which comprises the SGTMOS device with the left and right gate structures, which is prepared by the preparation method of the SGTMOS device with the left and right gate structures in the embodiment.
In this embodiment, the chip includes a chip substrate, on which one or more SGTMOS devices having left and right gate structures are disposed, where the SGTMOS devices having left and right gate structures may be manufactured by the manufacturing method in any of the above embodiments, or the SGTMOS devices having left and right gate structures in any of the above embodiments may be disposed on the chip substrate.
In one embodiment, other related semiconductor devices can be integrated on the chip substrate, and the semiconductor devices and SGTMOS devices with left and right gate structures form an integrated circuit.
In one specific application embodiment, the chip may be a switching chip or a driving chip.
The embodiment of the application has the beneficial effects that: the first P type heavy doping region and the second P type heavy doping region are formed at the bottom of the groove of the N type drift layer, a depletion layer can be formed at the bottom of the groove, the peak electric field at the round angle position below the shielding grid can be reduced, the breakdown voltage of the device is improved, the first N type doping region and the second N type doping region are respectively formed at two sides of the groove of the N type drift layer, the width of the depletion region can be reduced, and the purposes of reducing on resistance and improving the performance of the device are achieved.
It will be apparent to those skilled in the art that, for convenience and brevity of description, only the above-described division of each doped region and device is illustrated, and in practical application, the above-described function allocation may be performed by different doped regions and devices according to needs, i.e. the internal structure of the device is divided into different doped regions, so as to perform all or part of the above-described functions. The doped regions and the devices in the embodiments can be integrated in one unit, or each unit can exist alone physically, or two or more units can be integrated in one unit.
In addition, the specific names of the doped regions and the devices are only used for distinguishing the doped regions and the devices from each other, and are not used for limiting the protection scope of the application.
In the foregoing embodiments, the descriptions of the embodiments are emphasized, and in part, not described or illustrated in any particular embodiment, reference is made to the related descriptions of other embodiments.
In addition, each doped region in the embodiments of the present application may be integrated in one unit, or each unit may exist alone physically, or two or more units may be integrated in one unit.
The above embodiments are only for illustrating the technical solution of the present application, and are not limiting; although the application has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit and scope of the technical solutions of the embodiments of the present application, and are intended to be included in the scope of the present application.

Claims (9)

1. A SGTMOS device having a left and right gate structure, the SGTMOS device having a left and right gate structure comprising:
An N-type drift layer formed on the front surface of the N-type substrate layer;
The drain electrode layer is formed on the back surface of the N-type substrate layer;
The first N-type doped region and the second N-type doped region are respectively formed on two side walls of the groove of the N-type drift layer; wherein the N-type drift layer is of a concave structure;
The first P well and the second P well are respectively arranged above two side parts of the N-type drift layer;
The first N-type source region and the second N-type source region are respectively arranged on the first P well and the second P well;
The first P type heavily doped region and the second P type heavily doped region are arranged at the bottom of the N type drift layer and are respectively positioned below two side parts of the N type drift layer;
the grid electrode dielectric layer is used for isolating the shielding grid polycrystalline silicon layer;
The first grid electrode conductive polycrystalline silicon layer and the second grid electrode conductive polycrystalline silicon layer are respectively positioned at two sides of the shielding grid polycrystalline silicon layer and are isolated from the shielding grid polycrystalline silicon layer by the grid electrode dielectric layer;
The shielding gate electrode layer is contacted with the shielding gate polysilicon layer through the packaging layer;
The first grid electrode and the second grid electrode are respectively contacted with the first grid conductive polycrystalline silicon layer and the second grid conductive polycrystalline silicon layer through the packaging layer;
The first source electrode is respectively contacted with the first N-type source region and the first P well through the through hole on the packaging layer; the second source electrode is respectively contacted with the second N-type source region and the second P well through the through hole on the packaging layer;
The first P type heavy doping region and the second P type heavy doping region are positioned at the edge position of the bottom of the N type drift layer, and the first P type heavy doping region and the second P type heavy doping region are not contacted with the N type substrate layer; the concentration of the P-type doping elements in the first P-type heavily doped region and the second P-type heavily doped region is larger than that in the first P well and the second P well; the widths of the first N-type doped region and the second N-type doped region gradually increase from bottom to top.
2. The SGTMOS device having a left-right gate structure of claim 1, wherein the first N-type doped region and the second N-type doped region are the same height.
3. The SGTMOS device having a left-right gate structure of claim 1, wherein the length of the shield gate polysilicon layer is greater than the lengths of the first gate conductive polysilicon layer and the second gate conductive polysilicon layer.
4. The SGTMOS device having a left and right gate structure of claim 3 wherein the length of the shield gate polysilicon layer is at least 2 times the length of the first gate conductive polysilicon layer and the second gate conductive polysilicon layer.
5. The SGTMOS device having a left-right gate structure of claim 1, wherein the first gate conductive polysilicon layer and the second gate conductive polysilicon layer are axisymmetrically disposed with respect to the shield gate polysilicon layer.
6. The SGTMOS device with a left-right gate structure as claimed in claim 1, wherein the first P-type heavily doped region and the second P-type heavily doped region are axisymmetrically arranged with a straight extension line of the shielding gate polysilicon layer.
7. The SGTMOS device having a left-right gate structure of claim 1, wherein the first N-type doped region and the second N-type doped region are trapezoidal structures.
8. A preparation method of SGTMOS devices with left and right gate structures is characterized by comprising the following steps:
Forming an N-type drift layer on the front surface of an N-type substrate layer, injecting P-type doping ions into two sides of the front surface of the N-type drift layer to form a first P-type heavily doped region and a second P-type heavily doped region respectively, and forming a drain electrode layer on the back surface of the N-type substrate layer;
Continuing to carry out epitaxial growth on the N-type drift layer, and etching to form a groove on the N-type drift layer;
Injecting N-type doping ions into two side walls of the groove of the N-type drift layer to form a first N-type doping region and a second N-type doping region respectively;
Filling a dielectric material into the groove of the N-type drift layer to form a gate dielectric layer, and forming a first deep groove, a second deep groove and a third deep groove in the gate dielectric layer; the third deep groove is positioned between the first deep groove and the second deep groove, and the depth of the third deep groove is larger than the depths of the first deep groove and the second deep groove;
filling a polysilicon material, forming a first grid electrode conductive polysilicon layer and a second grid electrode conductive polysilicon layer in the first deep groove and the second deep groove respectively, and forming a shielding grid polysilicon layer in the third deep groove; the shielding gate polysilicon layer is isolated from the first N-type doped region and the second N-type doped region by the gate dielectric layer;
Forming a first P well and a second P well above two side parts of the N-type drift layer, and forming a first N-type source region and a second N-type source region on the first P well and the second P well respectively;
Depositing packaging materials to form a packaging layer, and forming a plurality of through holes on the packaging layer;
Depositing a metal electrode material, and etching the metal electrode material to form a shielding gate electrode layer, a first gate electrode, a second gate electrode, a first source electrode and a second source electrode; the first grid electrode and the second grid electrode are respectively contacted with the first grid conductive polysilicon layer and the second grid conductive polysilicon layer through the packaging layer, the first source electrode is respectively contacted with the first N-type source region and the first P-well through the through holes on the packaging layer, and the second source electrode is respectively contacted with the second N-type source region and the second P-well through the through holes on the packaging layer; the first P type heavy doping region and the second P type heavy doping region are positioned at the edge position of the bottom of the N type drift layer, and the first P type heavy doping region and the second P type heavy doping region are not contacted with the N type substrate layer; the concentration of the P-type doping elements in the first P-type heavily doped region and the second P-type heavily doped region is larger than that in the first P well and the second P well; the widths of the first N-type doped region and the second N-type doped region gradually increase from bottom to top.
9. A chip comprising a SGTMOS device having a left-right gate structure as claimed in any one of claims 1 to 7; or SGTMOS device with left and right gate structures prepared by the preparation method of SGTMOS device with left and right gate structures as claimed in claim 8.
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