CN116469916A - Groove type silicon carbide MOSFET and manufacturing method thereof - Google Patents

Groove type silicon carbide MOSFET and manufacturing method thereof Download PDF

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CN116469916A
CN116469916A CN202310615476.5A CN202310615476A CN116469916A CN 116469916 A CN116469916 A CN 116469916A CN 202310615476 A CN202310615476 A CN 202310615476A CN 116469916 A CN116469916 A CN 116469916A
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trench
gate
source
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刘冬梅
张琨
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Huarui Chuangxin Semiconductor Chengdu Co ltd
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Huarui Chuangxin Semiconductor Chengdu Co ltd
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Abstract

The invention belongs to the technical field of power semiconductor devices, and relates to a trench type silicon carbide MOSFET and a manufacturing method thereof. The separation gate, the P-type JFET region and the P+ shielding region introduced by the invention jointly reduce the gate-drain capacitance of the device, and optimize the switching capacity of the device; in addition, the P-type JFET region and the P+ shielding region can effectively relieve the electric field concentration phenomenon in the oxide layer, improve the reliability of the oxide layer, and further improve the voltage-resistant capability of the device by separating the thick oxide layer at the bottom of the gate from the low-doped P-type JFET region; the narrow-width and high-doped N-type injection region, the first split gate and the P-type JFET region form a parasitic double-gate JFET structure, a low-resistance conductive channel is formed at the parasitic double-gate JFET structure, the on-resistance of the device is reduced, the saturation current of the device is clamped, and the short-circuit tolerance time of the device is prolonged. The N-type injection region is prepared by the special process provided by the invention, so that the yield is improved and the cost is saved while the high-performance N-type injection region is obtained.

Description

Groove type silicon carbide MOSFET and manufacturing method thereof
Technical Field
The invention belongs to the technical field of power semiconductor devices, and particularly relates to a trench type silicon carbide MOSFET and a manufacturing method thereof.
Background
Over the past decades, with the rapid development of technology, electrical energy has emerged in aspects of human life, and how to more efficiently utilize electrical energy has been one of the focus of research. However, most of chemical electric energy provided by various batteries, whether hydroelectric, nuclear power, thermal power or wind power, cannot be directly used, and more than 75% of electric energy application can be used by equipment after being converted by a power semiconductor device. Today, energy and environmental protection problems are becoming more and more of a concern, society has a higher demand for efficiency of power electronic systems, and performance of power semiconductor devices is also being more and more demanded.
Since the first silicon (Si) thyristor was invented in the 50 s of the last century, the development of various Si-based power devices has been very mature, taking up a major share of the market. However, through more than 60 years of development, the trade-off relationship between the blocking capability and the on-state loss of silicon-based devices has gradually approached the physical limit of the materials. Therefore, wide bandgap materials and devices are receiving increasing attention, and silicon carbide devices with more superior material properties are beginning to show unique advantages in some areas. As a third generation semiconductor material, compared with Si, siC has a breakdown electric field of nearly ten times, so that SiC power devices can withstand higher voltages; a larger forbidden bandwidth and higher thermal conductivity to accept higher operating temperatures; higher electron saturation drift velocity accommodates higher operating frequencies. These advantages of SiC materials themselves enable SiC power devices to exhibit potential sufficient to replace Si-based power devices in most current power device applications.
Currently, siC MOSFETs have been in part on the market in the range of 650V-1200V voltage levels. However, the conventional planar gate structure has disadvantages of high channel resistance, low channel density, and the like, and the improvement of the performance is still limited. Therefore, a trench MOSFET structure with a higher channel density constitutes one of the hot spots of research for SiC power devices. Fig. 1 shows a schematic structural diagram of a conventional trench SiC MOSFET, in which the introduction of a trench eliminates the JFET effect of a planar gate structure, reduces the size of a cell, increases the channel density of the device, reduces the channel resistance, and significantly improves the performance of the device. However, the improvement of channel density of the trench type SiC MOSFET further increases the saturation current density of the device, resulting in that the problem of short circuit reliability that is present in SiC planar MOSFETs becomes more serious, deteriorating the reliability of the device. Meanwhile, the parasitic capacitance of the device is increased due to the introduction of the grooves, and the switching speed of the device is influenced. Moreover, because of the wide bandgap characteristics of SiC materials themselves, the electric field concentration phenomenon in the oxide layer at the bottom of the trench is more severe than that of Si-based trench MOS, which presents a significant challenge for oxide layer reliability at the trench corners.
Disclosure of Invention
In order to improve the reliability of a groove type SiC MOSFET oxide layer, reduce the switching loss of a device and improve the short circuit tolerance capability of the device, the invention provides a groove type silicon carbide MOSFET and a manufacturing method thereof.
In order to solve the above technical problems, an embodiment of the present invention provides a trench silicon carbide MOSFET, wherein a cell structure of the trench silicon carbide MOSFET includes a back drain metal 13, an n+ substrate 12, an N-drift region 11 and a source metal 1, which are sequentially stacked from bottom to top;
the top layer of the N-drift region 11 is provided with P-type JFET regions 7 which are arranged at intervals, and the top layer of the N-drift region 11 between the P-type JFET regions 7 which are arranged at intervals is provided with a trench gate structure; the top layer of the P-type JFET region 7 is provided with a P-type channel region 6, the top layer of the P-type channel region 6 is provided with an N+ source region 4 and a p+ contact region 5 which are arranged side by side and are in mutual contact on the side surface, and the side surface of the N+ source region 4 is in contact with the side surface of the trench gate structure; the source metal 1 is located on the N+ source region 4, the P+ contact region 5 and the trench gate structure, and an insulating medium layer 2 is arranged between the source metal 1 and the trench gate structure; the doping concentration of the P-type JFET region 7 is lower than that of the P-type channel region 6;
The trench gate structure comprises a first separation gate 3-2, a second oxide layer 8-2 and a control gate 3-1 which are sequentially stacked from bottom to top, wherein the first separation gate 3-2 is in equipotential with source metal 1, the top of the control gate 3-1 is flush with the top of the trench, a first oxide layer 8-1 is arranged between the control gate 3-1 and the side wall of the trench, a third oxide layer 8-3 is arranged between the first separation gate 3-2 and the side wall of the trench, and a fourth oxide layer 8-4 is arranged between the first separation gate 3-2 and the bottom of the trench; the lower surface of the control gate 3-1 is lower than the lower surface of the P-type channel region 6, the lower surface of the P-type JFET region 7 is not lower than the lower surface of the trench gate structure and is not higher than the lower surface of the first separation gate 3-2, and the control gate 3-1, the first oxide layer 8-1 and the P-type channel region 6 form a MOS structure;
a P+ shielding region 10 is arranged in the N-drift region 11 below the trench gate structure; an N-type injection region 9 is arranged between the P-type JFET region 7 and the trench gate structure, the upper surface of the N-type injection region 9 is flush with the upper surface of the P-type JFET region 7, and the lower surface of the N-type injection region 9 is not higher than the lower surface of the trench gate structure, so that a parasitic double-gate JFET structure consisting of the P-type JFET region 7, the N-type injection region 9 and the first separation gate 3-2 is formed below the MOS structure; the saturation current of the parasitic double-gate JFET structure is lower than the saturation current of the MOS structure.
The working principle of the invention is as follows:
according to the invention, the first separation gate 3-2, the P-type JFET region 7 and the P+ shielding region 10 are introduced, so that the coupling between gate and drain is effectively shielded, the gate and drain capacitance is reduced, and the working capacity of the device under high frequency is improved. Meanwhile, under the dual actions of the P-type JFET region 7 and the first separation gate 3-2, a parasitic double-gate JFET structure connected in series with the trench MOS structure is formed at the introduced narrow-width and high-doped N-type injection region 9. Thanks to the N-type implanted region 9 of higher concentration, the on-resistance of the device is greatly improved at this point, and the saturation current of the parasitic double gate JFET structure is lower than that of the MOS structure.
When the device is in a normal working state, due to the existence of the parasitic double-gate JFET structure, only an electron conduction path of an N-type injection region 9 exists between an N-drift region 11 and a P-type channel region 6, and at the moment, due to the fact that the potential of the drift region under the N-type injection region 9 is lower and the concentration of the N-type injection region 9 is higher, the bilateral depletion effect of the first separation gate 3-2 and the P-type JFET region 7 on the N-type injection region 9 is weaker, the on-resistance of the device at the position is greatly improved, and the forward conduction loss of the device is greatly improved.
When the device is short-circuited, the potential of the drift region under the N-type injection region 9 will rise rapidly, at this time, the bilateral depletion effect of the first split gate 3-2 and the P-type JFET region 7 on the N-type injection region 9 increases rapidly, the N-type injection region 9 is greatly depleted, its ability as a conductive path will be further limited, and the saturation current of the parasitic JFET structure will clamp the rapidly increased current of the whole device, thereby achieving the purpose of improving the short-circuit tolerance of the device.
When the device works in a forward blocking state, a depletion layer generated among the P+ shielding region 10, the P-type JFET region 7 and the N-drift region 11 has a double protection effect on an oxide layer at the corner of the trench; the depletion effect caused by the thick oxide layer 8-4 at the bottom of the separation gate and the low-doped P-type JFET region 7 further improves the voltage withstand capability of the device.
In particular, the N-type implantation region 9 designed by the invention is etched by the trench and then is completed by the inclined side wall ion implantation process, and the process can greatly reduce the requirement on the lithography precision while obtaining the N-type implantation region 9 with narrow width and high doping, thereby being beneficial to improving the yield and saving the cost.
The beneficial effects of the invention are as follows:
firstly, the first separation gate 3-2, the P-type JFET region 7 and the P+ shielding region 10 jointly reduce the gate-drain capacitance of the device, the switching capacity of the device is optimized, the device has higher switching speed and lower switching loss, the working capacity of the device at high frequency is improved, in addition, when the device is high-voltage resistant, the P-type JFET region 7 and the P+ shielding region 10 can effectively relieve the phenomenon of electric field concentration in an oxide layer at the bottom of a channel, the reliability of the oxide layer is protected, and meanwhile, the depletion effect brought by the thick oxide layer 8-4 at the bottom of the separation gate and the low-doped P-type JFET region 7 further improves the voltage-resistant capacity of the device;
The narrow-width and high-doped N-type injection region 9, the first separation gate 3-2 and the P-type JFET region 7 form a parasitic double-gate JFET structure, a narrow-width low-resistance conductive channel is formed at the parasitic double-gate JFET structure, the on-resistance of the device is reduced, the saturation current of the device is clamped, the short-circuit tolerance time of the device is effectively improved, the reliability of the device is improved, and the trade-off relation between the on-resistance and the short-circuit capacity in the SiC MOS device is greatly improved; the N-type injection region 9 is etched by a groove and then is finished through an inclined side wall ion injection process, and the process greatly reduces the requirement on the lithography precision while obtaining the N-type injection region 9 with narrow width and high doping; the narrow-width and high-doped N-type injection region 9 clamps the saturation current of the device while reducing the on-resistance of the device, and the reduction of the requirement on the lithography precision is beneficial to improving the yield and saving the cost.
On the basis of the technical scheme, the invention can be improved as follows.
Further, the p+ shielding region 10 is located below the N-type implantation region 9, and the distance between the p+ shielding region 10 and the two outer sides of the N-type implantation region 9 at two sides of the trench gate structure is the same as the width.
Further, the n+ source region 4 extends into the p+ contact region 5, so that the p+ contact region 5 is spaced apart.
Further, the N-drift region 11 has P pillars 14 and N pillars 15 alternately arranged therein, so as to form a superjunction structure, and the superjunction structure may occupy a part of the drift region or may occupy the whole drift region.
Further, a second separation gate 3-3 is arranged in the top layer of the first separation gate 3-2, wherein the first separation gate 3-2 is N-type doped polysilicon, and the second separation gate 3-3 is P-type doped polysilicon.
Further, the second oxide layer 8-2 extends into the first separation gate 3-2, thereby forming the first separation gate 3-2 in a concave shape.
The beneficial effects of adopting the further scheme are as follows: the concave separation gate structure increases the thickness of the oxide layer between the electrodes, and effectively reduces the gate capacitance of the device.
Further, the thickness of the third oxide layer 8-3 is not greater than the thickness of the fourth oxide layer 8-4.
The beneficial effects of adopting the further scheme are as follows: the concentration of the N-type implanted region 9 can be made higher, thereby reducing the on-resistance of the device and improving the forward on-characteristic.
Further, the control gate 3-1 and the first split gate 3-2 are metal gate electrodes or polysilicon gate electrodes.
Further, the source metal 1 is selected from one of titanium, nickel, copper and aluminum or a multi-layer combination of the above metals.
Further, the semiconductor material used in the device is any one or more of SiC, silicon, germanium, gallium nitride and diamond.
In order to solve the above technical problems, an embodiment of the present invention provides a trench silicon carbide MOSFET, wherein a cell structure of the trench silicon carbide MOSFET includes a back drain metal 13, an n+ substrate 12, an N-drift region 11 and a source metal 1, which are sequentially stacked from bottom to top;
a trench gate structure is arranged in the top layer of the N-drift region 11, source trench structures are arranged on two sides of the trench gate structure, the junction depth of the source trench structure is not smaller than that of the trench gate structure, a P-type channel region 6 is arranged in the top layer of the N-drift region 11 between the trench gate structure and the source trench structure, the P-type channel region 6 extends into the N-drift region 11 under the source trench structure to form a Z-type P-type channel region 6, an N+ source region 4 is arranged on the top layer of the P-type channel region 6 between the trench gate structure and the source trench structure, and a p+ contact region 5 is arranged on the top layer of the P-type channel region 6 under the source trench structure; the source metal 1 is located on the N+ source region 4 and the trench gate structure, the source metal 1 fills the source trench structure, and an insulating medium layer 2 is arranged between the source metal 1 and the trench gate structure; a P-type JFET region 7 is arranged in the top layer of the N-drift region 11 below the P-type channel region 6, and the doping concentration of the P-type JFET region 7 is lower than that of the P-type channel region 6;
The trench gate structure comprises a first separation gate 3-2, a second oxide layer 8-2 and a control gate 3-1 which are sequentially stacked from bottom to top, wherein the first separation gate 3-2 is in equipotential with source metal 1, the top of the control gate 3-1 is flush with the top of the trench, a first oxide layer 8-1 is arranged between the control gate 3-1 and the side wall of the trench, a third oxide layer 8-3 is arranged between the first separation gate 3-2 and the side wall of the trench, and a fourth oxide layer 8-4 is arranged between the first separation gate 3-2 and the bottom of the trench; the lower surface of the control gate 3-1 is lower than the lower surface of the P-type channel region 6 between the trench gate structure and the source trench structure, and the control gate 3-1, the first oxide layer 8-1 and the P-type channel region 6 between the trench gate structure and the source trench structure form a MOS structure; the lower surface of the P-type JFET region 7 is not lower than the lower surface of the trench gate structure and is not higher than the lower surface of the first separation gate 3-2;
an N-type injection region 9 is arranged between the P-type JFET region 7 and the trench gate structure, the upper surface of the N-type injection region 9 is flush with the upper surface of the P-type JFET region 7, and the lower surface of the N-type injection region 9 is lower than the lower surface of the trench gate structure, so that a parasitic double-gate JFET structure consisting of the P-type JFET region 7, the N-type injection region 9 and the first split gate 3-2 is formed below the MOS structure; the saturation current of the parasitic double-gate JFET structure is lower than the saturation current of the MOS structure.
The working principle of the invention is as follows:
according to the invention, the first separation gate 3-2, the P-type JFET region 7 and the Z-type P-type channel region 6 are introduced, so that the coupling between gate and drain is effectively shielded, the gate and drain capacitance is reduced, and the working capacity of the device under high frequency is improved. Meanwhile, under the dual actions of the P-type JFET region 7 and the first separation gate 3-2, a parasitic double-gate JFET structure connected in series with the trench MOS structure is formed at the introduced narrow-width and high-doped N-type injection region 9. Thanks to the N-type implanted region 9 of higher concentration, the on-resistance of the device is greatly improved at this point, and the saturation current of the parasitic double gate JFET structure is lower than that of the MOS structure.
When the device is in a normal working state, due to the existence of the parasitic double-gate JFET structure, only an electron conduction path of an N-type injection region 9 exists between an N-drift region 11 and a P-type channel region 6, and at the moment, due to the fact that the potential of the drift region under the N-type injection region 9 is lower and the concentration of the N-type injection region 9 is higher, the bilateral depletion effect of the first separation gate 3-2 and the P-type JFET region 7 on the N-type injection region 9 is weaker, the on-resistance of the device at the position is greatly improved, and the forward conduction loss of the device is greatly improved.
When the device is short-circuited, the potential of the drift region under the N-type injection region 9 will rise rapidly, at this time, the bilateral depletion effect of the first split gate 3-2 and the P-type JFET region 7 on the N-type injection region 9 increases rapidly, the N-type injection region 9 is greatly depleted, its ability as a conductive path will be further limited, and the saturation current of the parasitic JFET structure will clamp the rapidly increased current of the whole device, thereby achieving the purpose of improving the short-circuit tolerance of the device.
When the device works in a forward blocking state, a depletion layer generated among the Z-type P-type channel region 6, the P-type JFET region 7 and the N-drift region 11 has a double protection effect on an oxide layer at the corner of the groove; the depletion effect caused by the thick oxide layer 8-4 at the bottom of the separation gate and the low-doped P-type JFET region 7 further improves the voltage withstand capability of the device.
In particular, the N-type implantation region 9 designed by the invention is etched by the trench and then is completed by the inclined side wall ion implantation process, and the process can greatly reduce the requirement on the lithography precision while obtaining the N-type implantation region 9 with narrow width and high doping, thereby being beneficial to improving the yield and saving the cost.
The beneficial effects of the invention are as follows:
the first separation gate 3-2, the P-type JFET region 7 and the Z-type P-type channel region 6 jointly reduce the gate-drain capacitance of the device, optimize the switching capacity of the device, enable the device to have higher switching speed and lower switching loss, improve the working capacity of the device under high frequency, and in addition, when the device is high-voltage resistant, the P-type JFET region 7, the Z-type P-type channel region 6 and the source groove can effectively relieve the phenomenon of electric field concentration in an oxide layer at the bottom of the channel, protect the reliability of the oxide layer, and simultaneously further improve the voltage-resistant capacity of the device due to the depletion effect caused by the thick oxide layer 8-4 at the bottom of the separation gate and the low-doped P-type JFET region 7;
The narrow-width and high-doped N-type injection region 9, the first separation gate 3-2 and the P-type JFET region 7 form a parasitic double-gate JFET structure, a narrow-width low-resistance conductive channel is formed at the parasitic double-gate JFET structure, the on-resistance of the device is reduced, the saturation current of the device is clamped, the short-circuit tolerance time of the device is effectively improved, the reliability of the device is improved, and the trade-off relation between the on-resistance and the short-circuit capacity in the SiC MOS device is greatly improved; the N-type injection region 9 is etched by a groove and then is finished through an inclined side wall ion injection process, and the process greatly reduces the requirement on the lithography precision while obtaining the N-type injection region 9 with narrow width and high doping; the narrow-width and high-doped N-type injection region 9 clamps the saturation current of the device while reducing the on-resistance of the device, and the reduction of the requirement on the lithography precision is beneficial to improving the yield and saving the cost.
Further, the N-type implantation region 9 below the trench gate structure is provided with a p+ shielding region 10, and the width of the p+ shielding region 10 is not smaller than the width of the trench gate structure and is not larger than the distance between two outer side surfaces of the N-type implantation region 9 at two sides of the trench gate structure.
Further, the n+ source region 4 extends into the p+ contact region 5, so that the p+ contact region 5 is spaced apart.
Further, the N-drift region 11 has P pillars 14 and N pillars 15 alternately arranged therein, so as to form a superjunction structure, and the superjunction structure may occupy a part of the drift region or may occupy the whole drift region.
Further, a second separation gate 3-3 is arranged in the top layer of the first separation gate 3-2, wherein the first separation gate 3-2 is N-type doped polysilicon, and the second separation gate 3-3 is P-type doped polysilicon.
Further, the second oxide layer 8-2 extends into the first separation gate 3-2, thereby forming the first separation gate 3-2 in a concave shape.
The beneficial effects of adopting the further scheme are as follows: the concave separation gate structure of the gate capacitance can be effectively reduced, the thickness of an oxidation layer between electrodes is increased, and the gate capacitance of the device is effectively reduced.
Further, the thickness of the third oxide layer 8-3 is not greater than the thickness of the fourth oxide layer 8-4.
The beneficial effects of adopting the further scheme are as follows: the concentration of the N-type implanted region 9 can be made higher, thereby reducing the on-resistance of the device and improving the forward on-characteristic.
Further, the control gate 3-1 and the first split gate 3-2 are metal gate electrodes or polysilicon gate electrodes.
Further, the source metal 1 is selected from one of titanium, nickel, copper and aluminum or a multi-layer combination of the above metals.
Further, the semiconductor material used in the device is any one or more of SiC, silicon, germanium, gallium nitride and diamond.
In order to solve the above technical problems, the embodiment of the present invention provides a trench silicon carbide MOSFET, wherein the cell structure of the trench silicon carbide MOSFET includes a back drain metal 13, an n+ substrate 12, an N-drift region 11 and a source metal 1, which are sequentially stacked from bottom to top;
the top layer of the N-drift region 11 is provided with P-type channel regions 6 which are arranged at intervals, and the top layer of the N-drift region 11 between the P-type channel regions 6 which are arranged at intervals is provided with a trench gate structure; the top layer of the P-type channel region 6 is provided with an N+ source region 4 and a P+ contact region 5 which are arranged side by side and are in mutual contact with each other on the side surface, and the side surface of the N+ source region 4 is in contact with the side surface of the trench gate structure; the source metal 1 is located on the N+ source region 4, the P+ contact region 5 and the trench gate structure, and an insulating medium layer 2 is arranged between the source metal 1 and the trench gate structure;
the trench gate structure comprises a first separation gate 3-2, a second oxide layer 8-2 and a control gate 3-1 which are sequentially stacked from bottom to top, wherein the first separation gate 3-2 is in equipotential with source metal 1, the top of the control gate 3-1 is flush with the top of the trench, a first oxide layer 8-1 is arranged between the control gate 3-1 and the side wall of the trench, a third oxide layer 8-3 is arranged between the first separation gate 3-2 and the side wall of the trench, and a fourth oxide layer 8-4 is arranged between the first separation gate 3-2 and the bottom of the trench; the lower surface of the control gate 3-1 is lower than the lower surface of the P-type channel region 6, and the control gate 3-1, the first oxide layer 8-1 and the P-type channel region 6 form a MOS structure;
A P-type JFET region 7 is arranged in the top layer of the N-drift region 11 below the P-type channel region 6, the doping concentration of the P-type JFET region 7 is lower than that of the P-type channel region 6, the lower surface of the P-type JFET region 7 is lower than that of the trench gate structure, an N-type injection region 9 is arranged between the P-type JFET region 7 and the trench gate structure, the upper surface of the N-type injection region 9 is flush with the upper surface of the P-type JFET region 7, the lower surface of the N-type injection region 9 is lower than that of the trench gate structure, the N-type injection region 9 is in an L-type package trench gate structure, and a parasitic double-gate JFET structure consisting of the P-type JFET region 7, the N-type injection region 9 and the first separation gate 3-2 is formed below the MOS structure; the saturation current of the parasitic double-gate JFET structure is lower than the saturation current of the MOS structure.
The working principle of the invention is as follows:
the invention effectively shields the coupling between the grid and the drain by introducing the first separation grid 3-2 and the P-type JFET region 7, reduces the grid drain capacitance and improves the working capacity of the device under high frequency. Meanwhile, under the dual actions of the P-type JFET region 7 and the first separation gate 3-2, a parasitic double-gate JFET structure connected in series with the trench MOS structure is formed at the introduced narrow-width and high-doped N-type injection region 9. Thanks to the N-type implanted region 9 of higher concentration, the on-resistance of the device is greatly improved at this point, and the saturation current of the parasitic double gate JFET structure is lower than that of the MOS structure.
When the device is in a normal working state, due to the existence of the parasitic double-gate JFET structure, only an electron conduction path of an N-type injection region 9 exists between an N-drift region 11 and a P-type channel region 6, and at the moment, due to the fact that the potential of the drift region under the N-type injection region 9 is lower and the concentration of the N-type injection region 9 is higher, the bilateral depletion effect of the first separation gate 3-2 and the P-type JFET region 7 on the N-type injection region 9 is weaker, the on-resistance of the device at the position is greatly improved, and the forward conduction loss of the device is greatly improved.
When the device is short-circuited, the potential of the drift region under the N-type injection region 9 will rise rapidly, at this time, the bilateral depletion effect of the first split gate 3-2 and the P-type JFET region 7 on the N-type injection region 9 increases rapidly, the N-type injection region 9 is greatly depleted, its ability as a conductive path will be further limited, and the saturation current of the parasitic JFET structure will clamp the rapidly increased current of the whole device, thereby achieving the purpose of improving the short-circuit tolerance of the device.
When the device works in a forward blocking state, a depletion layer generated between the P-type JFET region 7 and the N-drift region 11 has a double protection effect on an oxide layer at the corner of the trench; the depletion effect caused by the thick oxide layer 8-4 at the bottom of the separation gate and the low-doped P-type JFET region 7 further improves the voltage withstand capability of the device.
In particular, the N-type implantation region 9 designed by the invention is etched by the trench and then is completed by the inclined side wall ion implantation process, and the process can greatly reduce the requirement on the lithography precision while obtaining the N-type implantation region 9 with narrow width and high doping, thereby being beneficial to improving the yield and saving the cost.
The beneficial effects of the invention are as follows:
the first separation gate 3-2 and the P-type JFET region 7 in the invention jointly reduce the gate-drain capacitance of the device, optimize the switching capacity of the device, enable the device to have higher switching speed and lower switching loss, improve the working capacity of the device under high frequency, and in addition, when the device is high-voltage resistant, the P-type JFET region 7 can effectively relieve the electric field concentration phenomenon in an oxide layer at the bottom of a channel, protect the reliability of the oxide layer, and simultaneously further improve the withstand voltage capacity of the device due to the depletion effect caused by the thick oxide layer 8-4 at the bottom of the separation gate and the low-doped P-type JFET region 7;
the narrow-width and high-doped N-type injection region 9, the first separation gate 3-2 and the P-type JFET region 7 form a parasitic double-gate JFET structure, a narrow-width low-resistance conductive channel is formed at the parasitic double-gate JFET structure, the on-resistance of the device is reduced, the saturation current of the device is clamped, the short-circuit tolerance time of the device is effectively improved, the reliability of the device is improved, and the trade-off relation between the on-resistance and the short-circuit capacity in the SiC MOS device is greatly improved; the N-type injection region 9 is etched by a groove and then is finished through an inclined side wall ion injection process, and the process greatly reduces the requirement on the lithography precision while obtaining the N-type injection region 9 with narrow width and high doping; the narrow-width and high-doped N-type injection region 9 clamps the saturation current of the device while reducing the on-resistance of the device, and the reduction of the requirement on the lithography precision is beneficial to improving the yield and saving the cost.
The separation gate and the N-type injection region introduced by the invention well solve the problem that the threshold voltage at the bottom corner of the trench is uncontrollable after the trench is covered by the conventional P-type region.
Further, the N-type implantation region 9 wraps the bottom of the trench gate structure, so that the N-type implantation region 9 is concave.
The beneficial effects of adopting the further scheme are as follows: the process can be simplified by making the recess by a single step ion implantation.
Further, the n+ source region 4 extends into the p+ contact region 5, so that the p+ contact region 5 is spaced apart.
Further, the N-drift region 11 has P pillars 14 and N pillars 15 alternately arranged therein, so as to form a superjunction structure, and the superjunction structure may occupy a part of the drift region or may occupy the whole drift region.
Further, a second separation gate 3-3 is arranged in the top layer of the first separation gate 3-2, wherein the first separation gate 3-2 is N-type doped polysilicon, and the second separation gate 3-3 is P-type doped polysilicon.
Further, the second oxide layer 8-2 extends into the first separation gate 3-2, thereby forming the first separation gate 3-2 in a concave shape.
The beneficial effects of adopting the further scheme are as follows: the concave separation gate structure of the gate capacitance can be effectively reduced, the thickness of an oxidation layer between electrodes is increased, and the gate capacitance of the device is effectively reduced.
Further, the thickness of the third oxide layer 8-3 is not greater than the thickness of the fourth oxide layer 8-4.
The beneficial effects of adopting the further scheme are as follows: the concentration of the N-type implanted region 9 can be made higher, thereby reducing the on-resistance of the device and improving the forward on-characteristic.
Further, the control gate 3-1 and the first split gate 3-2 are metal gate electrodes or polysilicon gate electrodes.
Further, the source metal 1 is selected from one of titanium, nickel, copper and aluminum or a multi-layer combination of the above metals.
Further, the semiconductor material used in the device is any one or more of SiC, silicon, germanium, gallium nitride and diamond.
In order to solve the technical problems, the embodiment of the invention provides a manufacturing method of a trench silicon carbide MOSFET, which comprises the following steps:
step 1: an N-type heavily doped SiC piece is selected as an N+ substrate 12 of the device, and an epitaxial process is adopted to form an N-drift region 11 on the N-type heavily doped SiC piece;
step 2: forming a P-type JFET region 7 of the device through multiple ion implantation and annealing processes;
step 3: forming a P-type channel region 6 of the device through multiple ion implantation and annealing processes;
step 4: forming an N+ source region 4 and a P+ contact region 5 of the device by adopting a photoetching process and performing ion implantation and annealing processes for a plurality of times;
Step 5: forming a groove through an etching process, and forming an N-type injection region 9 at the bottom of the groove through multiple ion injection;
step 6: forming a P+ shielding region 10 at the bottom of the groove through a plurality of ion implantation processes, wherein the junction depth of the P+ shielding region 10 is larger than that of the N-type implantation region 9;
step 7: generating an oxide layer at the bottom and the side wall of the groove and the surface of the drift region, and filling polysilicon in the groove;
step 8: etching part of the polysilicon and part of the oxide layer through an etching process to form a first separation gate 3-2 and a third oxide layer 8-3;
step 9: forming an oxide layer on the top of the separation gate and the side wall of the groove through a deposition and etching process, and filling polysilicon in the groove to form a control gate 3-1;
step 10: performing leveling treatment on the surface of the device, and then depositing to form a dielectric layer 2;
step 11: metal is deposited on the front surface of the device to form a metal source electrode 1, a SiC sheet is turned over, metal is deposited on the back surface of the SiC sheet, and a back drain electrode metal 13 is formed on the lower surface of an N+ substrate 12.
In order to solve the technical problems, the embodiment of the invention provides a manufacturing method of a trench silicon carbide MOSFET, which comprises the following steps:
step 1: an N-type heavily doped SiC piece is selected as an N+ substrate 12 of the device, and an epitaxial process is adopted to form an N-drift region 11 on the N-type heavily doped SiC piece;
Step 2: forming a P-type JFET region 7 of the device through multiple ion implantation and annealing processes;
step 3: forming a part of the P-type channel region 6 of the device through multiple ion implantation and annealing processes;
step 4: forming an N+ source region 4 of the device by adopting a photoetching process and performing ion implantation and annealing processes for a plurality of times;
step 5: forming a gate trench and a source trench through an etching process, forming an N-type injection region 9 at the bottom of the gate trench and forming another part of a P-type channel region 6 at the bottom of the source trench through a plurality of ion injection processes, and obtaining a Z-type P-type channel region 6;
step 6: forming a P+ contact region 5 at the bottom of the source electrode groove by adopting a photoetching process and carrying out ion implantation and annealing processes for a plurality of times;
step 7: generating an oxide layer at the bottom and the side wall of the groove and on the surface of the drift region, and filling polysilicon in the gate groove;
step 8: etching part of the polysilicon and the oxide layer through an etching process to form a first separation gate 3-2 and a third oxide layer 8-3;
step 9: forming an oxide layer on the top of the separation gate and the side wall of the gate groove through a deposition and etching process, and filling polysilicon in the groove to form a control gate 3-1;
step 10: performing leveling treatment on the surface of the device, and then depositing to form a dielectric layer 2;
Step 11: depositing metal on the front surface of the device to form a metal source electrode 1, turning over the SiC piece, depositing metal on the back surface of the SiC piece, and forming a back drain electrode metal 13 on the lower surface of the N+ substrate.
In order to solve the technical problems, the embodiment of the invention provides a manufacturing method of a trench silicon carbide MOSFET, which comprises the following steps:
step 1: an N-type heavily doped SiC piece is selected as an N+ substrate 12 of the device, and an epitaxial process is adopted to form an N-drift region 11 on the N-type heavily doped SiC piece;
step 2: forming a P-type JFET region 7 of the device through ion implantation and annealing processes;
step 3: forming a P-type channel region 6 of the device by adopting a photoetching process and an ion implantation and annealing process;
step 4: forming an N+ source region 4 and a P+ contact region 5 of the device by adopting a photoetching process and an ion implantation and annealing process;
step 5: forming a groove through an etching process, and forming an N-type injection region 9 at the bottom of the groove through multiple ion injection;
step 6: generating an oxide layer at the bottom and the side wall of the groove and the surface of the drift region, and filling polysilicon in the groove;
step 7: etching part of the polysilicon and part of the oxide layer through an etching process to form a first separation gate 3-2 and a third oxide layer 8-3;
Step 8: forming an oxide layer on the top of the separation gate and the side wall of the groove through a deposition and etching process, and filling polysilicon in the groove to form a control gate 3-1;
step 9: performing leveling treatment on the surface of the device, and then depositing to form a dielectric layer 2;
step 10: metal is deposited on the front surface of the device to form a metal source electrode 1, a SiC sheet is turned over, metal is deposited on the back surface of the SiC sheet, and a back drain electrode metal 13 is formed on the lower surface of an N+ substrate 12.
Drawings
FIG. 1 is a schematic diagram of a cell structure of a conventional trench MOS;
FIG. 2 is a schematic diagram of a cell structure of a trench silicon carbide MOSFET according to a first embodiment of the present invention;
FIG. 3 is a schematic diagram of a cell structure of a trench silicon carbide MOSFET according to a second embodiment of the present invention;
FIG. 4 is a schematic diagram of a cell structure of a trench silicon carbide MOSFET according to a third embodiment of the present invention;
FIG. 5 is a schematic cross-sectional view of a cell structure of a trench silicon carbide MOSFET according to a fourth embodiment of the present invention, cut along the AA' direction in the structure shown in FIG. 2;
FIG. 6 is a schematic diagram of a cell structure of a trench silicon carbide MOSFET according to a fifth embodiment of the present invention;
FIG. 7 is a schematic diagram of a cell structure of a trench silicon carbide MOSFET according to a sixth embodiment of the present invention;
FIG. 8 is a schematic cell structure of a trench silicon carbide MOSFET according to a seventh embodiment of the present invention;
FIG. 9 is a schematic diagram of a cell structure of a trench silicon carbide MOSFET according to an eighth embodiment of the present invention;
FIG. 10 is a schematic cell structure of a trench silicon carbide MOSFET according to a ninth embodiment of the present invention;
FIG. 11 is a schematic diagram of a cell structure of a trench silicon carbide MOSFET according to a tenth embodiment of the present invention;
FIG. 12 is a schematic cell structure of a trench silicon carbide MOSFET according to an eleventh embodiment of the present invention;
fig. 13-23 are process flow diagrams of a method for fabricating a trench silicon carbide MOSFET according to a first embodiment of the invention;
fig. 24-34 are process flow diagrams of a method for fabricating a trench silicon carbide MOSFET according to a second embodiment of the invention;
fig. 35-44 are process flow diagrams of a method for fabricating a trench silicon carbide MOSFET according to a tenth embodiment of the invention.
In the drawings, the list of components represented by the various numbers is as follows:
1 is source metal, 2 is a dielectric layer, 3-1 is a control gate, 3-2 is a first separation gate, 3-3 is a second separation gate, 4 is an N+ source region, 5 is a P+ contact region, 6 is a P-type channel region, 7 is a P-type JFET region, 8-1 is a first oxide layer, 8-2 is a second oxide layer, 8-3 is a third oxide layer, 8-4 is a fourth oxide layer, 9 is an N-type injection region, 10 is a P+ shielding region, 11 is an N-drift region, 12 is an N+ substrate, 13 is a back drain metal, 14 is a P column, and 15 is an N column.
Detailed Description
The principles and features of the present invention are described below with reference to the drawings, the examples are illustrated for the purpose of illustrating the invention and are not to be construed as limiting the scope of the invention.
As shown in fig. 2, a trench silicon carbide MOSFET according to a first embodiment of the present invention has a cell structure including a back drain metal 13, an n+ substrate 12, an N-drift region 11, and a source metal 1 stacked in this order from bottom to top;
the top layer of the N-drift region 11 is provided with P-type JFET regions 7 which are arranged at intervals, and the top layer of the N-drift region 11 between the P-type JFET regions 7 which are arranged at intervals is provided with a trench gate structure; a P-type channel region 6 is arranged in the top layer of the low-doped P-type JFET region 7, an N+ source region 4 and a p+ contact region 5 which are arranged side by side and are in side contact with each other are arranged in the top layer of the P-type channel region 6, and the side surface of the N+ source region 4 is in contact with the side surface of the trench gate structure; the source metal 1 is located on the N+ source region 4, the P+ contact region 5 and the trench gate structure, and an insulating medium layer 2 is arranged between the source metal 1 and the trench gate structure; the doping concentration of the P-type JFET region 7 is lower than that of the P-type channel region 6, wherein the doping concentration of the P-type channel region 6 is set between 5e16 cm and 5e17 cm -3 Between them;
the trench gate structure comprises a first separation gate 3-2, a second oxide layer 8-2 and a control gate 3-1 which are sequentially stacked from bottom to top, wherein the first separation gate 3-2 is in equipotential with source metal 1, the top of the control gate 3-1 is flush with the top of the trench, a first oxide layer 8-1 is arranged between the control gate 3-1 and the side wall of the trench, a third oxide layer 8-3 is arranged between the first separation gate 3-2 and the side wall of the trench, and a fourth oxide layer 8-4 is arranged between the first separation gate 3-2 and the bottom of the trench; the lower surface of the control gate 3-1 is lower than the lower surface of the P-type channel region 6, the lower surface of the P-type JFET region 7 is not lower than the lower surface of the trench gate structure and is not higher than the lower surface of the first separation gate 3-2, and the control gate 3-1, the first oxide layer 8-1 and the P-type channel region 6 form a MOS structure;
a P+ shielding region 10 is arranged in the N-drift region 11 below the trench gate structure; an N-type injection region 9 with a narrow width and high doping is arranged between the P-type JFET region 7 and the trench gate structure, the width of the N-type injection region 9 is not more than 1/4 of the width of the P-type JFET region 7, and the concentration is not less than 1e17 cm -3 The upper surface of the N-type injection region 9 is flush with the upper surface of the P-type JFET region 7, and the lower surface of the N-type injection region 9 is not higher than the lower surface of the trench gate structure, thereby forming a parasitic double gate JFET structure consisting of the P-type JFET region 7, the N-type injection region 9, and the first split gate 3-2 under the MOS structure.
The parasitic double-gate JFET structure is provided with a narrow-width low-resistance conductive path due to the N-type injection region 9 with higher concentration, so that the on-resistance of the device is greatly improved, and the saturation current of the parasitic double-gate JFET structure is lower than that of the MOS structure, thereby achieving the purpose of improving the short-circuit tolerance of the device.
In the above embodiment, siC is selected as the semiconductor material used for the device. In addition, the semiconductor material used in the device may be any one or more of SiC, si, ge, gaN, diamond and gallium oxide.
Optionally, the doping concentration of the P-type JFET region 7 is not more than 1e17 cm -3 ；
Optionally, the width of the p+ shielding region 10 is not smaller than the width of the trench gate structure, two ends of the p+ shielding region 10 do not exceed the outer side surfaces of the N-type injection regions 9 at two sides of the trench gate structure, and the junction depth of the p+ shielding region 10 is not smaller than the junction depth of the N-type injection regions 9.
The above embodiment can ensure that the p+ shielding region 10 does not affect the conduction capability of the device while protecting the oxide layer at the bottom of the trench.
As shown in fig. 3, a trench silicon carbide MOSFET according to a second embodiment of the present invention has a cell structure including a back drain metal 13, an n+ substrate 12, an N-drift region 11, and a source metal 1 stacked in this order from bottom to top;
A trench gate structure is arranged in the top layer of the N-drift region 11, source trench structures are arranged on two sides of the trench gate structure, the junction depth of the source trench structure is not smaller than that of the trench gate structure, a P-type channel region 6 is arranged in the top layer of the N-drift region 11 between the trench gate structure and the source trench structure, the P-type channel region 6 extends into the N-drift region 11 under the source trench structure to form a Z-type P-type channel region 6, an N+ source region 4 is arranged on the top layer of the P-type channel region 6 between the trench gate structure and the source trench structure, and a p+ contact region 5 is arranged on the top layer of the P-type channel region 6 under the source trench structure; the source metal 1 is located on the N+ source region 4 and the trench gate structure, the source metal 1 fills the source trench structure, and an insulating medium layer 2 is arranged between the source metal 1 and the trench gate structure; the top layer of the N-drift region 11 below the P-type channel region 6 is provided with a P-type JFET region 7, the doping concentration of the low doped P-type JFET region 7 is lower than that of the P-type channel region 6, wherein the doping concentration of the P-type channel region 6 is set between 5e16 cm and 5e17 cm -3 Between them; the method comprises the steps of carrying out a first treatment on the surface of the
The trench gate structure comprises a first separation gate 3-2, a second oxide layer 8-2 and a control gate 3-1 which are sequentially stacked from bottom to top, wherein the first separation gate 3-2 is in equipotential with source metal 1, the top of the control gate 3-1 is flush with the top of the trench, a first oxide layer 8-1 is arranged between the control gate 3-1 and the side wall of the trench, a third oxide layer 8-3 is arranged between the first separation gate 3-2 and the side wall of the trench, and a fourth oxide layer 8-4 is arranged between the first separation gate 3-2 and the bottom of the trench; the lower surface of the control gate 3-1 is lower than the lower surface of the P-type channel region 6 between the trench gate structure and the source trench structure, and the control gate 3-1, the first oxide layer 8-1 and the P-type channel region 6 between the trench gate structure and the source trench structure form a MOS structure; the lower surface of the P-type JFET region 7 is not lower than the lower surface of the trench gate structure and is not higher than the lower surface of the first separation gate 3-2;
the P-type JFET region 7 and the trench gate structure have a narrow-width and highly doped N-type injection region 9 therebetween, and the N-type injection region 9A width of not more than 1/4 of the width of the P-type JFET region 7 and a concentration of not less than 1e17 cm -3 The upper surface of the N-type injection region 9 is flush with the upper surface of the P-type JFET region 7, and the lower surface of the N-type injection region 9 is lower than the lower surface of the trench gate structure, thereby forming a parasitic double gate JFET structure consisting of the P-type JFET region 7, the N-type injection region 9, and the first split gate 3-2 under the MOS structure.
The parasitic double-gate JFET structure is provided with a narrow-width low-resistance conductive path due to the N-type injection region 9 with higher concentration, so that the on-resistance of the device is greatly improved, and the saturation current of the parasitic double-gate JFET structure is lower than that of the MOS structure, thereby achieving the purpose of improving the short-circuit tolerance of the device.
In the above embodiment, siC is selected as the semiconductor material used for the device. In addition, the semiconductor material used in the device may be any one or more of SiC, si, ge, gaN, diamond and gallium oxide.
Optionally, the doping concentration of the P-type JFET region 7 is not more than 1e17 cm -3 ；
As shown in fig. 4, in the trench silicon carbide MOSFET according to the third embodiment of the present invention, the p+ shielding region 10 is located below the N-type implantation region 9 on the basis of the first embodiment, and the distance between the p+ shielding region 10 and two outer side surfaces of the N-type implantation region 9 on two sides of the trench gate structure is the same.
The embodiment ensures that the strong electric field near the oxide layer is lower when the device is resistant to high voltage by widening the width of the P+ shielding region, and better protection of the oxide layer is realized.
As shown in fig. 5, a trench silicon carbide MOSFET according to a fourth embodiment of the present invention is provided, based on the first embodiment, in which the n+ source region 4 extends into the p+ contact region 5, so as to obtain the p+ contact regions 5 that are distributed at intervals.
In the embodiment, a part of the n+ source region 4 extends into the p+ contact region 5 at the top of the device, and the special source region reduces the space required for the source contact n+ source region 4, so that the device size can be reduced.
As shown in fig. 6, a trench silicon carbide MOSFET according to a fifth embodiment of the present invention is provided, based on the first embodiment, in which the N-drift region 11 has P pillars 14 and N pillars 15 alternately arranged, so as to form a superjunction structure.
In the above embodiment, when the device is voltage-resistant, the fully depleted P-pillars 14 and N-pillars 15 can greatly increase the breakdown voltage, and improve the trade-off relationship between MOS voltage-resistant and on.
As shown in fig. 7, a trench silicon carbide MOSFET according to a sixth embodiment of the present invention is provided, based on the first embodiment, with a second split gate 3-3 in the top layer of the first split gate 3-2.
In the above embodiment, the first separation gate 3-2 is N-type doped polysilicon, and the second separation gate 3-3 is P-type doped polysilicon. When the device works, the depletion layer generated between the two layers of polysilicon of the separation gate can effectively reduce the capacitance between the drain and the source, thereby reducing the output capacitance of the device.
As shown in fig. 8, a trench silicon carbide MOSFET according to a seventh embodiment of the present invention is provided, based on the first embodiment, by extending the second oxide layer 8-2 into the first split gate 3-2, thereby forming the first split gate 3-2 in a concave shape.
In the embodiment, the concave polysilicon separation gate can effectively reduce the gate capacitance and improve the high-frequency performance of the device.
As shown in fig. 9, in the trench silicon carbide MOSFET according to the eighth embodiment of the present invention, on the basis of the second embodiment, the N-type implantation region 9 under the trench gate structure is provided with a p+ shielding region 10, where the width of the p+ shielding region 10 is not smaller than the width of the trench gate structure and is not larger than the distance between two outer sides of the N-type implantation region 9 on both sides of the trench gate structure.
The embodiment can better protect the oxide layer, can shield the coupling between grid and drain, and improve the high-frequency characteristic of the device.
As shown in fig. 10, a trench silicon carbide MOSFET according to a ninth embodiment of the present invention is provided, in which P pillars 14 and N pillars 15 are alternately arranged in the N-drift region 11 on the basis of the eighth embodiment, so as to form a superjunction structure.
In the above embodiment, when the device is voltage-resistant, the fully depleted P-pillars 14 and N-pillars 15 can greatly increase the breakdown voltage, and improve the trade-off relationship between MOS voltage-resistant and on.
Optionally, the thickness of the third oxide layer 8-3 is not greater than the thickness of the fourth oxide layer 8-4.
In the above embodiment, the thick fourth oxide layer 8-4 can better protect the reliability of the oxide layer at the bottom of the trench, and the thin third oxide layer 8-3 can enhance the control capability of the electrode on the N-type injection region 9, thereby obtaining the N-type injection region 9 with higher concentration and improving the conduction capability of the device.
Alternatively, the control gate 3-1 and the first split gate 3-2 are metal gate electrodes or polysilicon gate electrodes.
Alternatively, the source metal 1 is selected from one of titanium, nickel, copper and aluminum or a multi-layer combination of the foregoing metals.
As shown in fig. 11, a trench silicon carbide MOSFET according to a tenth embodiment of the present invention has a cell structure including a back drain metal 13, an n+ substrate 12, an N-drift region 11, and a source metal 1 stacked in this order from bottom to top;
the top layer of the N-drift region 11 is provided with P-type channel regions 6 which are arranged at intervals, and the top layer of the N-drift region 11 between the P-type channel regions 6 which are arranged at intervals is provided with a trench gate structure; the top layer of the P-type channel region 6 is provided with an N+ source region 4 and a P+ contact region 5 which are arranged side by side and are in mutual contact with each other on the side surface, and the side surface of the N+ source region 4 is in contact with the side surface of the trench gate structure; the source metal 1 is located on the N+ source region 4, the P+ contact region 5 and the trench gate structure, and an insulating medium layer 2 is arranged between the source metal 1 and the trench gate structure;
the trench gate structure comprises a first separation gate 3-2, a second oxide layer 8-2 and a control gate 3-1 which are sequentially stacked from bottom to top, wherein the first separation gate 3-2 is in equipotential with source metal 1, the top of the control gate 3-1 is flush with the top of the trench, a first oxide layer 8-1 is arranged between the control gate 3-1 and the side wall of the trench, a third oxide layer 8-3 is arranged between the first separation gate 3-2 and the side wall of the trench, and a fourth oxide layer 8-4 is arranged between the first separation gate 3-2 and the bottom of the trench; the lower surface of the control gate 3-1 is lower than the lower surface of the P-type channel region 6, and the control gate 3-1, the first oxide layer 8-1 and the P-type channel region 6 form a MOS structure;
A low doped P-type JFET region 7 is provided in the top layer of the N-drift region 11 below the P-type channel region 6, the P-type JFET region 7 having a lower doping concentration than the P-type channel region 6, wherein the doping concentration of the P-type channel region 6 is set at 5e16-5e17 cm -3 The lower surface of the P-type JFET region 7 is lower than the lower surface of the trench gate structure, an N-type injection region 9 with narrow width and high doping is arranged between the P-type JFET region 7 and the trench gate structure, the width of the N-type injection region 9 is not more than 1/4 of the width of the P-type JFET region 7 and the concentration is not less than 1e17cm -3 The upper surface of the N-type injection region 9 is flush with the upper surface of the P-type JFET region 7, the lower surface of the N-type injection region 9 is lower than the lower surface of the trench gate structure, and the N-type injection region 9 is in an L-type package trench gate structure bottom angle, so that a parasitic double-gate JFET structure consisting of the P-type JFET region 7, the N-type injection region 9 and the first separation gate 3-2 is formed below the MOS structure; the parasitic double-gate JFET structure is provided with a narrow-width low-resistance conductive path due to the N-type injection region 9 with higher concentration, so that the on-resistance of the device is greatly improved, and the saturation current of the parasitic double-gate JFET structure is lower than that of the MOS structure, thereby achieving the purpose of improving the short-circuit tolerance of the device.
In the above embodiment, siC is selected as the semiconductor material used for the device. In addition, the semiconductor material used in the device may be any one or more of SiC, si, ge, gaN, diamond and gallium oxide.
Optionally, the doping concentration of the P-type JFET region 7 is not more than 1e17 cm -3 ；
As shown in fig. 12, in the trench silicon carbide MOSFET according to the eleventh embodiment of the present invention, the bottom of the trench gate structure is wrapped by the N-type implantation region 9 on the basis of the tenth embodiment, so as to obtain a concave N-type implantation region 9.
In the above embodiment, the concave N-type implantation region 9 is formed by single-step ion implantation, so that the on-resistance of the device can be reduced, and the process steps can be simplified.
As shown in fig. 13-23, a method for manufacturing a trench silicon carbide MOSFET according to a first embodiment of the present invention includes the steps of:
step 1: an N-type heavily doped SiC piece with certain thickness and concentration is selected as an N+ substrate 12 of the device, and an N-drift region 11 with certain thickness is epitaxially grown on the surface of the substrate;
step 2: the P-type JFET region 7 of the device is formed by multiple ion implantation and annealing processes with an implantation energy of about 500 keV-2 MeV and a dose of about 10 11 cm -3 ～10 14 cm -3 ；
Step 3: the P-type channel region 6 of the device is formed by multiple ion implantation and annealing processes with an implantation energy of about 20keV to about 450keV and a dose of about 10 11 cm -3 ～10 13 cm -3 ；
Step 4: the N+ source region 4 and the P+ contact region 5 of the device are formed by photoetching, multiple ion implantation and annealing processes, the implantation energy is about 10 keV-100 keV, and the dosage is about 10 13 cm -3 ～10 16 cm -3 ；
Step 5: etching to form a trench structure, and forming an N-type implantation region 9 at the bottom of the trench by multiple ion implantation with implantation energy of about 0 keV-200 keV and dosage of about 10 11 cm -3 ～10 13 cm -3 ；
Step 6: p+ shielding region 10 with the same width as the trench is formed at the bottom of the trench by multiple ion implantation and annealing processes, the junction depth is deeper than that of N-type implantation region 9, the implantation energy is about 50-250 keV, and the dosage is about 10 13 cm -3 ～10 16 cm -3 ；
Step 7: generating oxide layers 8-3 and 8-4 on the bottom and the side wall of the groove and the surface of the drift region, and filling polysilicon 3-2 in the groove;
step 8: etching part of the polysilicon 3-2 and the oxide layer 8-3 by etching to form a first separation gate 3-2 and the oxide layer 8-3;
step 9: forming oxide layers 8-1 and 8-2 on the top of the separation gate and the side wall of the groove through a deposition and etching process, and filling polysilicon 3-1 in the groove to form a control gate 3-1;
step 10: performing leveling treatment on the surface, and then depositing to form a dielectric layer 2;
step 11: metal is deposited on the front surface of the device to form a metal source electrode 1, a SiC sheet is turned over, metal is deposited on the back surface of the SiC sheet, and a metal drain electrode 13 is formed on the lower surface of an N+ substrate 12.
As shown in fig. 24-34, a method for manufacturing a trench silicon carbide MOSFET according to a second embodiment of the present invention includes the steps of:
step 1: an N-type heavily doped SiC piece with certain thickness and concentration is selected as an N+ substrate 12 of the device, and an N-drift region 11 with certain thickness is epitaxially grown on the surface of the substrate;
step 2: the P-type JFET region 7 of the device is formed by photolithography, multiple ion implantation and annealing processes, the implantation energy is about 500 keV-2 MeV, and the dose is about 10 11 cm -3 ～10 14 cm -3 ；
Step 3: the upper half of the P-type channel region 6 of the device is formed by photolithography, multiple ion implantation and annealing processes with an implantation energy of about 20keV to 450keV and a dose of about 10 11 cm -3 ～10 13 cm -3 ；
Step 4: the N+ source region 4 of the device is formed by photolithography, multiple ion implantation and annealing processes with an implantation energy of about 10keV to 100keV and a dose of about 10 13 cm -3 ～10 16 cm -3 ；
Step 5: etching to form a double-trench structure, forming an N-type injection region 9 at the bottom of the gate trench and forming the lower half part of the P-type channel region 6 at the bottom of the source trench by multiple ion injection, wherein the injection energy of the N-type injection region 9 is about 10 keV-100 keV, and the dosage is about 10 13 cm -3 ～10 16 cm -3 ；
Step 6: p+ contact region 5 is formed at the bottom of the source trench by photolithography, multiple ion implantation and annealing processes, the implantation energy is about 10 keV-100 keV, and the dose is about 10 13 cm -3 ～10 16 cm -3 ；
Step 7: generating oxide layers 8-3 and 8-4 on the bottom and the side wall of the groove and the surface of the drift region, and filling polysilicon 3-2 in the groove;
step 8: etching part of the polysilicon 3-2 and the oxide layer 8-3 by etching to form a separation gate 3-2 and the oxide layer 8-3;
step 9: forming oxide layers 8-1 and 8-2 on the top of the separation gate and the side wall of the groove through a deposition and etching process, and filling polysilicon 3-1 in the groove to form a control gate 3-1;
step 10: performing leveling treatment on the surface, and then depositing to form a dielectric layer 2;
step 11: depositing metal on the front surface of the device to form a metal source electrode 1, turning over the SiC piece, depositing metal on the back surface of the SiC piece, and forming a metal drain electrode 13 on the lower surface of the N+ substrate.
As shown in fig. 35-44, a method for manufacturing a trench silicon carbide MOSFET according to a tenth embodiment of the present invention includes the steps of:
step 1: an N-type heavily doped SiC piece with certain thickness and concentration is selected as an N+ substrate 12 of the device, and an N-drift region 11 with certain thickness is epitaxially grown on the surface of the substrate;
step 2: the P-type JFET region 7 of the device is formed by ion implantation and annealing at an energy of about 500keV to 2MeV at a dose of about 10 11 cm -3 ～10 14 cm -3 ；
Step 3: the P-type channel region 6 of the device is formed by photolithography, ion implantation and annealing processes with an implantation energy of about 20keV to about 450keV and a dose of about 10 11 cm -3 ～10 13 cm -3 ；
Step 4: the N+ source region 4 and the P+ contact region 5 of the device are formed by photolithography, ion implantation and annealing processes, the implantation energy is about 10keV to 100keV, and the dose is about 10 13 cm -3 ～10 16 cm -3 ；
Step 5: etching to form a trench structure, forming L-shaped N-type injection regions 9 at two bottom corners of the trench by inclined ion injection, wherein the injection energy is about 10-100 keV,at a dose of about 10 13 cm -3 ～10 16 cm -3 ；
Step 6: generating oxide layers 8-3 and 8-4 on the bottom and the side wall of the groove and the surface of the drift region, and filling polysilicon 3-2 in the groove;
step 7: etching part of the polysilicon 3-2 and the oxide layer 8-3 by etching to form a separation gate 3-2 and the oxide layer 8-3;
step 8: forming oxide layers 8-1 and 8-2 on the top of the separation gate and the side wall of the groove through a deposition and etching process, and filling polysilicon 3-1 in the groove to form a control gate 3-1;
step 9: the surface is subjected to leveling treatment and then deposited to form a dielectric layer 2;
step 10: metal is deposited on the front surface of the device to form a metal source electrode 1, a SiC sheet is turned over, metal is deposited on the back surface of the SiC sheet, and a metal drain electrode 13 is formed on the lower surface of an N+ substrate 12.
The trench gate structure in the trench type silicon carbide MOSFET provided by the invention is divided into the control gate and the separation gate, a P+ shielding region is arranged below the trench gate structure, and the P+ shielding region can relieve the phenomenon of electric field concentration, protect an oxide layer at the corner of the trench structure, play a role in shielding the coupling between gate and drain as the separation gate, reduce the switching loss of a device and improve the switching speed. In addition, the isolation gate structure, the N-type injection region and the P-type JFET region of the trench silicon carbide MOSFET provided by the invention form a JFET structure at the side wall of the trench, and when the MOSFET is normally conducted, the JFET structure provides a conductive path on the side wall of the trench for electrons, and when the drain voltage is higher, the N-type injection region is pinched off, so that the purposes of reducing the saturation current of a device and improving the short circuit tolerance of the device are achieved.
In addition, in order to further improve the reliability of an oxide layer while reducing the switching loss of the device and improving the short circuit tolerance of the device, the invention provides a second trench type silicon carbide MOSFET. The second trench type silicon carbide MOSFET of the present invention has a double trench structure, which is divided into a gate trench in the middle and source trenches on both sides. The inner part of the grid electrode groove structure is divided into a control grid and a separation grid which is in short circuit with the source electrode; the source electrode groove is filled with source electrode metal, the bottom of the source electrode groove structure is covered by the Z-shaped P-type channel region, and the P-type channel region with deeper junction depth can relieve the phenomenon of electric field concentration and protect the oxide layer at the corner of the groove structure.
The invention provides a third groove type silicon carbide MOSFET which adopts a separation gate structure and simultaneously introduces a P type JFET region 7 near the bottom corner of a groove. The introduced P-type JFET region 7 and the separation gate structure shield the coupling between gate and drain electrodes, reduce the gate and drain capacitance of the device, improve the switching speed and reduce the switching loss. In addition, the introduced split gate and the N-type injection region well solve the problem that the threshold voltage at the bottom corner of the trench is uncontrollable after the conventional P-type region covers the trench. Meanwhile, the invention also forms a double-gate JFET structure below the channel by introducing a split gate structure, an N-type injection region 9 and a P-type JFET region 7. During normal conduction, the JFET structure provides a conductive path on the side wall of the groove for electrons, and when the drain voltage is higher, the N-type injection region 9 can be pinched off, so that the purposes of reducing the saturation current of the device and improving the short circuit tolerance of the device are achieved. The N-type injection region 9 designed by the invention is completed by an inclined ion injection process, the requirement on the lithography precision is not high, and the process threshold is reduced.
In the description of the present invention, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", "axial", "radial", "circumferential", etc. indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings are merely for convenience in describing the present invention and simplifying the description, and do not indicate or imply that the device or element being referred to must have a specific orientation, be configured and operated in a specific orientation, and therefore should not be construed as limiting the present invention.
Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include at least one such feature. In the description of the present invention, the meaning of "plurality" means at least two, for example, two, three, etc., unless specifically defined otherwise.
In the present invention, unless explicitly specified and limited otherwise, the terms "mounted," "connected," "secured," and the like are to be construed broadly, and may be, for example, fixedly connected, detachably connected, or integrally formed; can be mechanically or electrically connected; either directly or indirectly, through intermediaries, or both, may be in communication with each other or in interaction with each other, unless expressly defined otherwise. The specific meaning of the above terms in the present invention can be understood by those of ordinary skill in the art according to the specific circumstances.
In the present invention, unless expressly stated or limited otherwise, a first feature "up" or "down" a second feature may be the first and second features in direct contact, or the first and second features in indirect contact via an intervening medium. Moreover, a first feature being "above," "over" and "on" a second feature may be a first feature being directly above or obliquely above the second feature, or simply indicating that the first feature is level higher than the second feature. The first feature being "under", "below" and "beneath" the second feature may be the first feature being directly under or obliquely below the second feature, or simply indicating that the first feature is less level than the second feature.
In the description of the present specification, a description referring to terms "one embodiment," "some embodiments," "examples," "specific examples," or "some examples," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the present invention. In this specification, schematic representations of the above terms are not necessarily directed to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, the different embodiments or examples described in this specification and the features of the different embodiments or examples may be combined and combined by those skilled in the art without contradiction.
The foregoing description of the preferred embodiments of the invention is not intended to limit the invention to the precise form disclosed, and any such modifications, equivalents, and alternatives falling within the spirit and scope of the invention are intended to be included within the scope of the invention.

Claims (13)

1. The trench type silicon carbide MOSFET is characterized in that a cell structure comprises a back drain metal (13), an N+ substrate (12), an N-drift region (11) and a source metal (1) which are sequentially stacked from bottom to top;
The top layer of the N-drift region (11) is provided with P-type JFET regions (7) which are arranged at intervals, and the top layer of the N-drift region (11) between the P-type JFET regions (7) which are arranged at intervals is provided with a trench gate structure; the top layer of the P-type JFET region (7) is provided with a P-type channel region (6), the top layer of the P-type channel region (6) is provided with an N+ source region (4) and a P+ contact region (5) which are arranged side by side and are in side contact with each other, and the side surface of the N+ source region (4) is in contact with the side surface of the trench gate structure; the source metal (1) is positioned on the N+ source region (4), the P+ contact region (5) and the trench gate structure, and an insulating medium layer (2) is arranged between the source metal (1) and the trench gate structure; the doping concentration of the P-type JFET region (7) is lower than that of the P-type channel region (6);
the trench gate structure comprises a first separation gate (3-2), a second oxidation layer (8-2) and a control gate (3-1) which are sequentially stacked from bottom to top, wherein the first separation gate (3-2) is in equipotential with a source metal (1), the top of the control gate (3-1) is flush with the top of a trench, the first oxidation layer (8-1) is arranged between the control gate (3-1) and the side wall of the trench, a third oxidation layer (8-3) is arranged between the first separation gate (3-2) and the side wall of the trench, and a fourth oxidation layer (8-4) is arranged between the first separation gate (3-2) and the bottom of the trench; the lower surface of the control gate (3-1) is lower than the lower surface of the P-type channel region (6), the lower surface of the P-type JFET region (7) is not lower than the lower surface of the trench gate structure and is not higher than the lower surface of the first separation gate (3-2), and the control gate (3-1), the first oxide layer (8-1) and the P-type channel region (6) form a MOS structure;
A P+ shielding region (10) is arranged in the N-drift region (11) below the trench gate structure; an N-type injection region (9) is arranged between the P-type JFET region (7) and the trench gate structure, the upper surface of the N-type injection region (9) is flush with the upper surface of the P-type JFET region (7), and the lower surface of the N-type injection region (9) is not higher than the lower surface of the trench gate structure, so that a parasitic double-gate JFET structure consisting of the P-type JFET region (7), the N-type injection region (9) and the first separation gate (3-2) is formed below the MOS structure; the saturation current of the parasitic double-gate JFET structure is lower than the saturation current of the MOS structure.
2. A trench silicon carbide MOSFET according to claim 1, wherein the p+ shield region (10) is located below the N-type implanted region (9), and the p+ shield region (10) is equally wide with the spacing between the two outer sides of the N-type implanted region (9) on both sides of the trench gate structure.
3. The trench type silicon carbide MOSFET is characterized in that a cell structure comprises a back drain metal (13), an N+ substrate (12), an N-drift region (11) and a source metal (1) which are sequentially stacked from bottom to top;
a groove gate structure is arranged in the top layer of the N-drift region (11), source groove structures are arranged on two sides of the groove gate structure, the junction depth of the source groove structures is not smaller than that of the groove gate structures, a P-type channel region (6) is arranged in the top layer of the N-drift region (11) between the groove gate structures and the source groove structures, the P-type channel region (6) extends into the N-drift region (11) under the source groove structures to form a Z-type P-type channel region (6), an N+ source region (4) is arranged on the top layer of the P-type channel region (6) between the groove gate structures and the source groove structures, and a P+ contact region (5) is arranged on the top layer of the P-type channel region (6) under the source groove structures; the source metal (1) is positioned on the N+ source region (4) and the trench gate structure, the source metal (1) fills the source trench structure, and an insulating medium layer (2) is arranged between the source metal (1) and the trench gate structure; a P-type JFET region (7) is arranged in the top layer of the N-drift region (11) below the P-type channel region (6), and the doping concentration of the P-type JFET region (7) is lower than that of the P-type channel region (6);
The trench gate structure comprises a first separation gate (3-2), a second oxidation layer (8-2) and a control gate (3-1) which are sequentially stacked from bottom to top, wherein the first separation gate (3-2) is in equipotential with a source metal (1), the top of the control gate (3-1) is flush with the top of a trench, the first oxidation layer (8-1) is arranged between the control gate (3-1) and the side wall of the trench, a third oxidation layer (8-3) is arranged between the first separation gate (3-2) and the side wall of the trench, and a fourth oxidation layer (8-4) is arranged between the first separation gate (3-2) and the bottom of the trench; the lower surface of the control gate (3-1) is lower than the lower surface of the P-type channel region (6) between the trench gate structure and the source trench structure, and the control gate (3-1), the first oxide layer (8-1) and the P-type channel region (6) between the trench gate structure and the source trench structure form a MOS structure; the lower surface of the P-type JFET region (7) is not lower than the lower surface of the trench gate structure and is not higher than the lower surface of the first separation gate (3-2);
an N-type injection region (9) is arranged between the P-type JFET region (7) and the trench gate structure, the upper surface of the N-type injection region (9) is flush with the upper surface of the P-type JFET region (7), and the lower surface of the N-type injection region (9) is lower than the lower surface of the trench gate structure, so that a parasitic double-gate JFET structure consisting of the P-type JFET region (7), the N-type injection region (9) and the first separation gate (3-2) is formed below the MOS structure; the saturation current of the parasitic double-gate JFET structure is lower than the saturation current of the MOS structure.
4. A trench silicon carbide MOSFET according to claim 3 wherein the N-type implanted region (9) under the trench gate structure has a p+ shield region (10), the p+ shield region (10) having a width not smaller than the width of the trench gate structure and not larger than the spacing between the two outer sides of the N-type implanted region (9) on either side of the trench gate structure.
5. The trench type silicon carbide MOSFET is characterized in that a cell structure comprises a back drain metal (13), an N+ substrate (12), an N-drift region (11) and a source metal (1) which are sequentially stacked from bottom to top;
the top layer of the N-drift region (11) is provided with P-type channel regions (6) which are arranged at intervals, and the top layer of the N-drift region (11) between the P-type channel regions (6) which are arranged at intervals is provided with a trench gate structure; an N+ source region (4) and a P+ contact region (5) which are arranged side by side and are in side contact with each other are arranged in the top layer of the P-type channel region (6), and the side surface of the N+ source region (4) is in contact with the side surface of the trench gate structure; the source metal (1) is positioned on the N+ source region (4), the P+ contact region (5) and the trench gate structure, and an insulating medium layer (2) is arranged between the source metal (1) and the trench gate structure;
The trench gate structure comprises a first separation gate (3-2), a second oxidation layer (8-2) and a control gate (3-1) which are sequentially stacked from bottom to top, wherein the first separation gate (3-2) is in equipotential with a source metal (1), the top of the control gate (3-1) is flush with the top of a trench, the first oxidation layer (8-1) is arranged between the control gate (3-1) and the side wall of the trench, a third oxidation layer (8-3) is arranged between the first separation gate (3-2) and the side wall of the trench, and a fourth oxidation layer (8-4) is arranged between the first separation gate (3-2) and the bottom of the trench; the lower surface of the control gate (3-1) is lower than the lower surface of the P-type channel region (6), and the control gate (3-1), the first oxide layer (8-1) and the P-type channel region (6) form a MOS structure;
a P-type JFET region (7) is arranged in the top layer of the N-drift region (11) below the P-type channel region (6), the doping concentration of the P-type JFET region (7) is lower than that of the P-type channel region (6), the lower surface of the P-type JFET region (7) is lower than that of the trench gate structure, an N-type injection region (9) is arranged between the P-type JFET region (7) and the trench gate structure, the upper surface of the N-type injection region (9) is flush with the upper surface of the P-type JFET region (7), the lower surface of the N-type injection region (9) is lower than that of the trench gate structure, and the N-type injection region (9) is in an L-shaped bottom corner wrapping the trench gate structure, so that a parasitic double-gate structure consisting of the P-type JFET region (7), the N-type injection region (9) and the first separation gate (3-2) is formed below the MOS structure; the saturation current of the parasitic double-gate JFET structure is lower than the saturation current of the MOS structure.
6. A trench silicon carbide MOSFET according to claim 5 wherein the N-type implanted region (9) wraps around the bottom of the trench gate structure such that the N-type implanted region (9) is concave.
7. A trench silicon carbide MOSFET according to any of the claims 1-6, characterized in that the n+ source region (4) extends into the p+ contact region (5) such that the p+ contact regions (5) are spaced apart.
8. A trench silicon carbide MOSFET according to any of the claims 1-6, characterized in that the N-drift region (11) has alternating P-pillars 14 and N-pillars (15) therein, thereby forming a superjunction structure.
9. A trench silicon carbide MOSFET according to any of the claims 1-6 characterized in that the top layer of the first split gate (3-2) has a second split gate (3-3) in it.
10. A trench silicon carbide MOSFET according to any of the claims 1-6, characterized in that the second oxide layer (8-2) extends into the first split gate (3-2) forming a concave-shaped first split gate (3-2).
11. A method of fabricating a trench silicon carbide MOSFET according to any one of claims 1-2, comprising the steps of:
Step 1: an N-type heavily doped SiC sheet is selected as an N+ substrate (12) of the device, and an epitaxial process is adopted to form an N-drift region (11) on the N-type heavily doped SiC sheet;
step 2: forming a P-type JFET region (7) of the device through multiple ion implantation and annealing processes;
step 3: forming a P-type channel region (6) of the device through multiple ion implantation and annealing processes;
step 4: forming an N+ source region (4) and a P+ contact region (5) of the device by adopting a photoetching process and performing ion implantation and annealing processes for a plurality of times;
step 5: forming a groove through an etching process, and forming an N-type injection region (9) at the bottom of the groove through multiple ion injection;
step 6: forming a P+ shielding region (10) at the bottom of the groove through a plurality of ion implantation processes, wherein the junction depth of the P+ shielding region (10) is larger than that of the N-type implantation region (9);
step 7: generating an oxide layer at the bottom and the side wall of the groove and the surface of the drift region, and filling polysilicon in the groove;
step 8: etching part of the polysilicon and part of the oxide layer through an etching process to form a first separation gate (3-2) and a third oxide layer (8-3);
step 9: forming an oxide layer on the top of the separation gate and the side wall of the groove through a deposition and etching process, and filling polysilicon in the groove to form a control gate (3-1);
Step 10: performing leveling treatment on the surface of the device, and then depositing to form a dielectric layer (2);
step 11: depositing metal on the front surface of the device to form a metal source electrode 1, turning over a SiC sheet, depositing metal on the back surface of the SiC sheet, and forming a back drain metal (13) on the lower surface of an N+ substrate (12).
12. A method of fabricating a trench silicon carbide MOSFET according to any of claims 3-4 comprising the steps of:
step 1: an N-type heavily doped SiC sheet is selected as an N+ substrate (12) of the device, and an epitaxial process is adopted to form an N-drift region (11) on the N-type heavily doped SiC sheet;
step 2: forming a P-type JFET region (7) of the device through multiple ion implantation and annealing processes;
step 3: forming a part of P-type channel region (6) of the device through multiple ion implantation and annealing processes;
step 4: forming an N+ source region (4) of the device by adopting a photoetching process and performing ion implantation and annealing processes for a plurality of times;
step 5: forming a grid electrode groove and a source electrode groove through an etching process, forming an N-type injection region (9) at the bottom of the grid electrode groove and forming another part of a P-type channel region (6) at the bottom of the source electrode groove through a plurality of ion injection processes, and obtaining a Z-type P-type channel region (6);
step 6: forming a P+ contact region (5) at the bottom of the source electrode groove by adopting a photoetching process and carrying out ion implantation and annealing processes for a plurality of times;
Step 7: generating an oxide layer at the bottom and the side wall of the groove and on the surface of the drift region, and filling polysilicon in the gate groove;
step 8: etching part of the polysilicon and the oxide layer through an etching process to form a first separation gate (3-2) and a third oxide layer (8-3);
step 9: forming an oxide layer on the top of the separation gate and the side wall of the gate trench through a deposition and etching process, and filling polysilicon in the trench to form a control gate (3-1);
step 10: performing leveling treatment on the surface of the device, and then depositing to form a dielectric layer (2);
step 11: depositing metal on the front surface of the device to form a metal source electrode 1, turning over the SiC piece, depositing metal on the back surface of the SiC piece, and forming a back drain electrode metal (13) on the lower surface of the N+ substrate.
13. A method of fabricating a trench silicon carbide MOSFET according to any of claims 5-6 comprising the steps of:
step 1: an N-type heavily doped SiC sheet is selected as an N+ substrate (12) of the device, and an epitaxial process is adopted to form an N-drift region (11) on the N-type heavily doped SiC sheet;
step 2: forming a P-type JFET region (7) of the device through ion implantation and annealing processes;
step 3: forming a P-type channel region (6) of the device by adopting a photoetching process and an ion implantation and annealing process;
Step 4: forming an N+ source region (4) and a P+ contact region (5) of the device by adopting a photoetching process and an ion implantation and annealing process;
step 5: forming a groove through an etching process, and forming an N-type injection region (9) at the bottom of the groove through multiple ion injection;
step 6: generating an oxide layer at the bottom and the side wall of the groove and the surface of the drift region, and filling polysilicon in the groove;
step 7: etching part of the polysilicon and part of the oxide layer through an etching process to form a first separation gate (3-2) and a third oxide layer (8-3);
step 8: forming an oxide layer on the top of the separation gate and the side wall of the groove through a deposition and etching process, and filling polysilicon in the groove to form a control gate (3-1);
step 9: performing leveling treatment on the surface of the device, and then depositing to form a dielectric layer (2);
step 10: depositing metal on the front surface of the device to form a metal source electrode 1, turning over a SiC sheet, depositing metal on the back surface of the SiC sheet, and forming a back drain metal (13) on the lower surface of an N+ substrate (12).
CN202310615476.5A 2023-05-29 2023-05-29 Groove type silicon carbide MOSFET and manufacturing method thereof Pending CN116469916A (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117476746A (en) * 2023-12-27 2024-01-30 天狼芯半导体(成都)有限公司 Shielding gate trench MOS device, preparation method thereof and chip
CN117497568A (en) * 2023-12-27 2024-02-02 天狼芯半导体(成都)有限公司 SGTMOS device with left and right gate structures, preparation method thereof and chip

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117476746A (en) * 2023-12-27 2024-01-30 天狼芯半导体(成都)有限公司 Shielding gate trench MOS device, preparation method thereof and chip
CN117497568A (en) * 2023-12-27 2024-02-02 天狼芯半导体(成都)有限公司 SGTMOS device with left and right gate structures, preparation method thereof and chip
CN117497568B (en) * 2023-12-27 2024-04-19 天狼芯半导体(成都)有限公司 SGTMOS device with left and right gate structures, preparation method thereof and chip
CN117476746B (en) * 2023-12-27 2024-04-19 天狼芯半导体(成都)有限公司 Shielding gate trench MOS device, preparation method thereof and chip

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