CN114420745A - Silicon carbide MOSFET and preparation method thereof - Google Patents
Silicon carbide MOSFET and preparation method thereof Download PDFInfo
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- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 title claims abstract description 97
- 229910010271 silicon carbide Inorganic materials 0.000 title claims abstract description 97
- 238000002360 preparation method Methods 0.000 title claims abstract description 8
- 239000010410 layer Substances 0.000 claims description 356
- 238000005530 etching Methods 0.000 claims description 75
- 150000002500 ions Chemical class 0.000 claims description 60
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 50
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 50
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 40
- 229910052751 metal Inorganic materials 0.000 claims description 37
- 239000002184 metal Substances 0.000 claims description 37
- 238000000151 deposition Methods 0.000 claims description 29
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 23
- 239000000758 substrate Substances 0.000 claims description 23
- 230000000903 blocking effect Effects 0.000 claims description 20
- 238000000034 method Methods 0.000 claims description 19
- 238000002347 injection Methods 0.000 claims description 12
- 239000007924 injection Substances 0.000 claims description 12
- 235000012239 silicon dioxide Nutrition 0.000 claims description 11
- 239000000377 silicon dioxide Substances 0.000 claims description 11
- 230000004888 barrier function Effects 0.000 claims description 7
- 239000000463 material Substances 0.000 claims description 7
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims description 6
- 238000000137 annealing Methods 0.000 claims description 6
- 229910052799 carbon Inorganic materials 0.000 claims description 6
- 238000001312 dry etching Methods 0.000 claims description 4
- 239000007943 implant Substances 0.000 claims description 4
- 239000011241 protective layer Substances 0.000 claims description 2
- 229920005591 polysilicon Polymers 0.000 description 22
- 239000002019 doping agent Substances 0.000 description 21
- 238000002513 implantation Methods 0.000 description 15
- 238000010586 diagram Methods 0.000 description 12
- 229920002120 photoresistant polymer Polymers 0.000 description 10
- -1 aluminum ions Chemical class 0.000 description 9
- 230000005684 electric field Effects 0.000 description 9
- 230000008569 process Effects 0.000 description 7
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 4
- 239000000243 solution Substances 0.000 description 4
- 229910052782 aluminium Inorganic materials 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- 229910052796 boron Inorganic materials 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 229910052757 nitrogen Inorganic materials 0.000 description 2
- IJGRMHOSHXDMSA-UHFFFAOYSA-N nitrogen Substances N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- 230000002093 peripheral effect Effects 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- 230000003313 weakening effect Effects 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000000407 epitaxy Methods 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66053—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide
- H01L29/66068—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
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Abstract
The invention belongs to the technical field of power devices and provides a silicon carbide MOSFET and a preparation method thereof.
Description
Technical Field
The invention belongs to the technical field of power devices, and particularly relates to a silicon carbide MOSFET and a preparation method thereof.
Background
The silicon carbide MOSFET has the characteristic of high frequency and high power density, can greatly reduce the volume of a power supply and improve the conversion efficiency of the power supply as a power device, and therefore has wide application prospect.
The silicon carbide MOSFET mainly has two structures, namely a plane structure and a groove structure, and the current density of the plane silicon carbide MOSFET is lower than that of the groove silicon carbide MOSFET due to the low channel mobility of the plane silicon carbide MOSFET, however, in the existing groove structure silicon carbide MOSFET, the electric field intensity at the corner of the groove is high, the breakdown phenomenon easily occurs, and the stability of the groove structure silicon carbide MOSFET is greatly influenced.
Disclosure of Invention
The invention aims to provide a silicon carbide MOSFET and a preparation method thereof, and aims to solve the problem of poor stability of the existing silicon carbide MOSFET with a groove structure.
A first aspect of the present invention provides a silicon carbide MOSFET comprising:
a silicon carbide substrate;
the silicon carbide epitaxial layer and the silicon carbide substrate are both doped with first type doping ions, and the doping concentration of the silicon carbide epitaxial layer is smaller than that of the silicon carbide substrate;
the first well region is arranged in the deep groove on the upper surface of the silicon carbide epitaxial layer and comprises a first transverse well region and a first longitudinal well region, wherein the first transverse well region and the first longitudinal well region form a T-shaped structure doped with second type doped ions, and the doping concentration of the first transverse well region is greater than that of the first longitudinal well region;
the second well region is arranged on the silicon carbide epitaxial layer and comprises two second transverse well regions and a second longitudinal well region, wherein the two second transverse well regions are arranged on two sides of the second longitudinal well region, and the doping concentration of the second longitudinal well region is greater than that of the second transverse well region;
the first gate oxide layer and the second gate oxide layer are of concave structures and are respectively arranged on two sides of the first longitudinal well region;
the first polycrystalline silicon and the second polycrystalline silicon are respectively arranged in the concave regions of the first gate oxide layer and the second gate oxide layer;
the insulating protective layer is arranged on the first polycrystalline silicon and the second polycrystalline silicon;
and the source region is arranged on the second transverse well region, wherein the second transverse well region and the first transverse well region are respectively arranged on the bottom edge and the side edge of the first gate oxide layer.
In one embodiment, a depth of the first lateral well region is greater than a width of the first longitudinal well region.
In one embodiment, the width of the first lateral well region is smaller than the width of the recessed region of the first gate oxide layer.
In one embodiment, a depth of the second longitudinal well region is greater than a depth of the second lateral well region.
In one embodiment, an upper surface of the source region is flush with an upper surface of the second longitudinal well region.
The second aspect of the present invention also provides a method for manufacturing a silicon carbide MOSFET, the method comprising:
forming a silicon carbide epitaxial layer on the silicon carbide substrate, wherein the silicon carbide epitaxial layer and the silicon carbide substrate are both doped with first type doping ions, and the doping concentration of the silicon carbide epitaxial layer is less than that of the silicon carbide substrate;
forming a well region doping layer doped with second type doping ions on the silicon carbide epitaxial layer, and forming a first etching mask layer on the well region doping layer, wherein a plurality of grooves are formed in the first etching mask layer;
forming a buffer layer on the side wall of each groove on the first etching mask layer;
forming a silicon nitride filling layer in each groove on the first etching mask layer, and depositing a metal mask layer on the first etching mask layer;
selectively etching the metal mask layer, the first etching mask layer, the buffer layer and the silicon nitride to expose a preset first well region, wherein the central position of the first well region is covered by the silicon nitride filling layer;
etching the first well region to form a well region deep groove, wherein the depth of the well region deep groove is greater than that of the well region doping layer;
forming an injection barrier layer on the well region deep groove and the metal mask layer;
etching the injection barrier layer to expose the first well region doping area and the second well region doping area;
injecting second-type doped ions into the first well region doped region and the second well region doped region to form a first transverse well region in the silicon carbide epitaxial layer and a second longitudinal well region in the well region doped layer, wherein the doping concentrations of the first transverse well region and the second longitudinal well region are greater than that of the well region doped layer;
removing the injection blocking layer and the buffer layer to obtain a first well region and a second well region, wherein the first well region comprises a first transverse well region and a first longitudinal well region, the first transverse well region and the first longitudinal well region form a T-shaped structure doped with second type doped ions, the second well region comprises two second transverse well regions and one second longitudinal well region, and the two second transverse well regions are arranged on two sides of the second longitudinal well region;
depositing a gate oxide material to form a first gate oxide layer and a second gate oxide layer, wherein the first gate oxide layer and the second gate oxide layer are of concave structures and are respectively arranged on two sides of the first longitudinal well region;
injecting first type doping ions into the second transverse well region, depositing a carbon film and then performing annealing treatment to form a source region on the second transverse well region;
depositing polycrystalline silicon to form first polycrystalline silicon and second polycrystalline silicon in concave regions of the first gate oxide layer and the second gate oxide layer respectively, and forming an insulating protection layer on the first polycrystalline silicon and the second polycrystalline silicon.
In one embodiment, the forming a buffer layer on the sidewall of each trench on the first etch mask layer includes:
depositing silicon dioxide on the first etching mask layer to serve as a pre-buffer layer;
and carrying out dry etching on the pre-buffer layer to form a buffer layer on the inner wall of each groove.
In one embodiment, the filling of silicon nitride in each of the trenches on the first etch mask layer, and the depositing of a metal mask layer on the first etch mask layer, include:
depositing silicon nitride on the first etching mask layer to form a silicon nitride layer, and etching the silicon nitride layer until the buffer layer on the side wall of the groove is flush with the silicon nitride in the filling hole;
and depositing metal on the first etching mask layer to form a metal mask layer.
In one embodiment, the etching the implantation blocking layer to expose the first well region doping region and the second well region doping region includes:
etching the injection barrier layer in the well region deep groove to form a first well region doped region, wherein the width of the first well region doped region on two sides of the silicon nitride filling layer is equal;
and etching the injection blocking layer on the metal mask layer and the first etching mask layer to form the second well region doping area on the well region doping layer.
In one embodiment, the forming a second longitudinal well region on the well region doping layer includes:
and injecting second-type doped ions into the well region doped layer through the second well region doped region to form the second longitudinal well region, wherein the depth of the second longitudinal well region is greater than that of the well region doped layer.
According to the silicon carbide MOSFET and the preparation method thereof, the first well region and the second well region are respectively formed on the two sides of the first gate oxide layer and the second gate oxide layer, the first transverse well region and the first longitudinal well region in the first well region form the T-shaped structure doped with the second type of doped ions, the doping concentration of the first transverse well region is greater than that of the first longitudinal well region, the two second transverse well regions in the second well region are arranged on the two sides of the second longitudinal well region, and the doping concentration of the second longitudinal well region is greater than that of the second transverse well region, so that the depletion length of the MOSFET is ensured, the complete depletion of the MOSFET is ensured, the weakening of the electric field intensity at the corner of the groove is realized, and the stability of the silicon carbide MOSFET is improved.
Drawings
Fig. 1 is a schematic structural diagram of a silicon carbide MOSFET according to an embodiment of the present invention.
FIG. 2 is a schematic flow chart of a method for fabricating a silicon carbide MOSFET according to an embodiment of the present invention;
FIG. 3 is an exemplary diagram of a first etch mask layer formed over a well doped layer according to an embodiment of the invention;
FIG. 4 is an exemplary diagram of forming a buffer layer provided by an embodiment of the invention;
FIG. 5 is an exemplary diagram of forming a silicon nitride fill layer and a metal mask layer in accordance with an embodiment of the present invention;
FIG. 6 is an exemplary diagram of selectively etching a metal mask layer according to an embodiment of the present invention;
fig. 7 is an exemplary diagram of forming deep trenches of a well region according to an embodiment of the present invention;
FIG. 8 is an exemplary diagram of forming an implant block layer provided by an embodiment of the present invention;
FIG. 9 is an exemplary illustration of etching an implant block layer, as provided by an embodiment of the invention;
fig. 10 is an exemplary diagram of forming a first lateral well region and a second longitudinal well region according to an embodiment of the present invention;
fig. 11 is an exemplary diagram of a first well region and a second well region provided by an embodiment of the invention;
FIG. 12 is an exemplary diagram of forming source regions provided by an embodiment of the invention;
fig. 13 is an exemplary diagram of forming a gate oxide layer and polysilicon provided by an embodiment of the present invention;
fig. 14 is an exemplary diagram of forming an insulating protection layer according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
It will be understood that when an element is referred to as being "secured to" or "disposed on" another element, it can be directly on the other element or be indirectly on the other element. When an element is referred to as being "connected to" another element, it can be directly connected to the other element or be indirectly connected to the other element.
It will be understood that the terms "length," "width," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," and the like, refer to an orientation or positional relationship illustrated in the drawings for convenience in describing the present application and to simplify description, and do not indicate or imply that the referenced device or element must have a particular orientation, be constructed and operated in a particular orientation, and thus should not be construed as limiting the present application.
Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present application, "a plurality" means two or more unless specifically limited otherwise.
An embodiment of the present invention provides a silicon carbide MOSFET, as shown in fig. 1, including: the semiconductor device comprises a silicon carbide substrate 100, a silicon carbide epitaxial layer 200, a first well region 300, a second well region 500, a first gate oxide layer 410, a second gate oxide layer 420, first polysilicon 610, second polysilicon 620, an insulating protection layer 710 and a source region 810.
Specifically, the silicon carbide epitaxial layer 200 and the silicon carbide substrate 100 are doped with the first type of dopant ions, and the doping concentration of the silicon carbide epitaxial layer 200 is less than the doping concentration of the silicon carbide substrate 100.
The first well region 300 is disposed in a deep trench on the upper surface of the silicon carbide epitaxial layer 200, and the first well region 300 includes a first transverse well region 310 and a first longitudinal well region 320, wherein the first transverse well region 310 and the first longitudinal well region 320 form a T-shaped structure doped with second-type doped ions, the T-shaped structure is disposed in an inverted T-shape in the device, the bottom side (i.e., the first transverse well region 310) of the T-shaped structure contacts the silicon carbide epitaxial layer 200, the protruding structure (i.e., the first longitudinal well region 320) of the T-shaped structure contacts the insulating protection layer 710, and the doping concentration of the first transverse well region 310 is greater than the doping concentration of the first longitudinal well region 320.
Specifically, the second type of doped ions is different from the first type of doped ions, for example, the second type of doped ions is P-type doped, and the first type of doped ions is N-type doped, or the second type of doped ions is N-type doped, and the first type of doped ions is P-type doped.
The second well region 500 is disposed on the silicon carbide epitaxial layer 200 and disposed on a side of the first gate oxide layer 410, and the second well region 500 includes two second transverse well regions 520 and a second longitudinal well region 510, wherein the two second transverse well regions 520 are disposed on two sides of the second longitudinal well region 510, and a doping concentration of the second longitudinal well region 510 is greater than a doping concentration of the second transverse well region 520.
The first gate oxide layer 410 and the second gate oxide layer 420 are concave structures and are respectively arranged at two sides of the first longitudinal well region 320, the first well region 300 and the second well region 500 are respectively arranged at two sides of the first gate oxide layer 410, the first transverse well region 310 in the first well region 300 is arranged at the bottom edge of the first gate oxide layer 410, the second transverse well region 520 is arranged at the side edge of the first gate oxide layer 410, and one corner of the first gate oxide layer 410 is arranged between the first transverse well region 310 and the second transverse well region 520.
The first polysilicon 610 and the second polysilicon 620 are disposed in the recessed regions of the first gate oxide layer 410 and the second gate oxide layer 420, respectively.
The insulating protection layer 710 is disposed on the first polysilicon 610 and the second polysilicon 620, and the source region 810 is disposed on the second lateral well region 520, wherein the second lateral well region 520 and the first lateral well region 310 are disposed on the bottom side and the side edge of the first gate oxide layer 410, respectively.
In the present embodiment, referring to fig. 1, the first well region 300 is an inverted T-shaped structure, and the first lateral well region 310 at the bottom of the inverted T-shaped structure is a heavily doped region with a doping concentration greater than that of the first longitudinal well region 320, and since the first lateral well region 310 is a lateral structure, the heavily doped characteristic thereof can ensure that the depletion length is sufficient.
The second well region 500 is arranged at the side of the first gate oxide layer 410, wherein the doping concentration of the second longitudinal well region 510 in the second well region 500 is greater than that of the second transverse well region 520, at this time, depletion is formed between the first transverse well region 310 and the second longitudinal well region 510, and by clamping off the electric field at the corner of the first gate oxide layer 410, the influence of the electric field strength on the gate oxide at the corner can be reduced, so that the effect of protecting the gate oxide layer and preventing the gate oxide layer from being punctured is achieved.
Similarly, referring to fig. 1, if two unit cells are included in the same power chip, the second well region 500 is disposed between adjacent unit cells, so that the depletion of the sidewall trench can be realized together, and the influence of the electric field strength on the corner of the trench is reduced.
In one embodiment, the first type dopant ions doped in the silicon carbide epitaxial layer 200 and the silicon carbide substrate 100 may be N-type dopant ions, such as aluminum ions, boron ions, and the like.
In one embodiment, the second type dopant ions doped in the first well region 300 and the second well region 500 may be P type dopant ions, such as phosphorus ions, nitrogen ions, and the like.
In one embodiment, referring to fig. 1, the depth of the first lateral well region 310 is greater than the width of the first longitudinal well region 320.
Specifically, as shown in fig. 1, the first longitudinal well region 320 is a vertical structure, has a narrow lateral width, and can be used to isolate the first gate oxide layer 410 from the second gate oxide layer 420, the first longitudinal well region 310 can be formed by implanting second-type dopant ions into the silicon carbide epitaxial layer 200, the implantation depth of the second-type dopant ions determines the depth of the first longitudinal well region 310, and the width of the first longitudinal well region 320 can be defined by an etching mask layer. In one embodiment, referring to fig. 1, the width of the first lateral well region 310 is less than the width of the recessed region of the first gate oxide layer 410.
Specifically, the first lateral well region 310 is disposed on the bottom side of the first gate oxide layer 410, the width of the first lateral well region 310 is smaller than the length of the bottom side of the first gate oxide layer 410, the second lateral well region 520 is disposed on the side of the first gate oxide layer 410, one corner of the first gate oxide layer 410 is disposed between the first lateral well region 310 and the second lateral well region 520, and the thickness of the second lateral well region 520 is smaller than the length of the side of the first gate oxide layer 410.
In one embodiment, the first vertical well region 320 is disposed at an axial centerline position of the first lateral well region 310, and the first lateral well region 310 on both sides thereof has the same width with the first vertical well region 320 as a central axis, and the width of the first lateral well region 310 on both sides thereof is smaller than the width of the gate oxide layers (the first gate oxide layer 410 and the second gate oxide layer 420) on both sides thereof.
In one embodiment, the first longitudinal well region 320 is taken as a central axis, the widths of the first lateral well regions 310 on both sides thereof are the same, and the widths of the first lateral well regions 310 on both sides thereof are half of the widths of the gate oxide layers (the first gate oxide layer 410 and the second gate oxide layer 420) on both sides thereof.
In one embodiment, the depth of the second vertical well region 510 is greater than the depth of the second lateral well region 520.
In the second well region 500, the doping concentration of the second longitudinal well region 510 is greater than that of the second transverse well region 520, both sides of the second longitudinal well region 510 are provided with the second transverse well region 520, the thickness of the second transverse well region 520 on both sides of the second longitudinal well region is the same, the depth of the second longitudinal well region 510 is set to be greater than that of the second transverse well region 520, the second well region 500 can be set to be a T-shaped structure, the second transverse well region 520 is located on both sides above the second longitudinal well region 510 at the moment, the second transverse well region 520 with higher doping concentration can ensure complete depletion on the lower side, and the electric field intensity at the corner of the first gate oxide layer 410 is weakened.
In one embodiment, the upper surface of source region 810 is flush with the upper surface of second vertical well region 510.
In this embodiment, the source regions 810 are disposed on both sides of the second vertical well region 510, and the upper surfaces of the source regions 810 are flush with the upper surface of the second vertical well region 510.
In one embodiment, the insulating protection layer 710 is provided with contact holes, and gate electrodes connected to the first and second polysilicon layers 610 and 620 are formed on the insulating protection layer 710 by filling an electrode metal in the contact holes.
In one embodiment, the first well region 300 is connected to the second lateral well region 520 by peripheral vias, which serve as the source of a silicon carbide MOSFET.
The embodiment of the present application further provides a method for manufacturing a silicon carbide MOSFET, and referring to fig. 2, the method in the present embodiment includes steps S101 to S113.
In step S101, a silicon carbide epitaxial layer is formed on the silicon carbide substrate.
The silicon carbide epitaxial layer and the silicon carbide substrate are both doped with first type doping ions, and the doping concentration of the silicon carbide epitaxial layer is smaller than that of the silicon carbide substrate.
In step S102, a well region doping layer doped with second type doping ions is formed on the silicon carbide epitaxial layer, and a first etching mask layer is formed on the well region doping layer, wherein a plurality of trenches are formed on the first etching mask layer.
Referring to fig. 3, the silicon carbide epitaxial layer 200 is disposed on the silicon carbide substrate 100, and at this time, the silicon carbide epitaxial layer 200 and the silicon carbide substrate 100 are both doped with the first type dopant ions, wherein the doping concentration of the silicon carbide epitaxial layer 200 is less than the doping concentration of the silicon carbide substrate 100, the well region doping layer 330 is disposed on the silicon carbide epitaxial layer 200, the first etching mask layer 340 is disposed on the well region doping layer 330, and the first etching mask layer 340 is provided with a plurality of trenches.
Specifically, a well region doping layer 330 may be formed on the upper surface of the silicon carbide epitaxial layer 200 by epitaxy or ion implantation, and then a plurality of trenches are formed by selective etching using a photoresist, the plurality of trenches are arranged in an array, the distances between adjacent trenches are the same, and the sizes of the plurality of trenches are the same.
In a specific application, the second type of doped ions is different from the first type of doped ions, for example, the second type of doped ions is P-type doped and the first type of doped ions is N-type doped, or the second type of doped ions is N-type doped and the first type of doped ions is P-type doped.
In one embodiment, the first type dopant ions doped in the silicon carbide epitaxial layer 200 and the silicon carbide substrate 100 may be N-type dopant ions, such as aluminum ions, boron ions, and the like.
In one embodiment, the second type dopant ions doped in the first well region 300 and the second well region 500 may be P type dopant ions, such as phosphorus ions, nitrogen ions, and the like.
In one embodiment, the first etch mask layer 340 may be a silicon nitride layer, and a plurality of trenches may be formed on the silicon nitride layer by selectively etching the silicon nitride layer through a photoresist.
In step S103, a buffer layer is formed on a sidewall of each of the trenches on the first etch mask layer.
As shown in fig. 4, a buffer layer 350 is formed in each trench on the first etching mask layer 340 to protect the subsequent etching process and prevent the etching solution from affecting the non-etching region in the well region doped layer 330.
In one embodiment, in step S103, forming a buffer layer on the sidewall of each trench on the first etch mask layer includes:
step S103-1: depositing silicon dioxide on the first etching mask layer to serve as a pre-buffer layer;
step S103-2: and carrying out dry etching on the pre-buffer layer to form a buffer layer on the inner wall of each groove.
Specifically, a pre-buffer layer may be formed by depositing silicon dioxide on the first etching mask layer 340, and then performing mask-free dry etching on the pre-buffer layer to remove the silicon dioxide on the upper surface of the first etching mask layer 340, so as to form an unfilled hole in each trench, where the silicon dioxide that is not etched may be formed on the inner wall of each trench as the buffer layer 350, as shown in fig. 4.
In step S104, a silicon nitride filling layer is formed in each of the trenches on the first etching mask layer, and a metal mask layer is deposited on the first etching mask layer.
In this embodiment, as shown in fig. 5, a photoresist may be used as a mask, and then silicon nitride may be deposited to form a silicon nitride filling layer 360 in each trench, or a silicon nitride filling layer 360 may be formed in each trench in the order of depositing silicon nitride and etching silicon nitride, and a metal mask layer 370 may be deposited on the first etching mask layer 340 after the silicon nitride filling layer 360 is formed.
In one embodiment, in step S104, filling silicon nitride in each of the trenches on the first etch mask layer, and depositing a metal mask layer on the first etch mask layer, includes:
step S104-1: depositing silicon nitride on the first etching mask layer to form a silicon nitride layer, and etching the silicon nitride layer until the buffer layer on the side wall of the groove is flush with the silicon nitride in the filling hole;
step S104-2: and depositing metal on the first etching mask layer to form a metal mask layer.
In the present embodiment, a silicon nitride layer is formed by depositing silicon nitride on the first etching mask layer 340, the silicon nitride layer not only fills in the filling hole formed by the buffer layer 350, but also exists on the first etching mask layer and the buffer layer 350, and is dry-etched through a maskless method until the upper surface of the buffer layer 350 is exposed, and then a metal mask layer is deposited on the first etching mask layer 340.
In one embodiment, a metallic nickel layer may be formed as the metallic mask layer 370 by depositing metallic nickel on the first etch mask layer 340.
In one embodiment, the thickness of the metal mask layer 370 may be 1-5 um.
In step S105, the metal mask layer, the first etching mask layer, the buffer layer, and the silicon nitride are selectively etched to expose a predetermined first well region, where a central position of the first well region is covered by the silicon nitride filling layer.
In the present embodiment, as shown in fig. 6, by selectively etching the metal mask layer 370, a predetermined first well region, such as the first etching region 401 and the second etching region 402 in fig. 6, may be exposed, and the first well region is disposed around the silicon nitride filling layer 360, and at this time, the silicon nitride filling layer 360 may serve as a subsequent etching mask.
In a specific application, a photoresist is formed on the metal mask layer 370 to define a first well region, then the metal mask layer 370 is dry etched to expose the silicon nitride filling layer 360 and the buffer layer 350 covered by the first well region, the buffer layer 350 is silicon dioxide, wet etching of silicon nitride can be performed under protection of the photoresist to etch away the exposed silicon nitride filling layer 360, then wet etching process of silicon dioxide is performed, and the exposed silicon dioxide is also etched away under protection of the photoresist and the silicon nitride filling layer 360 to obtain the structure shown in fig. 6.
Further, a part of the metal mask layer 370 may be etched away in the process of etching the silicon dioxide with hydrofluoric acid, and the hydrofluoric acid may be used to prevent the metal mask layer from reacting with the well region doping layer 330, so as to protect the well region doping layer 330 from being affected.
In step S106, the first well region is etched to form a deep well region trench, where a depth of the deep well region trench is greater than a depth of the doped well region layer.
In the present embodiment, as shown in fig. 7, the silicon nitride filling layer 360 exposed in step S105 is used as a mask to etch the first well region to form well region deep trenches (the first deep trench 411 and the second deep trench 412) surrounding the exposed silicon nitride filling layer 360, and the depth of the well region deep trenches is greater than that of the well region doping layer 330.
In one embodiment, the distance between the bottom surfaces of the first and second deep trenches 411 and 412 and the lower surface of the well region doping layer 330 is less than the thickness of the well region doping layer 330.
In step S107, an implantation blocking layer is formed on the well deep trench and the metal mask layer.
Referring to fig. 8, the deep well region is filled with an implantation blocking material to form an implantation blocking layer 380, and the implantation blocking layer 380 not only fills the deep well region, but also covers the metal mask layer 370.
In one embodiment, the implant block material may be silicon dioxide.
In step S108, the implantation blocking layer is etched to expose the first well region doped region and the second well region doped region.
As shown in fig. 9, an etching region of the implantation blocking layer 380 may be defined by photoresist, and then the implantation blocking layer 380 is etched, so that the first well region doping region (see the first doping region 381 and the second doping region 382 in fig. 9) and the second well region doping region (see the third doping region 383 in fig. 9) are exposed.
Specifically, the first well region doping region is located on the surface of the silicon carbide epitaxial layer 200, and the second well region doping region is located on the surface of the well region doping layer 330.
In one embodiment, in step S108, etching the implantation blocking layer to expose the first well region doping region and the second well region doping region includes:
step S108-1: etching the injection barrier layer in the well region deep groove to form a first well region doped region, wherein the width of the first well region doped region on two sides of the silicon nitride filling layer is equal;
step S108-2: and etching the injection blocking layer on the metal mask layer and the first etching mask layer to form the second well region doping area on the well region doping layer.
In this embodiment, by etching the implantation blocking layer 380 in the deep trench of the well region, the first well region doped region is exposed at two sides of the silicon nitride filling layer 360, and the widths of the first well region doped regions at two sides are equal, and meanwhile, the position of the second well region doped region is defined by the photoresist, and the metal mask layer 370, the implantation blocking layer 380, and the first etching mask layer 350 are etched to form the second well region doped region on the well region doped layer 330.
In step S109, second type dopant ions are implanted into the first well region doped region and the second well region doped region to form a first lateral well region in the silicon carbide epitaxial layer and a second longitudinal well region in the well region doped layer, wherein the doping concentrations of the first lateral well region and the second longitudinal well region are greater than the doping concentration of the well region doped layer.
As shown in fig. 10, under the cover of the implantation blocking layer 380, second-type dopant ions are implanted into the first well region doping region, so as to form a first lateral well region 310 in the silicon carbide epitaxial layer 200, and second-type dopant ions are implanted into the second well region doping region, so as to form a second longitudinal well region 510 in the well region doping layer 330, wherein the doping concentrations of the first lateral well region 310 and the second longitudinal well region 510 are greater than the doping concentration of the well region doping layer 330.
In one embodiment, the second type dopant ions implanted into the first well region doped region and the second well region doped region may be aluminum ions.
In one embodiment, in step S109, forming a second vertical well region in the well region doping layer includes: and injecting second-type doped ions into the well region doped layer through the second well region doped region to form the second longitudinal well region, wherein the depth of the second longitudinal well region is greater than that of the well region doped layer.
Specifically, as shown in fig. 10, second-type doped ions are implanted into the well region doping layer 330 through the second well region doping region, so as to form a second longitudinal well region 510 in the well region doping layer 330 and the silicon carbide epitaxial layer 200, and the second longitudinal well region 510 divides the well region doping layer 330 into second lateral well regions 520 with the same size, and the depth of the second lateral well regions is greater than the depth of the well region doping layer 330.
In step S110, the implantation blocking layer and the buffer layer are removed to obtain a first well region and a second well region.
The first well region comprises a first transverse well region and a first longitudinal well region, the first transverse well region and the first longitudinal well region form a T-shaped structure doped with second type doped ions, the second well region comprises two second transverse well regions and one second longitudinal well region, and the two second transverse well regions are arranged on two sides of the second longitudinal well region.
In this embodiment, referring to fig. 11, after removing the implantation blocking layer 380, the silicon nitride filling layer 360, the buffer layer 350, and the first etching mask layer 340, annealing the device to obtain a first well region and a second well region, where the first well region includes a first lateral well region 310 and a first longitudinal well region 320, the first lateral well region 310 and the first longitudinal well region 320 form a T-shaped structure doped with the second type of doped ions, the T-shaped structure is an inverted T-shaped structure in the device, a bottom edge (i.e., the first lateral well region 310) of the T-shaped structure contacts the silicon carbide epitaxial layer 200, a protruding structure (i.e., the first longitudinal well region 320) of the T-shaped structure contacts the insulating protection layer 710, and a doping concentration of the first lateral well region 310 is greater than a doping concentration of the first longitudinal well region 320.
The second well region includes two second lateral well regions 520 and a second longitudinal well region 510, the two second lateral well regions 520 are disposed on two sides of the second longitudinal well region 510, and the doping concentration of the second longitudinal well region 510 is greater than the doping concentration of the second lateral well region 520.
In step S111, first type dopant ions are implanted into the second lateral well region, and a carbon film is deposited and then annealed to form a source region on the second lateral well region.
In this embodiment, the region where the second lateral well region 520 is exposed may be covered by a photoresist, the first type dopant ions may be implanted into the second lateral well region 520, the photoresist may be removed, a carbon film may be used to cover the entire device, and an annealing process may be performed on the device under the protection of the carbon film, so as to form the source region 810 on the second lateral well region 520, as shown in fig. 12. The carbon film covers the device, so that the silicon dangling bond caused by silicon carbide mismatch in the annealing process can be avoided.
Further, in step S109, the first lateral well region 310 is doped with the second type dopant ions, and in the case of annealing, the second type dopant ions may diffuse into the first longitudinal well region 320, so that the vertical structure between the well region doping layer 330 in the first longitudinal well region 320 and the silicon carbide epitaxial layer 200 is doped with the second type dopant ions.
In step S112, a gate oxide material is deposited to form a first gate oxide layer and a second gate oxide layer, where the first gate oxide layer and the second gate oxide layer are in a concave structure and are respectively disposed on two sides of the first longitudinal well region.
As shown in fig. 13, a first gate oxide layer 410 and a second gate oxide layer 420 having a concave structure may be formed on two sides of the first vertical well region 320 in the first well region by depositing a gate oxide material or an oxide body on the bottom and the side walls of the trench formed by the first well region. Referring to fig. 13, the second lateral well region 520 and the first lateral well region 310 are respectively disposed at the bottom and the side of the first gate oxide layer 410.
In one embodiment, the first vertical well region 320 is disposed at an axial centerline position of the first lateral well region 310, and the first lateral well region 310 on both sides thereof has the same width with the first vertical well region 320 as a central axis, and the width of the first lateral well region 310 on both sides thereof is smaller than the width of the gate oxide layers (the first gate oxide layer 410 and the second gate oxide layer 420) on both sides thereof.
In step S113, depositing polysilicon to form a first polysilicon and a second polysilicon in the concave regions of the first gate oxide and the second gate oxide, respectively, and forming an insulating protection layer on the first polysilicon and the second polysilicon.
In the present embodiment, as shown in fig. 13, a first polysilicon is formed in the recess of the first gate oxide layer 410 and a second polysilicon is formed in the recess of the second gate oxide layer 420, respectively, by depositing a polysilicon material.
In the present embodiment, as shown in fig. 14, an insulating protection layer 710 is formed on the first polysilicon 610 and the second polysilicon 620 by depositing an insulating material.
Specifically, the base of first gate oxide 410 is located to first horizontal well region 310, its width is less than the base length of first gate oxide 410, the side of first gate oxide 410 is located to the horizontal well region 520 of second, a turning of first gate oxide 410 is located between first horizontal well region 310 and the horizontal well region 520 of second, the thickness of the horizontal well region 520 of second is less than the length of first gate oxide 410 side, at this moment, form between first horizontal well region 310 and the vertical well region 510 of second and exhaust, through the electric field of pinching off first gate oxide 410 corner, can reduce the influence of electric field intensity to its corner gate oxygen, reach the protection gate oxide, prevent its effect of being punctured.
Further, in one embodiment, the insulating protection layer 710 is selectively etched to form a plurality of contact holes exposing the second lateral well region 520, the polysilicon (the first polysilicon 610 and the second polysilicon 620) and the first well region 300, respectively, and then the polysilicon is connected to the gate electrode by depositing metal and etching the metal, and the first well region 300 is connected to the second lateral well region 520 through the peripheral metal traces to serve as the source of the silicon carbide MOSFET.
According to the silicon carbide MOSFET and the preparation method thereof, the first well region and the second well region are respectively formed on the two sides of the first gate oxide layer and the second gate oxide layer, the first transverse well region and the first longitudinal well region in the first well region form the T-shaped structure doped with the second type of doped ions, the doping concentration of the first transverse well region is greater than that of the first longitudinal well region, the two second transverse well regions in the second well region are arranged on the two sides of the second longitudinal well region, and the doping concentration of the second longitudinal well region is greater than that of the second transverse well region, so that the depletion length of the MOSFET is ensured, the complete depletion of the MOSFET is ensured, the weakening of the electric field intensity at the corner of the groove is realized, and the stability of the silicon carbide MOSFET is improved.
It will be clear to those skilled in the art that, for convenience and simplicity of description, the above division of the doped regions is merely illustrated, and in practical applications, the above functional region allocation can be performed by different doped regions according to needs, that is, the internal structure of the device is divided into different doped regions to perform all or part of the above-described functions.
In the embodiment, each doped region may be integrated in one functional region, or each doped region may exist alone physically, or two or more doped regions may be integrated in one functional region, and the integrated functional regions may be implemented by using the same type of doped ions, or by using multiple types of doped ions. In addition, the specific names of the doped regions are only for the convenience of distinguishing from each other, and are not used to limit the protection scope of the present application. For a specific working process of the middle doped region in the method for manufacturing the device, reference may be made to a corresponding process in the foregoing method embodiment, which is not described herein again.
The above-mentioned embodiments are only used for illustrating the technical solutions of the present invention, and not for limiting the same; although the present invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; such modifications and substitutions do not substantially depart from the spirit and scope of the embodiments of the present invention, and are intended to be included within the scope of the present invention.
Claims (10)
1. A silicon carbide MOSFET, comprising:
a silicon carbide substrate;
the silicon carbide epitaxial layer and the silicon carbide substrate are both doped with first type doping ions, and the doping concentration of the silicon carbide epitaxial layer is smaller than that of the silicon carbide substrate;
the first well region is arranged in the deep groove on the upper surface of the silicon carbide epitaxial layer and comprises a first transverse well region and a first longitudinal well region, wherein the first transverse well region and the first longitudinal well region form a T-shaped structure doped with second type doped ions, and the doping concentration of the first transverse well region is greater than that of the first longitudinal well region;
the second well region is arranged on the silicon carbide epitaxial layer and comprises two second transverse well regions and a second longitudinal well region, wherein the two second transverse well regions are arranged on two sides of the second longitudinal well region, and the doping concentration of the second longitudinal well region is greater than that of the second transverse well region;
the first gate oxide layer and the second gate oxide layer are of concave structures and are respectively arranged on two sides of the first longitudinal well region;
the first polycrystalline silicon and the second polycrystalline silicon are respectively arranged in the concave regions of the first gate oxide layer and the second gate oxide layer;
the insulating protective layer is arranged on the first polycrystalline silicon and the second polycrystalline silicon;
and the source region is arranged on the second transverse well region, wherein the second transverse well region and the first transverse well region are respectively arranged on the bottom edge and the side edge of the first gate oxide layer.
2. The silicon carbide MOSFET of claim 1, wherein the depth of the first lateral well region is greater than the width of the first longitudinal well region.
3. The silicon carbide MOSFET of claim 2 wherein the first lateral well region has a width less than a recess width of the first gate oxide layer.
4. The silicon carbide MOSFET of claim 1 wherein the depth of the second longitudinal well region is greater than the depth of the second lateral well region.
5. The silicon carbide MOSFET of claim 1, wherein an upper surface of the source region is flush with an upper surface of the second longitudinal well region.
6. A preparation method of a silicon carbide MOSFET is characterized by comprising the following steps:
forming a silicon carbide epitaxial layer on a silicon carbide substrate, wherein the silicon carbide epitaxial layer and the silicon carbide substrate are both doped with first type doping ions, and the doping concentration of the silicon carbide epitaxial layer is less than that of the silicon carbide substrate;
forming a well region doping layer doped with second type doping ions on the silicon carbide epitaxial layer, and forming a first etching mask layer on the well region doping layer, wherein a plurality of grooves are formed in the first etching mask layer;
forming a buffer layer on the side wall of each groove on the first etching mask layer;
forming a silicon nitride filling layer in each groove on the first etching mask layer, and depositing a metal mask layer on the first etching mask layer;
selectively etching the metal mask layer, the first etching mask layer, the buffer layer and the silicon nitride to expose a preset first well region, wherein the central position of the first well region is covered by the silicon nitride filling layer;
etching the first well region to form a well region deep groove, wherein the depth of the well region deep groove is greater than that of the well region doping layer;
forming an injection barrier layer on the well region deep groove and the metal mask layer;
etching the injection barrier layer to expose the first well region doping area and the second well region doping area;
injecting second-type doped ions into the first well region doped region and the second well region doped region to form a first transverse well region in the silicon carbide epitaxial layer and a second longitudinal well region in the well region doped layer, wherein the doping concentrations of the first transverse well region and the second longitudinal well region are greater than that of the well region doped layer;
removing the injection blocking layer and the buffer layer to obtain a first well region and a second well region, wherein the first well region comprises a first transverse well region and a first longitudinal well region, the first transverse well region and the first longitudinal well region form a T-shaped structure doped with second type doped ions, the second well region comprises two second transverse well regions and one second longitudinal well region, and the two second transverse well regions are arranged on two sides of the second longitudinal well region;
injecting first type doping ions into the second transverse well region, depositing a carbon film and then performing annealing treatment to form a source region on the second transverse well region;
depositing a gate oxide material to form a first gate oxide layer and a second gate oxide layer, wherein the first gate oxide layer and the second gate oxide layer are of concave structures and are respectively arranged on two sides of the first longitudinal well region; the second transverse well region and the first transverse well region are respectively arranged on the bottom edge and the side edge of the first gate oxide layer;
depositing polycrystalline silicon to form first polycrystalline silicon and second polycrystalline silicon in concave regions of the first gate oxide layer and the second gate oxide layer respectively, and forming an insulating protection layer on the first polycrystalline silicon and the second polycrystalline silicon.
7. The method of claim 6, wherein forming a buffer layer on sidewalls of each of the trenches on the first etch mask layer comprises:
depositing silicon dioxide on the first etching mask layer to serve as a pre-buffer layer;
and carrying out dry etching on the pre-buffer layer to form a buffer layer on the inner wall of each groove.
8. The method of claim 6, wherein the filling of silicon nitride in each of the trenches on the first etch mask layer and the depositing of a metal mask layer on the first etch mask layer comprises:
depositing silicon nitride on the first etching mask layer to form a silicon nitride layer, and etching the silicon nitride layer until the buffer layer on the side wall of the groove is flush with the silicon nitride in the filling hole;
and depositing metal on the first etching mask layer to form a metal mask layer.
9. The method of claim 6, wherein etching the implant blocking layer to expose the first well doped region and the second well doped region comprises:
etching the injection barrier layer in the well region deep groove to form a first well region doped region, wherein the width of the first well region doped region on two sides of the silicon nitride filling layer is equal;
and etching the injection blocking layer on the metal mask layer and the first etching mask layer to form the second well region doping area on the well region doping layer.
10. The method according to claim 6, wherein the forming of the second vertical well region in the well region doping layer comprises:
and injecting second-type doped ions into the well region doped layer through the second well region doped region to form the second longitudinal well region, wherein the depth of the second longitudinal well region is greater than that of the well region doped layer.
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