CN114496783B - Groove type silicon carbide MOSFET prepared based on buffer layer and preparation method thereof - Google Patents
Groove type silicon carbide MOSFET prepared based on buffer layer and preparation method thereof Download PDFInfo
- Publication number
- CN114496783B CN114496783B CN202210401030.8A CN202210401030A CN114496783B CN 114496783 B CN114496783 B CN 114496783B CN 202210401030 A CN202210401030 A CN 202210401030A CN 114496783 B CN114496783 B CN 114496783B
- Authority
- CN
- China
- Prior art keywords
- silicon carbide
- region
- pwell
- groove
- buffer layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 title claims abstract description 96
- 229910010271 silicon carbide Inorganic materials 0.000 title claims abstract description 96
- 238000002360 preparation method Methods 0.000 title claims abstract description 19
- 238000002347 injection Methods 0.000 claims abstract description 21
- 239000007924 injection Substances 0.000 claims abstract description 21
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 16
- 238000005530 etching Methods 0.000 claims abstract description 15
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 14
- 238000000407 epitaxy Methods 0.000 claims abstract description 12
- 229920005591 polysilicon Polymers 0.000 claims abstract description 12
- 235000012239 silicon dioxide Nutrition 0.000 claims abstract description 8
- 239000000377 silicon dioxide Substances 0.000 claims abstract description 8
- 239000000758 substrate Substances 0.000 claims abstract description 7
- 239000010410 layer Substances 0.000 claims description 48
- 238000000151 deposition Methods 0.000 claims description 14
- 150000002500 ions Chemical class 0.000 claims description 10
- 239000011241 protective layer Substances 0.000 claims description 10
- 238000001465 metallisation Methods 0.000 claims description 9
- 238000000034 method Methods 0.000 claims description 9
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims description 6
- 229910052799 carbon Inorganic materials 0.000 claims description 6
- 239000002184 metal Substances 0.000 claims description 4
- 238000000137 annealing Methods 0.000 claims description 3
- 230000008021 deposition Effects 0.000 claims description 3
- 238000001312 dry etching Methods 0.000 claims description 3
- 238000002955 isolation Methods 0.000 claims description 3
- 230000005684 electric field Effects 0.000 abstract description 9
- 229910052681 coesite Inorganic materials 0.000 abstract description 5
- 229910052906 cristobalite Inorganic materials 0.000 abstract description 5
- 229910052682 stishovite Inorganic materials 0.000 abstract description 5
- 229910052905 tridymite Inorganic materials 0.000 abstract description 5
- 238000010586 diagram Methods 0.000 description 5
- 238000002513 implantation Methods 0.000 description 5
- 230000002035 prolonged effect Effects 0.000 description 4
- 229910021332 silicide Inorganic materials 0.000 description 3
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 3
- 230000015556 catabolic process Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 239000000243 solution Substances 0.000 description 2
- -1 SiO2 Chemical compound 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66053—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide
- H01L29/6606—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
- H01L29/872—Schottky diodes
- H01L29/8725—Schottky diodes of the trench MOS barrier type [TMBS]
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Manufacturing & Machinery (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
The invention provides a groove type silicon carbide MOSFET prepared based on a buffer layer and a preparation method thereof, wherein the preparation method comprises the following steps: a drain (10), a silicon carbide substrate (9), a silicon carbide N epitaxy (8); the upper left side in the silicon carbide N epitaxy (8) comprises a Pwell region (3), and the trench region (32) comprises a Pplusbottom region (7), a gate oxide region (6) and a polysilicon region (5) from bottom to top; a source electrode (1). According to the groove type silicon carbide MOSFET prepared based on the buffer layer and the preparation method thereof, the injection buffer layer is applied during the Pwell injection to form the Pwell bottom with the depth larger than that of the groove, then the silicon carbide etching of the Pwell bottom area is carried out, so that part of the Pwell bottom is reserved at the bottom of the groove, and the Pwell bottom and the Pwell are in a connection state through an unetched area, namely, a grounded contact is reserved; under the protection of the side wall of SiN or SiO2, performing enrichment injection on Pwellbottom to form Ppplussbottom; the Ppplusbottom can pinch off the gate oxide electric field at the groove position because the homologous electrodes keep equipotential, and failure caused by strong gate oxide electric field is avoided.
Description
Technical Field
The invention relates to the technical field of preparation of groove type silicon carbide MOSFET, in particular to a groove type silicon carbide MOSFET prepared based on a buffer layer and a preparation method thereof.
Background
The silicon carbide MOSFET is an important component of modern power electronic devices, and has the characteristics of high frequency and high power density, so that the volume of a power supply can be greatly reduced, and the conversion efficiency is improved. Silicon carbide MOSFETs mainly comprise two structures, planar and trench, and because of the low channel mobility of planar silicon carbide MOSFETs, the current density does not perform as well as trench silicon carbide MOSFETs. Known semiconductor device manufacturers such as english-flying, lom generally adopt a trench MOSFET, for example, lom adopts a double-trench structure, and english-flying uses a structure of a single trench and a single-side injection P-emitter to weaken the electric field strength at the corner of the trench, protect gate oxide, and prevent breakdown.
However, the trench MOSFET described above has a poor protection at the bottom of the gate electrode, which increases the risk of breakdown and limits the lifetime of the trench MOSFET, and therefore, there is a need for improvement in view of this defect.
Disclosure of Invention
In view of the above, there is a need for a trench type silicon carbide MOSFET prepared based on a buffer layer and a preparation method thereof, which can effectively protect the bottom of the gate of the trench type silicon carbide MOSFET and improve the service life and the lifetime.
In order to solve the technical problem, the invention provides a trench type silicon carbide MOSFET prepared based on a buffer layer, which comprises:
the drain electrode, the silicon carbide substrate located above the drain electrode, and the silicon carbide N epitaxy located above the silicon carbide substrate; the upper left side of the inner part of the silicon carbide N epitaxy comprises a Pwell area, two N + areas and one Pplus area are arranged above the Pwell area, the upper right side of the inner part of the silicon carbide N epitaxy comprises a groove area, and the groove area comprises a Pplus bottom area, a gate oxide area and a polysilicon area from bottom to top; the two N + regions and one Pplus region comprise a source electrode above;
wherein the PpplusBottom region is deeper than the Pwell region.
Preferably, the Pwell region is connected to the sidewall of the trench region, and two of the Pwell regions are repeatedly disposed above the inside of the silicon carbide N epitaxy.
Preferably, said one Pplus region is located in the middle of said two N + regions.
Preferably, the gate oxide region wraps the polysilicon region in a semi-annular shape.
Preferably, the lower part of the gate oxide region is connected with the upper part of the PpplussBottom region.
The invention also provides a preparation method of the groove type silicon carbide MOSFET based on the buffer layer preparation, which comprises the following steps:
depositing and injecting polycrystalline silicon into a buffer layer, and etching the buffer layer;
injecting Al ions at high temperature for multiple times to obtain a Pwell area with the depth smaller than the depth of the groove and a Pwell bottom area with the depth larger than the depth of the groove;
silicon dioxide is used for depositing silicon carbide to etch the mask layer and open holes, and the size of each open hole is larger than or equal to the depth of the PwellBottom area;
etching silicon carbide to form a silicon carbide groove, wherein the depth of the silicon carbide groove is less than that of the Pwellbottom area, and part of the Pwellbottom area is reserved in the silicon carbide groove;
depositing silicon carbide and carrying out mask-free dry etching on the silicon carbide to obtain a groove with a silicon carbide protective layer;
performing Al ion enrichment injection to form a PpplusBottom region;
removing the mask layer, only keeping the silicon carbide protective layer, continuing to perform enrichment injection of Al ions to the Pwell area, and simultaneously enriching the Ppplusbottm area at the bottom;
removing the silicon carbide protective layer, selectively performing N + injection on the Pplus area, depositing a carbon film, performing high-temperature annealing, and then removing the carbon film;
preparing a gate oxide region and a polysilicon region;
and then, carrying out isolation layer deposition, source opening and ohmic metallization, and Poly opening and metallization, forming a source electrode and a grid electrode by etching metal, and forming a drain electrode by back metallization to obtain the buffer layer-based prepared groove type silicon carbide MOSFET.
The beneficial effects of adopting the above embodiment are:
according to the groove type silicon carbide MOSFET prepared based on the buffer layer and the preparation method thereof, the injection buffer layer is applied during the Pwell injection to form the Pwell bottom with the depth larger than that of the groove, then the silicon carbide etching of the Pwell bottom area is carried out, so that part of the Pwell bottom is reserved at the bottom of the groove, and the Pwell bottom and the Pwell are in a connection state through an unetched area, namely, a grounded contact is reserved; under the protection of the side wall of SiN or SiO2, performing enrichment injection on Pwellbottom to form Ppplussbottom; the Ppplusbottom can pinch off the electric field of the gate oxide at the groove position because the homologous electrodes keep the equipotential, and the failure caused by the strong electric field of the gate oxide is avoided, so that the bottom of the grid of the groove type silicon carbide MOSFET can be effectively protected, the service life is prolonged, and the service life is prolonged.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
FIG. 1 is a schematic structural diagram of a buffer layer-based trench silicon carbide MOSFET in accordance with an embodiment of the present invention;
FIG. 2 is a schematic structural diagram of an embodiment of a trench region during fabrication of a trench-type silicon carbide MOSFET fabricated based on a buffer layer according to the present invention;
fig. 3 to fig. 11 are schematic views illustrating structural changes of a trench type silicon carbide MOSFET in the method for manufacturing a trench type silicon carbide MOSFET based on a buffer layer according to the present invention.
Detailed Description
The technical solution in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. It is to be understood that the described embodiments are merely exemplary of the invention, and not restrictive of the full scope of the invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The invention provides a groove type silicon carbide MOSFET prepared based on a buffer layer and a preparation method thereof, which are respectively explained below.
Fig. 1 is a schematic structural diagram of a trench silicon carbide MOSFET made based on a buffer layer according to an embodiment of the present invention.
In this embodiment, the present invention provides a trench type silicon carbide MOSFET prepared based on a buffer layer, including:
a drain 10, a silicon carbide substrate 9 located above the drain 10, and a silicon carbide N epitaxy 8 located above the silicon carbide substrate 9; the upper left side inside the silicon carbide N epitaxy 8 comprises a Pwell region 3, the Pwell region 3 comprises two N + regions 2 and one Pplus region 4, the upper right side inside the silicon carbide N epitaxy 8 comprises a trench region 32, and the trench region 32 comprises a Pplus bottom region 7, a gate oxide region 6 and a polysilicon region 5 from bottom to top; the source 1 is included above the two N + regions 2 and one Pplus region 4. Wherein the depth of the PpplusBottom region 7 is greater than the depth of the Pwell region 3.
It should be noted that, the depth of the ppluss bottom region 7 is set to be greater than the depth of the Pwell region 3, and the width of the ppluss bottom region 7 is the same as the width of the gate oxide region 6, so that a part of Pwell bottom is reserved at the bottom of the trench, where Pwell bottom and Pwell are kept connected through an unetched region, that is, a grounded contact is reserved, and gate bottom protection can be achieved.
In a preferred embodiment, the Pwell region 3 is connected to the sidewall of the trench region 32, and two of the Pwell regions are repeatedly arranged above the inside of the silicon carbide N epitaxy 8. As is apparent from fig. 1, the number of the Pwell areas 3 and the groove areas 32 that are sequentially and repeatedly arranged is 5, and in other embodiments, the number of the Pwell areas and the groove areas may be more, which is not described herein again.
As a preferred embodiment, said one Pplus region 4 is located in the middle of said two N + regions 2. It will be appreciated that this arrangement is for the purpose of constructing an NPN structure.
In a preferred embodiment, the gate oxide region 6 wraps the polysilicon region 5 in a semi-ring shape.
In a preferred embodiment, the lower portion of the gate oxide region 6 is connected to the upper portion of the PpplusBottom region 7.
Referring to fig. 2 for explaining the core inventive concept of the present invention, fig. 2 is a schematic structural diagram of an embodiment of the trench region during the preparation of the trench-type silicon carbide MOSFET prepared based on the buffer layer according to the present invention.
As shown in fig. 2, in the present invention, an injection buffer layer is applied during injection through the Pwell region 3 to form a Pwell bottom region 31 having a depth greater than that of the trench region 32, and then silicon carbide etching of the Pwell bottom region 31 is performed to leave a portion of Pwell bottom at the bottom of the trench, where the portion of Pwell bottom and the Pwell region 3 are kept in a connection state through an unetched region, that is, a grounded contact is kept; under the protection of the side wall of SiN or SiO2, carrying out enrichment injection on the Pwellbottom region 31 to form a Ppplussbottom region 7; the Pplusbottom region 7 keeps the same potential as the source electrode 10, so that the electric field of the gate oxide region 6 at the groove can be pinched off, and failure caused by strong gate oxide electric field is avoided.
To accurately illustrate how the trench type silicon carbide MOSFET fabricated based on the buffer layer according to the present invention is fabricated, please refer to fig. 3-11, and fig. 3-11 are schematic diagrams illustrating structural changes of the trench type silicon carbide MOSFET in the method for fabricating the trench type silicon carbide MOSFET fabricated based on the buffer layer according to the present invention.
In this embodiment, the method for preparing the trench type silicon carbide MOSFET based on the buffer layer includes the following steps:
depositing and injecting polysilicon into the buffer layer 33, and etching the buffer layer 33, as shown in fig. 3, wherein the thickness of the injected buffer layer determines the injection depth of the Pwell region 3, and the injected buffer layer 33 may be made of polysilicon or other silicide;
injecting Al ions for multiple times at high temperature to obtain a Pwell region 3 with the depth smaller than the depth of the groove and a Pwell bottom region 31 with the depth larger than the depth of the groove, as shown in FIG. 4;
silicon carbide is deposited by using silicon dioxide to etch the mask layer 34 and form an opening, wherein the size of the opening is greater than or equal to the depth of the PwellBottom region 31, as shown in FIG. 5; wherein, before depositing the silicon carbide, the injection buffer layer is selected to be removed or reserved, silicide or Ni metal can be selected according to the gas for etching the silicon carbide, and silicide, such as SiO2, is preferred for facilitating the subsequent process;
etching silicon carbide to form a silicon carbide trench, wherein the depth of the silicon carbide trench is less than that of the pwell bottom region 31, and a part of the pwell bottom region 31 is reserved at the bottom of the silicon carbide trench, as shown in fig. 6;
depositing silicon carbide and performing mask-free dry etching on the silicon carbide to obtain a groove with a silicon carbide protective layer 35, as shown in fig. 7;
performing Al ion enrichment implantation to form a pplus bottom region 7, as shown in fig. 8, it should be noted that this step is a core step of the present preparation method, since the etching mask layer 34 has an effect of blocking Al ions, the top Pwell region 3 is not implanted or only implanted shallowly, the implantation of the Pwell region 3 is balanced and adjusted by barrier layer and implantation energy, the bottom Pwell bottom region 31 can be enriched due to the existence of sidewall protection (silicon carbide protection layer 35) to form the pplus bottom region 7, since the pplus bottom region 7 is partially overlapped with the Pwell region 3, and the Pwell bottom region 31 is also overlapped with the Pwell region 3, the pplus bottom region 7 can be equipotentially connected with the Pwell region 3, the bottom of the trench can be protected, and the depth and concentration of the pplus bottom region 7 determine the protection effect;
removing the mask layer 34, only remaining the silicon carbide protective layer 35, continuing to perform Al ion enrichment implantation on the Pwell region 3, and simultaneously enriching the bottom pplustbottom region 7, as shown in fig. 9;
removing the silicon carbide protective layer 35 and selectively performing N + implantation on the Pplus region 4, and depositing a carbon film and performing high temperature annealing, followed by removing the carbon film, as shown in fig. 10;
preparing a gate oxide region 6 and a polysilicon region 5, as shown in fig. 11;
and then, carrying out isolation layer deposition, opening a source electrode 1 and carrying out ohmic metallization, and opening and metallization of Poly, forming a source electrode 1 and a grid electrode by etching metal, and forming a drain electrode 10 by back metallization to obtain the buffer layer-based trench type silicon carbide MOSFET, as shown in FIG. 1.
According to the groove type silicon carbide MOSFET prepared based on the buffer layer and the preparation method thereof, the injection buffer layer is applied during the Pwell injection to form the Pwell bottom with the depth larger than that of the groove, then the silicon carbide etching of the Pwell bottom area is carried out, so that part of the Pwell bottom is reserved at the bottom of the groove, and the Pwell bottom and the Pwell are in a connection state through an unetched area, namely, a grounded contact is reserved; under the protection of the side wall of SiN or SiO2, performing enrichment injection on Pwellbottom to form Ppplussbottom; the Ppplusbottom can pinch off the electric field of the gate oxide at the groove position because the homologous electrodes keep the equipotential, and the failure caused by the strong electric field of the gate oxide is avoided, so that the bottom of the grid of the groove type silicon carbide MOSFET can be effectively protected, the service life is prolonged, and the service life is prolonged.
The trench silicon carbide MOSFET prepared based on the buffer layer and the preparation method thereof provided by the invention are described in detail above, and the principle and the implementation mode of the invention are explained by applying specific examples, and the description of the above examples is only used for helping to understand the method and the core idea of the invention; meanwhile, for those skilled in the art, according to the idea of the present invention, there may be variations in the specific embodiments and the application scope, and in summary, the content of the present specification should not be construed as a limitation to the present invention.
Claims (5)
1. A preparation method of a groove type silicon carbide MOSFET prepared based on a buffer layer is characterized in that the groove type silicon carbide MOSFET prepared based on the buffer layer comprises the following steps:
a drain (10), a silicon carbide substrate (9) located above the drain (10), a silicon carbide N-epi (8) located above the silicon carbide substrate (9); the upper left side inside the silicon carbide N epitaxy (8) comprises a Pwell region (3), the Pwell region (3) comprises two N + regions (2) and one Pplus region (4) above, the upper right side inside the silicon carbide N epitaxy (8) comprises a groove region (32), and the groove region (32) comprises a Pplus bottom region (7), a gate oxide region (6) and a polysilicon region (5) from bottom to top; the two N + regions (2) and one Pplus region (4) comprise a source electrode (1) above;
wherein the depth of the PpplusBottom region (7) is greater than the depth of the Pwell region (3);
the preparation method of the groove type silicon carbide MOSFET based on the buffer layer preparation comprises the following steps:
depositing and injecting polycrystalline silicon into a buffer layer (33), and etching the buffer layer (33);
injecting Al ions at high temperature for multiple times to obtain a Pwell area (3) with the depth smaller than the depth of the groove and a Pwell bottom area (31) with the depth larger than the depth of the groove;
silicon carbide is deposited by utilizing silicon dioxide to etch the mask layer (34) and openings are formed, and the size of each opening is larger than or equal to the depth of the PwellBottom area (31);
etching silicon carbide to form a silicon carbide groove, wherein the depth of the silicon carbide groove is less than that of the Pwellbottom area (31), and a part of the Pwellbottom area (31) is reserved at the bottom of the silicon carbide groove;
depositing silicon carbide and carrying out mask-free dry etching on the silicon carbide to obtain a groove with a silicon carbide protective layer (35), wherein the silicon carbide protective layer (35) is formed on the side wall of the groove;
carrying out Al ion enrichment injection on a Pwellbottom region (31) at the bottom of the groove to form a Ppplussbottom region (7);
removing the mask layer (34), only keeping the silicon carbide protective layer (35), continuing to perform Al ion enrichment injection on the Pwell region (3) to form a Pplus region (4), and simultaneously enriching a Pplus bottm region (7) at the bottom;
removing the silicon carbide protective layer (35), selectively carrying out N + injection on the Pplus region (4), depositing a carbon film, carrying out high-temperature annealing, and then removing the carbon film;
preparing a gate oxide region (6) and a polysilicon region (5);
and then, carrying out isolation layer deposition, opening a source electrode (1), carrying out ohmic metallization, opening a Poly, carrying out metallization, forming a source electrode (1) and a grid electrode by etching the metal, and forming a drain electrode (10) by back metallization to obtain the buffer layer-based prepared groove type silicon carbide MOSFET.
2. The method of claim 1, wherein the Pwell region (3) is contiguous with the trench region (32) sidewalls and is repeatedly disposed two by two over the interior of the N-epi (8) of silicon carbide.
3. The method of claim 1, wherein the Ppll us region (4) is located in the middle of the two N + regions (2).
4. The method of claim 1, wherein the gate oxide region (6) is wrapped around the polysilicon region (5) in a semi-ring shape.
5. The method of claim 4, wherein the lower portion of the gate oxide region (6) is connected to the upper portion of the Ppluss bottom region (7).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210401030.8A CN114496783B (en) | 2022-04-18 | 2022-04-18 | Groove type silicon carbide MOSFET prepared based on buffer layer and preparation method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210401030.8A CN114496783B (en) | 2022-04-18 | 2022-04-18 | Groove type silicon carbide MOSFET prepared based on buffer layer and preparation method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN114496783A CN114496783A (en) | 2022-05-13 |
| CN114496783B true CN114496783B (en) | 2022-08-05 |
Family
ID=81489535
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202210401030.8A Active CN114496783B (en) | 2022-04-18 | 2022-04-18 | Groove type silicon carbide MOSFET prepared based on buffer layer and preparation method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN114496783B (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115188803B (en) * | 2022-09-09 | 2022-12-13 | 深圳芯能半导体技术有限公司 | Groove side wall gate silicon carbide MOSFET and preparation method thereof |
| CN115207092B (en) * | 2022-09-09 | 2022-12-13 | 深圳芯能半导体技术有限公司 | High-reliability trench side wall gate silicon carbide MOSFET and preparation method thereof |
| CN116344587A (en) * | 2023-04-26 | 2023-06-27 | 无锡新洁能股份有限公司 | Groove type silicon carbide MOSFET device and preparation process thereof |
Family Cites Families (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4033657B2 (en) * | 2001-10-09 | 2008-01-16 | シャープ株式会社 | Manufacturing method of semiconductor device |
| JP2006156441A (en) * | 2004-11-25 | 2006-06-15 | Nikon Corp | Ion implanter and ion implanting method |
| JP5721308B2 (en) * | 2008-03-26 | 2015-05-20 | ローム株式会社 | Semiconductor device |
| US20100035421A1 (en) * | 2008-08-06 | 2010-02-11 | Texas Instruments Incorporated | Semiconductor well implanted through partially blocking material pattern |
| CN203787451U (en) * | 2012-08-28 | 2014-08-20 | 璨圆光电股份有限公司 | Compound semiconductor element |
| JP6341074B2 (en) * | 2014-01-24 | 2018-06-13 | 株式会社デンソー | Manufacturing method of semiconductor device |
| JP6411929B2 (en) * | 2015-03-24 | 2018-10-24 | トヨタ自動車株式会社 | MOSFET |
| US10559652B2 (en) * | 2016-02-09 | 2020-02-11 | Mitsubishi Electric Corporation | Semiconductor device |
| US11271084B2 (en) * | 2017-06-06 | 2022-03-08 | Mitsubishi Electric Corporation | Semiconductor device and power converter |
| CN110176498B (en) * | 2019-04-30 | 2022-06-14 | 东南大学 | Low-on-resistance groove silicon carbide power device and manufacturing method thereof |
| CN113314613A (en) * | 2021-05-31 | 2021-08-27 | 电子科技大学 | Silicon carbide MOSFET device with avalanche charge transition buffer layer and preparation method |
-
2022
- 2022-04-18 CN CN202210401030.8A patent/CN114496783B/en active Active
Also Published As
| Publication number | Publication date |
|---|---|
| CN114496783A (en) | 2022-05-13 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN114496783B (en) | Groove type silicon carbide MOSFET prepared based on buffer layer and preparation method thereof | |
| JP6848317B2 (en) | Semiconductor devices and methods for manufacturing semiconductor devices | |
| US10680067B2 (en) | Silicon carbide MOSFET device and method for manufacturing the same | |
| KR100850689B1 (en) | Power mosfet and method of making the same | |
| EP2242107A1 (en) | Semiconductor device | |
| JP2007165657A (en) | Semiconductor device and manufacturing method therefor | |
| CN114496785B (en) | T-shaped bottom-protected groove-type silicon carbide MOSFET and preparation method thereof | |
| CN114975602B (en) | High-reliability IGBT chip and manufacturing method thereof | |
| US9953971B2 (en) | Insulated gate bipolar transistor (IGBT) and related methods | |
| CN114496784B (en) | Bottom protection grounding groove type silicon carbide MOSFET and preparation method thereof | |
| US6087224A (en) | Manufacture of trench-gate semiconductor devices | |
| CN114420745B (en) | Silicon carbide MOSFET and preparation method thereof | |
| CN114744044A (en) | Trench type silicon carbide MOSFET of triple-protection gate oxide layer and preparation method thereof | |
| CN114361242B (en) | Planar silicon carbide MOSFET (Metal-oxide-semiconductor field Effect transistor) capable of adjusting threshold voltage and preparation method thereof | |
| EP0996970B1 (en) | Manufacture of field-effect semiconductor devices | |
| JP3663657B2 (en) | Manufacturing method of semiconductor device | |
| JPH08255902A (en) | Insulated gate semiconductor device and fabrication thereof | |
| CN213459737U (en) | Novel power device with high dynamic latch-up resistance | |
| CN113053999B (en) | Metal oxide semiconductor transistor and preparation method thereof | |
| CN116779650B (en) | IGBT chip with large-area active region and manufacturing method thereof | |
| CN109065447B (en) | Power device chip and manufacturing method thereof | |
| CN118571920A (en) | Semiconductor device, electronic apparatus, and method for manufacturing semiconductor device | |
| CN109103180B (en) | Power device chip and manufacturing method thereof | |
| CN115377219A (en) | Silicon carbide trench MOSFET with negative voltage resistance grid and preparation method thereof | |
| CN114171386A (en) | Process optimization method for carrier storage groove gate bipolar transistor structure |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |