CN113314613A - Silicon carbide MOSFET device with avalanche charge transition buffer layer and preparation method - Google Patents
Silicon carbide MOSFET device with avalanche charge transition buffer layer and preparation method Download PDFInfo
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- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 title claims abstract description 33
- 229910010271 silicon carbide Inorganic materials 0.000 title claims abstract description 33
- 230000007704 transition Effects 0.000 title claims abstract description 13
- 238000002360 preparation method Methods 0.000 title description 3
- 238000000151 deposition Methods 0.000 claims abstract description 17
- -1 aluminum ions Chemical class 0.000 claims abstract description 13
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 13
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 12
- 229910052782 aluminium Inorganic materials 0.000 claims abstract description 10
- 229910052681 coesite Inorganic materials 0.000 claims abstract description 10
- 229910052906 cristobalite Inorganic materials 0.000 claims abstract description 10
- 239000000377 silicon dioxide Substances 0.000 claims abstract description 10
- 229910052682 stishovite Inorganic materials 0.000 claims abstract description 10
- 229910052905 tridymite Inorganic materials 0.000 claims abstract description 10
- 238000000137 annealing Methods 0.000 claims abstract description 8
- 230000000903 blocking effect Effects 0.000 claims abstract description 7
- IJGRMHOSHXDMSA-UHFFFAOYSA-N nitrogen Substances N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims abstract description 6
- 238000005530 etching Methods 0.000 claims abstract description 5
- 229910052757 nitrogen Inorganic materials 0.000 claims abstract description 5
- 230000003213 activating effect Effects 0.000 claims abstract description 4
- 238000002347 injection Methods 0.000 claims abstract description 4
- 239000007924 injection Substances 0.000 claims abstract description 4
- 238000004519 manufacturing process Methods 0.000 claims abstract description 4
- 229910052751 metal Inorganic materials 0.000 claims description 23
- 239000002184 metal Substances 0.000 claims description 23
- 239000000758 substrate Substances 0.000 claims description 12
- 238000005468 ion implantation Methods 0.000 claims description 8
- 229920005591 polysilicon Polymers 0.000 claims description 5
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 4
- 238000002955 isolation Methods 0.000 claims description 4
- 239000001301 oxygen Substances 0.000 claims description 4
- 229910052760 oxygen Inorganic materials 0.000 claims description 4
- 238000004140 cleaning Methods 0.000 claims description 3
- 238000000407 epitaxy Methods 0.000 claims description 3
- 230000001590 oxidative effect Effects 0.000 claims description 3
- 238000000059 patterning Methods 0.000 claims description 3
- 230000005684 electric field Effects 0.000 abstract description 5
- 238000009826 distribution Methods 0.000 abstract description 3
- 238000010586 diagram Methods 0.000 description 8
- 239000000463 material Substances 0.000 description 4
- 230000015556 catabolic process Effects 0.000 description 3
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- 238000000034 method Methods 0.000 description 3
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- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000009471 action Effects 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/0445—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising crystalline silicon carbide
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66053—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide
- H01L29/66068—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
Abstract
The invention provides a silicon carbide MOSFET device with an avalanche charge transition buffer layer and a manufacturing method thereof, wherein the manufacturing method comprises the following steps: injecting aluminum ions into the N-epitaxial layer to simultaneously form a P-type avalanche charge transit buffer layer and a P-type base region, wherein the injection depth passes through SiO2Regulating and controlling the thickness of the mask; injecting aluminum ions to form a P + ohmic contact region; injecting nitrogen ions to form an N + source region and activating and annealing; thermally growing a gate oxide layer and performing nitridation annealing; depositing and etching polycrystalline silicon; a plurality of electric field peak values are introduced below a P-type base region through a P-type avalanche charge transit buffer layer, when avalanche occurs on a device, avalanche charges are respectively released from the P-type avalanche charge transit buffer layer and the corners of the P-type base region, and the generated current is in discrete distribution, so that the rise of local temperature is greatly alleviated, and the avalanche capability of the device is improvedThe avalanche reliability of the silicon carbide MOSFET device in the blocking state is successfully enhanced.
Description
Technical Field
The invention belongs to the technical field of power semiconductors, and particularly relates to a silicon carbide MOSFET device with an avalanche charge transition buffer layer.
Background
Silicon Carbide (Silicon Carbide) material, which is one of the representative third-generation wide bandgap semiconductor materials, has a high breakdown field strength (4 × 10)6V/cm) and high saturated drift velocity (2 x 10)7cm/s), high thermal conductivity (490W/m.k), good thermal stability and the like, so that the material has wide application prospect in the fields of high-power, high-temperature and high-frequency power electronics.
MOSFETs are one of the most widely used devices in silicon carbide power devices, and have lower switching losses and higher frequency characteristics than bipolar devices because they have no charge storage effect. The power MOSFET is used as a voltage type control device, and has the characteristics of high input impedance, high switching speed, no secondary breakdown and the like, so that the power MOSFET is widely applied to a power electronic switching circuit.
With the recent acceptance of the advantages of silicon carbide MOSFETs, many semiconductor device manufacturers have introduced commercially available silicon carbide MOSFET devices. Silicon carbide MOSFETs on the market are mainly classified into planar gates and trench gates. The trench gate silicon carbide MOSFET eliminates a planar JFET region, thereby reducing the forward on-resistance; but the planar gate device has the advantages of simple process, lower cost, higher reliability and the like. With such a trend, reliability studies of silicon carbide MOSFET devices have become increasingly important. For the power silicon carbide MOSFET, due to the existence of inductive load and stray inductance, energy stored in the inductance is released through the power device at the moment of turning off the device, so that the device is forced to generate avalanche breakdown, and the device is very easy to fail due to high-voltage large-current impact generated at the moment, which is a serious challenge in applying the silicon carbide MOSFET to a power electronic system.
When the silicon carbide MOSFET is in reverse blocking, the N-drift region is used for depletion to bear high reverse bias, and the electric field peak appears at the corner of the P-type base region due to the curvature effect. After avalanche occurs in the device, a large amount of avalanche charges can be discharged through the corners of the P-type base region under the action of a strong electric field, and the current generated by the avalanche charge discharge causes local temperature rise, which may exceed the highest working temperature of the device, so that the device fails. Therefore, in order to improve the avalanche reliability of the device, it is necessary to slow down the temperature rise caused by the avalanche charge.
Disclosure of Invention
The invention aims to introduce a plurality of electric field peak values to buffer the release of avalanche charges, and provides a silicon carbide MOSFET device with an avalanche charge transition buffer layer and a preparation method thereof. An electric field peak value is introduced below the P-type base region through the P-type avalanche charge transition buffer layer, when avalanche occurs in the device, avalanche charges are respectively released from the P-type avalanche charge transition buffer layer and the corners of the P-type base region, and at the moment, currents generated by the avalanche charges are distributed discretely, so that local temperature rise caused by the avalanche charges is relieved, and the avalanche capability of the device is improved.
In order to achieve the purpose, the invention adopts the following technical scheme:
a silicon carbide MOSFET device with an avalanche charge transit buffer layer comprising a drain metal 6, an N + substrate 5 over the drain metal 6, an N-drift region 4 over the N + substrate 5; a gate dielectric 8 and a polysilicon gate 9 are arranged in the middle above the N-drift region 4; a P-type base region 3 is respectively arranged at the upper left part and the upper right part in the N-drift region 4, and a P-type avalanche charge transit buffer layer 31 is arranged below the P-type base region 3; the upper left P-type base region 3 comprises an upper left P + ohmic contact region 2 and an N + source region 7 on the right side of the P + ohmic contact region 2; the upper right P-type base region 3 comprises an upper right P + ohmic contact region 2 and an N + source region 7 on the left side of the P + ohmic contact region 2; a source metal 1 is arranged above the N + source region 7 and the P + ohmic contact region 2; the part of the P-type base region 3 close to the gate dielectric 8 is a channel of the device; the P-type avalanche charge transit buffer layer 31 is a plurality of separate sub-regions.
Preferably, the gate dielectric is SiO2。
Preferably, the P-type avalanche charge transit buffer layer 31, the P + ohmic contact region 2, the N + source region 7, and the P-type base region 3 are all formed by multiple ion implantations.
Preferably, the materials of the N-drift region 4, the N + substrate 5, the P-type avalanche charge transition buffer layer 31, the P + ohmic contact region 2, the N + source region 7 and the P-type base region 3 of the device are all silicon carbide.
To achieve the above object, the present invention further provides a method for manufacturing the silicon carbide MOSFET device with the avalanche charge transit buffer layer, comprising the following steps:
the first step is as follows: cleaning the epitaxial wafer, N-epitaxy with SiO2Injecting aluminum ions into the injection blocking layer to form a P-type avalanche charge transit buffer layer and a P-type base region;
the second step is that: injecting aluminum ions to form a P + ohmic contact region;
the third step: injecting nitrogen ions to form an N + source region and activating and annealing;
the fourth step: oxidizing the wet oxygen to generate a gate oxide layer;
the fifth step: depositing polycrystalline silicon, annealing after ion implantation and patterning the polycrystalline silicon;
and a sixth step: depositing a gate metal to form a gate electrode;
the seventh step: thermally growing an isolation oxide layer;
eighth step: etching SiO2Depositing source metal to form a source electrode;
the ninth step: and depositing drain metal to form an electrode.
The end of the device gate dielectric layer is a grid electrode, the bottom end of the N + substrate is a drain electrode, and the N + source region and the P + ohmic contact region are source electrodes;
the invention has the beneficial effects that: the invention adjusts the current distribution generated by the avalanche charges by introducing the P-type avalanche charge transition buffer layer, thereby slowing down the local temperature rise caused by the avalanche current, improving the avalanche capability of the device and enhancing the avalanche reliability of the silicon carbide MOSFET device in a blocking state.
Drawings
Fig. 1 is a schematic diagram of a silicon carbide MOSFET device having an avalanche charge transit buffer layer according to example 1 of the present invention;
FIG. 2 is a schematic diagram of SiO deposition on an epitaxial wafer according to example 2 of the present invention2Implanting aluminum ions to form a P-type avalanche charge transit buffer layer and a P-type base region;
FIG. 3 is a schematic diagram of forming a P + ohmic contact region by aluminum ion implantation in example 2 of the present invention;
FIG. 4 is a schematic diagram of N + source region formation by nitrogen ion implantation in example 2 of the present invention;
FIG. 5 is a schematic diagram of a wet oxygen oxidation to form a gate oxide layer according to embodiment 2 of the present invention;
FIG. 6 is a schematic diagram of depositing polysilicon and depositing gate metal to form a gate electrode according to embodiment 2 of the present invention;
FIG. 7 is a schematic view of a thermally grown isolation oxide layer according to embodiment 2 of the present invention;
FIG. 8 is a diagram of etching SiO in example 2 of the present invention2Depositing source metal to form a schematic diagram of a source electrode;
FIG. 9 is a schematic view of the deposited drain metal forming electrode of example 2 of the present invention;
1 is source metal, 2 is a P + ohmic contact region, 3 is a P-type base region, 31 is a P-type avalanche charge transit buffer layer, 4 is an N-drift region, 5 is an N + substrate, 6 is drain metal, 7 is an N + source region, 8 is a gate dielectric, and 9 is a polysilicon gate.
Detailed Description
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.
Example 1
As shown in fig. 1, a silicon carbide MOSFET device with an avalanche charge transit buffer comprises a drain metal 6, an N + substrate 5 over the drain metal 6, an N-drift region 4 over the N + substrate 5; a gate dielectric 8 and a polysilicon gate 9 are arranged in the middle above the N-drift region 4; a P-type base region 3 is respectively arranged at the upper left part and the upper right part in the N-drift region 4, and a P-type avalanche charge transit buffer layer 31 is arranged below the P-type base region 3; the upper left P-type base region 3 comprises an upper left P + ohmic contact region 2 and an N + source region 7 on the right side of the P + ohmic contact region 2; the upper right P-type base region 3 comprises an upper right P + ohmic contact region 2 and an N + source region 7 on the left side of the P + ohmic contact region 2; a source metal 1 is arranged above the N + source region 7 and the P + ohmic contact region 2; the part of the P-type base region 3 close to the gate dielectric 8 is a channel of the device; the P-type avalanche charge transit buffer layer 31 is a plurality of separate sub-regions.
The gate dielectric 8 is SiO2。
The P-type avalanche charge transition buffer layer 31, the P + ohmic contact region 2, the N + source region 7 and the P-type base region 3 are all formed by multiple times of ion implantation.
The N-drift region 4, the N + substrate 5, the P-type avalanche charge transit buffer layer 31, the P + ohmic contact region 2, the N + source region 7 and the P-type base region 3 of the device are all made of silicon carbide.
In other embodiments, the doping types in the device can be changed to opposite doping types, i.e., the P-type doping is changed to the N-type doping, and the N-type doping is changed to the P-type doping.
In the embodiment, the current distribution generated by the avalanche charges is adjusted by introducing the P-type avalanche charge transition buffer layer, so that the local temperature rise caused by the avalanche current is slowed down, the avalanche capability of the device is improved, and the avalanche reliability of the silicon carbide MOSFET device in a blocking state is enhanced.
Example 2
As shown in fig. 2-9, the present embodiment provides a method for fabricating the above-mentioned silicon carbide MOSFET device with an avalanche charge transit buffer layer, comprising the steps of:
the first step is as follows: cleaning the epitaxial wafer, N-epitaxy with SiO2Injecting aluminum ions into the injection blocking layer to form a P-type avalanche charge transit buffer layer and a P-type base region;
the second step is that: injecting aluminum ions to form a P + ohmic contact region;
the third step: injecting nitrogen ions to form an N + source region and activating and annealing;
the fourth step: oxidizing the wet oxygen to generate a gate oxide layer;
the fifth step: depositing polycrystalline silicon, annealing after ion implantation and patterning the polycrystalline silicon;
and a sixth step: depositing a gate metal to form a gate electrode;
the seventh step: thermally growing an isolation oxide layer;
eighth step: etching SiO2Depositing source metal to form a source electrode;
the ninth step: and depositing drain metal to form an electrode.
The end of the device gate dielectric layer is a grid electrode, the bottom end of the N + substrate is a drain electrode, and the N + source region and the P + ohmic contact region are source electrodes;
the foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.
Claims (6)
1. A silicon carbide MOSFET device having an avalanche charge transit buffer, characterized by: comprises drain metal (6), an N + substrate (5) above the drain metal (6), and an N-drift region (4) above the N + substrate (5); a gate dielectric (8) and a polysilicon gate (9) are arranged in the middle above the N-drift region (4); a P-type base region (3) is respectively arranged at the upper left part and the upper right part in the N-drift region (4), and a P-type avalanche charge transit buffer layer (31) is arranged below the P-type base region (3); the upper left P-type base region (3) internally comprises an upper left P + ohmic contact region (2) and an N + source region (7) on the right side of the P + ohmic contact region (2); the upper right P-type base region (3) internally comprises an upper right P + ohmic contact region (2) and an N + source region (7) on the left side of the P + ohmic contact region (2); a source metal (1) is arranged above the N + source region (7) and the P + ohmic contact region (2); the part of the P-type base region (3) close to the gate dielectric (8) is a channel of the device; the P-type avalanche charge transit buffer layer (31) is a plurality of separate subregions.
2. The silicon carbide MOSFET device with an avalanche charge transit buffer as claimed in claim 1, wherein: the gate dielectric (8) is SiO2。
3. The silicon carbide MOSFET device with an avalanche charge transit buffer as claimed in claim 1, wherein: the P-type avalanche charge transition buffer layer (31), the P + ohmic contact region (2), the N + source region (7) and the P-type base region (3) are formed by multiple times of ion implantation.
4. The silicon carbide MOSFET device with an avalanche charge transit buffer as claimed in claim 1, wherein: the N-drift region (4), the N + substrate (5), the P-type avalanche charge transition buffer layer (31), the P + ohmic contact region (2), the N + source region (7) and the P-type base region (3) of the device are all made of silicon carbide.
5. The silicon carbide MOSFET device with an avalanche charge transit buffer layer as claimed in any one of claims 1 to 4, wherein: each doping type in the device can be correspondingly changed into opposite doping, namely P-type doping is changed into N-type doping, and simultaneously N-type doping is changed into P-type doping.
6. The method of fabricating a silicon carbide MOSFET device with an avalanche charge transit buffer as claimed in any one of claims 1 to 5, comprising the steps of:
the first step is as follows: cleaning the epitaxial wafer, N-epitaxy with SiO2Injecting aluminum ions into the injection blocking layer to form a P-type avalanche charge transit buffer layer and a P-type base region;
the second step is that: injecting aluminum ions to form a P + ohmic contact region;
the third step: injecting nitrogen ions to form an N + source region and activating and annealing;
the fourth step: oxidizing the wet oxygen to generate a gate oxide layer;
the fifth step: depositing polycrystalline silicon, annealing after ion implantation and patterning the polycrystalline silicon;
and a sixth step: depositing a gate metal to form a gate electrode;
the seventh step: thermally growing an isolation oxide layer;
eighth step: etching SiO2Depositing source metal to form a source electrode;
the ninth step: and depositing drain metal to form an electrode.
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN114496784A (en) * | 2022-04-18 | 2022-05-13 | 深圳芯能半导体技术有限公司 | Bottom protection grounding groove type silicon carbide MOSFET and preparation method thereof |
| CN114496783A (en) * | 2022-04-18 | 2022-05-13 | 深圳芯能半导体技术有限公司 | Groove type silicon carbide MOSFET prepared based on buffer layer and preparation method thereof |
| CN114496785A (en) * | 2022-04-18 | 2022-05-13 | 深圳芯能半导体技术有限公司 | T-shaped bottom-protected groove-type silicon carbide MOSFET and preparation method thereof |
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Application publication date: 20210827 |