CN114843332A - Low-power-consumption high-reliability half-packaged trench gate MOSFET device and preparation method thereof - Google Patents
Low-power-consumption high-reliability half-packaged trench gate MOSFET device and preparation method thereof Download PDFInfo
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- 238000002360 preparation method Methods 0.000 title abstract description 8
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 claims abstract description 43
- 229910010271 silicon carbide Inorganic materials 0.000 claims abstract description 43
- 239000000758 substrate Substances 0.000 claims abstract description 25
- 238000005530 etching Methods 0.000 claims description 15
- -1 aluminum ions Chemical class 0.000 claims description 12
- 238000000137 annealing Methods 0.000 claims description 12
- 230000004888 barrier function Effects 0.000 claims description 12
- 238000002347 injection Methods 0.000 claims description 12
- 239000007924 injection Substances 0.000 claims description 12
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 12
- 229910052782 aluminium Inorganic materials 0.000 claims description 9
- 230000004913 activation Effects 0.000 claims description 8
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 8
- 238000000151 deposition Methods 0.000 claims description 8
- 238000005468 ion implantation Methods 0.000 claims description 8
- 230000003647 oxidation Effects 0.000 claims description 8
- 238000007254 oxidation reaction Methods 0.000 claims description 8
- 239000001301 oxygen Substances 0.000 claims description 8
- 229910052760 oxygen Inorganic materials 0.000 claims description 8
- 238000000034 method Methods 0.000 claims description 5
- 229920005591 polysilicon Polymers 0.000 claims description 5
- 229910052751 metal Inorganic materials 0.000 claims description 4
- 239000002184 metal Substances 0.000 claims description 4
- 239000012299 nitrogen atmosphere Substances 0.000 claims description 4
- 238000000059 patterning Methods 0.000 claims description 4
- 239000004065 semiconductor Substances 0.000 claims description 4
- 229910004298 SiO 2 Inorganic materials 0.000 claims description 3
- 238000004140 cleaning Methods 0.000 claims description 3
- 238000000407 epitaxy Methods 0.000 claims description 3
- IJGRMHOSHXDMSA-UHFFFAOYSA-N nitrogen Substances N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 3
- 229910052757 nitrogen Inorganic materials 0.000 claims description 3
- 230000008901 benefit Effects 0.000 abstract description 5
- 238000004519 manufacturing process Methods 0.000 description 13
- 230000005684 electric field Effects 0.000 description 7
- 238000010586 diagram Methods 0.000 description 6
- 230000000694 effects Effects 0.000 description 6
- 239000003989 dielectric material Substances 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 230000001413 cellular effect Effects 0.000 description 2
- 230000036961 partial effect Effects 0.000 description 2
- 230000008569 process Effects 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 230000002860 competitive effect Effects 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 230000002708 enhancing effect Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 230000007246 mechanism Effects 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000002210 silicon-based material Substances 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
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- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
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- Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
Abstract
The invention provides a low-power-consumption high-reliability semi-packaged trench gate silicon carbide MOSFET device and a preparation method thereof, wherein the preparation method comprises the following steps: the device comprises an N-type substrate, an N-type epitaxial layer, a first P-body region, a first P + contact region, a first N + contact region, a second P-body region, a second P + contact region, a second N + contact region, a gate medium, a trench gate, a secondary trench gate, a source electrode and a drain electrode; compared with the traditional semi-packaged trench gate silicon carbide MOSFET, the trench gate silicon carbide MOSFET has the advantages that the second P-body region is formed at the bottom of the trench to protect the gate dielectric, the reliability of the gate dielectric of the device is enhanced on the basis of not sacrificing the conduction capability of the original trench MOSFET, part of gate leakage capacitance is shielded, the switching loss of the device is reduced, when the device is in short circuit, the drain voltage is higher, and at the moment, the JFET region between the second P-body region and the first P + contact region is pinched off, so that the saturation current of the device is reduced, and the short circuit capability of the device is improved.
Description
Technical Field
The invention belongs to the technical field of power semiconductor devices, and particularly relates to a low-power-consumption high-reliability semi-packaged trench gate silicon carbide MOSFET device and a preparation method thereof.
Background
As one of the representatives of the third generation wide bandgap semiconductor materials, Silicon Carbide (Silicon Carbide) materials have the advantages of wider bandgap width (3 times), higher critical electric field (10 times), higher carrier saturation drift velocity (2 times), higher thermal conductivity (2.5 times) and the like than Silicon materials, are excellent materials for preparing high-voltage power electronic devices, and have wide application prospects in the fields of high-power, high-temperature, high-voltage and anti-irradiation power electronics.
MOSFETs are the most widely used type of gate-controlled devices in silicon carbide power devices. Because the silicon carbide MOSFET is a device characterized by a unipolar transport operation mechanism, only one of electrons or holes conducts electricity, and no charge storage effect exists, the silicon carbide MOSFET becomes a new generation of a competitive low-loss power device due to the fact that the silicon carbide MOSFET can achieve lower switching loss and higher frequency characteristics compared with a bipolar device, and due to the low on-resistance and excellent high-temperature characteristics of the silicon carbide MOSFET. Silicon carbide MOSFETs that have been commercialized to date have two main types of structures: trench gate type and planar type. In the planar type, due to the limitation of process precision, the on-resistance is larger and the integration level is lower. The groove-type silicon carbide MOSFET effectively improves the channel density by using the groove gate, but when the device is resistant to voltage, an extremely high peak electric field exists at the corner of the gate dielectric layer due to the curvature effect, and the reliability of the gate dielectric layer is reduced due to long-time work.
In order to reduce the electric field intensity near the gate dielectric layer when the device is blocked and improve the reliability of the dielectric layer, a common solution is to sacrifice the channel on one side of the trench gate and form a grounded P + shielding layer at the bottom of the trench, i.e. a conventional half-wrapped trench gate silicon carbide MOSFET. Although the traditional half-wrapped trench gate MOSFET can ensure that the gate dielectric is protected strongly and the reliability of the gate dielectric of the device is improved, half of the channel density is sacrificed, so that the on-resistance of the device is increased and the conduction loss is increased.
When the device is short-circuited, compared with a silicon-based device of the same quantity level, the silicon carbide MOSFET bears stronger electrothermal stress in a short-circuit state due to smaller chip area and larger current density. Therefore, the design requirements of the short-circuit reinforced silicon carbide MOSFET are more urgent.
Disclosure of Invention
The invention aims to provide a low-power-consumption high-reliability semi-wrapped trench gate silicon carbide MOSFET device and a preparation method thereof. Due to the shielding effect of the second P-body region on the electric field at the tail end of the channel, the reverse channel of the device can be shortened, the on-resistance of the device is greatly reduced due to the short channel, and the on-loss of the device is reduced. When the device is in short circuit, the drain electrode voltage is larger, and at the moment, the JFET area between the second P-body area and the first P + contact area is pinched off, so that the saturation current of the device is reduced, the short-circuit capability of the device is improved, and the reliability of the device is enhanced.
In order to achieve the purpose, the technical scheme of the invention is as follows:
a low power consumption high reliability half-wrapped trench gate silicon carbide MOSFET device, comprising: an N-type substrate 12, an N-type epitaxial layer 11 positioned above the N-type substrate 12, a second P-body region 10 positioned above the N-type epitaxial layer 11, a second P + contact region 8 and a second N + contact region 9 positioned inside the second P-body region 10, a first source electrode 1 positioned above the second P + contact region 8 and the second N + contact region 9 and forming ohmic contact with the second P + contact region 8 and the second N + contact region 9, a gate dielectric 7 positioned on the left side and the right side above the second P-body region 10, a trench gate 2 positioned inside the gate dielectric 7 on the left side, a sub-trench gate 3 positioned inside the gate dielectric 7 on the right side, first P + contact regions 4 positioned on two sides of the second P-body region 10 positioned above the first source electrode 1, a first N + contact region 5 positioned between the first P + contact region 4 on the left side and the gate dielectric 7 on the left side of the device, and a second N + contact region 5 positioned between the first P + contact region 4 on the left side and the gate dielectric 7 on the left side of the device, A first P-body region 6 located under the first N + contact region 5, a drain 13 located under the device and forming an ohmic contact with the N-type substrate 12.
As a preferred mode, the first source electrode 1 is T-shaped, and includes a horizontal segment of the first source electrode 1 and a vertical segment of the first source electrode 1, the horizontal segment of the first source electrode 1 is located above the first P + contact region 4, the first N + contact region 5, and the gate dielectric 7, the vertical segment of the first source electrode 2 is located between the left and right gate dielectrics 7, the horizontal segment of the first source electrode 1 forms ohmic contact with the first P + contact regions 4 on both sides of the device and the first N + contact region 5 on the left side, and the vertical segment of the first source electrode 1 forms ohmic contact with the second P + contact region 9 and the second N + contact region 8.
Preferably, the gate dielectric 7 is SiO 2 Or a high K dielectric.
Preferably, each doping type in the device is correspondingly changed into opposite doping, namely, the P-type doping is changed into the N-type doping, and meanwhile, the N-type doping is changed into the P-type doping.
The invention also provides a preparation method of the half-wrapped trench gate silicon carbide MOSFET device with low power consumption and high reliability, which comprises the following steps:
the first step is as follows: cleaning the epitaxial wafer, and injecting aluminum ions on the N-epitaxy by taking the oxide layer as an injection barrier layer to form a second P-body region;
the second step is that: injecting nitrogen ions by taking the oxide layer as an injection barrier layer to form a second N + contact region;
the third step: injecting aluminum ions by taking the oxide layer as an injection barrier layer to form a second P + contact region;
the fourth step: growing SiC epitaxially;
the fifth step: injecting aluminum ions by taking the oxide layer as an injection barrier layer to form a second P-body region activation annealing;
and a sixth step: growing SiC in an epitaxial manner;
the seventh step: etching the groove;
eighth step: generating a gate oxide layer by dry oxygen oxidation, annealing in a nitrogen atmosphere and patterning the gate oxide;
the ninth step: depositing polycrystalline silicon and etching the polycrystalline silicon;
the tenth step: isolating the polysilicon by wet oxygen oxidation;
the eleventh step: ion implantation is carried out to form a first P-body area, a first P + contact area and a first N + contact area, and activation annealing is carried out;
a twelfth step: etching the gate oxide at the bottom of the trench;
the thirteenth step: and depositing and etching the drain electrode, the source electrode and the grid electrode metal to form an ohmic contact electrode.
Preferably, a second source electrode 14 separated from the first source electrode 1 is arranged above the N-type epitaxial layer 11, the second source electrode 14 is arranged above the first P + contact region 4, and the second source electrode 14 forms schottky contact with the N-type substrate 11.
The invention also provides a second low-power-consumption high-reliability half-packaged trench gate silicon carbide MOSFET device, which comprises: an N-type substrate 12, an N-type epitaxial layer 11 positioned above the N-type substrate 12, second P-body regions 10 positioned at the left side and the right side above the N-type epitaxial layer 11, a second P + contact region 8 and a second N + contact region 9 positioned inside the second P-body region 10, a source electrode 1 positioned above the second P + contact region 8 and the second N + contact region 9, a gate medium 7 arranged at the middle part above the N-type epitaxial layer 11, a trench gate 2 is arranged in the gate dielectric 7 in the middle, a gate dielectric 7 and an auxiliary trench gate 3 in the gate dielectric 7 are arranged above the second P-body regions 10 on the left side and the right side respectively, a first P + contact region 4 and a first N + contact region 5 are arranged between the gate dielectric 7 in the middle and the gate dielectrics 7 on the two sides below the source electrode 1, a first P-body region 6 is arranged below the first N + contact region 5, and a drain electrode 13 is arranged below the device and forms ohmic contact with an N-type substrate 12; the source electrode 1 forms ohmic contact with the first P + contact region 4, the first N + contact region 5, the second P + contact region 8, and the second N + contact region 9.
The polycrystalline silicon end of the device is a grid electrode, the bottom end of the N + substrate is a drain electrode, and the N + contact area and the P + contact area are source electrodes.
The invention has the beneficial effects that: 1: on the basis of not reducing the number of cellular channels and reducing the conduction capability of the device, the silicon carbide MOSFET device forms a second P-body region at the bottom of the groove to protect the groove gate, so that the reliability of the gate medium of the device is enhanced, partial gate-drain capacitance is shielded, and the switching loss of the device is reduced; 2: due to the shielding effect of the second P-body region on the electric field at the tail end of the channel, the reverse channel of the device can be shortened, the on-resistance of the device is greatly reduced due to the short channel, and the conduction loss is reduced; 3: when the device is short-circuited, the drain voltage is higher, and at this time, the JFET region between the second P-body region 10 and the first P + contact region 4 is pinched off, so that the saturation current of the device is reduced, the short-circuit capability of the device is improved, and the reliability of the device is enhanced.
Drawings
FIG. 1 is a schematic diagram of a conventional asymmetric trench gate silicon carbide MOSFET device structure;
FIG. 2 is a schematic view of the device structure of embodiment 1 of the present invention;
FIG. 3 is a schematic view showing the formation of a second P-body region by ion implantation on an N-epi in the manufacturing method of example 1 of the present invention;
FIG. 4 is a schematic view of ion implantation on an N-epi to form a second N + contact region in the manufacturing method of embodiment 1 of the present invention;
FIG. 5 is a schematic view of ion implantation on an N-epi to form a second P + contact region in the manufacturing method of embodiment 1 of the present invention;
FIG. 6 is a schematic view showing an epitaxial SiC growth in the production method in example 1 of the present invention;
FIG. 7 is a schematic view showing the formation of a second P-body region by ion implantation and activation annealing in the manufacturing method of example 1 of the present invention;
FIG. 8 is a schematic view showing SiC epitaxial growth in the production method in example 1 of the present invention;
FIG. 9 is a schematic diagram showing a trench etched in the manufacturing method of embodiment 1 of the present invention;
FIG. 10 is a schematic diagram showing a gate oxide layer formed by dry oxygen oxidation, annealing in a nitrogen atmosphere and patterning the gate oxide layer in the manufacturing method of example 1 of the present invention;
FIG. 11 is a schematic view showing deposition and etching of polysilicon in the manufacturing method of embodiment 1 of the present invention;
FIG. 12 is a schematic view of a wet oxygen oxidation isolation polysilicon in the production method in example 1 of the present invention;
FIG. 13 is a schematic view of a process of forming a first P-body region, a first P + contact region, and a first N + contact region by ion implantation and activation annealing in the manufacturing method of embodiment 1 of the present invention;
FIG. 14 is a schematic diagram of etching a trench bottom gate oxide in the manufacturing method according to embodiment 1 of the present invention;
FIG. 15 is a schematic diagram of ohmic contact electrodes formed by depositing and etching drain, source and gate metals in the manufacturing method of embodiment 1 of the present invention;
FIG. 16 is a schematic view of the device structure of embodiment 2 of the present invention;
fig. 17 is a schematic diagram of a conventional double trench gate silicon carbide MOSFET device structure;
fig. 18 is a schematic view of the device structure of embodiment 3 of the present invention.
The structure of the semiconductor device comprises a substrate, a first source electrode 1, a trench gate 2, a sub-trench gate 3, a first P + contact region 4, a first N + contact region 5, a first P-body region 6, a gate dielectric 7, a second P + contact region 8, a second N + contact region 9, a second P-body region 10, an N-type epitaxial layer 11, an N-type substrate 12, a drain electrode 13 and a second source electrode 14.
Detailed Description
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.
Example 1
As shown in fig. 2, a low power consumption half-wrapped trench gate silicon carbide MOSFET device of the present embodiment includes: an N-type substrate 12, an N-type epitaxial layer 11 positioned above the N-type substrate 12, a second P-body region 10 positioned above the N-type epitaxial layer 11, a second P + contact region 8 and a second N + contact region 9 positioned inside the second P-body region 10, a first source electrode 1 positioned above the second P + contact region 8 and the second N + contact region 9 and forming ohmic contact with the second P + contact region 8 and the second N + contact region 9, a gate dielectric 7 positioned on the left side above the second P-body region 10 and a gate dielectric 7 positioned on the right side, a trench gate 2 positioned inside the gate dielectric 7 on the left side, a sub-trench gate 3 positioned inside the gate dielectric 7 on the right side, first P + contact regions 4 positioned on two sides of the second P-body region 10 below the first source electrode 1, a first N + contact region 5 positioned between the first P + contact region 4 on the left side of the device and the gate dielectric 7 on the left side of the device, and a second N + contact region 5 positioned between the first P + contact regions 4 and the gate dielectric 7 on the left side of the device, A first P-body region 6 located under the first N + contact region 5, a drain 13 located under the device and forming an ohmic contact with the N-type substrate 12.
The first source electrode 1 is T-shaped and comprises a horizontal section of the first source electrode 1 and a vertical section of the first source electrode 1, the horizontal section of the first source electrode 1 is positioned above a first P + contact area 4, a first N + contact area 5 and a gate medium 7, the vertical section of the first source electrode 1 is positioned between the left gate medium 7 and the right gate medium 7, ohmic contacts are formed between the horizontal section of the first source electrode 1 and the first P + contact areas 4 and the first N + contact area 5 on the left side of the first source electrode 1 on two sides of a device, and ohmic contacts are formed between the vertical section of the first source electrode 1 and a second P + contact area 9 and a second N + contact area 8.
The gate dielectric 7 is SiO 2 Or a high K dielectric.
The doping types in the device are correspondingly changed into opposite doping, namely P-type doping is changed into N-type doping, and simultaneously N-type doping is changed into P-type doping.
The working principle of the embodiment is as follows: when the device works in a reverse blocking state, the second P-body region 10 wraps and protects the gate dielectric 7, so that the electric field borne by the device gate dielectric 7 is obviously reduced, and the reliability of the device gate dielectric is improved.
When the device works in the on state, the probability of punch-through breakdown of the second P-body region 10 is reduced due to the wrapping and protection of the second P-body region 10 to the gate dielectric 7, and therefore, the channel of the second P-body region can be made very short, so that the on resistance and the on loss of the device are greatly reduced.
When the device performs a switching operation, the switching loss of the device is reduced due to the existence of the fin-shaped gate structure and the shielding of part of the gate-drain capacitance by the second P-body region.
When the device is short-circuited, the drain voltage is higher, and at this time, the JFET region between the second P-body region 10 and the first P + contact region 4 is pinched off, so that the saturation current of the device is reduced, the short-circuit capability of the device is improved, and the reliability of the device is enhanced.
The embodiment also provides a preparation method of the low-power-consumption high-reliability half-packaged trench gate silicon carbide MOSFET device, which comprises the following steps:
the first step is as follows: cleaning the epitaxial wafer, and injecting aluminum ions on the N-epitaxy by taking the oxide layer as an injection barrier layer to form a second P-body area;
the second step is that: injecting nitrogen ions by taking the oxide layer as an injection barrier layer to form a second N + contact region;
the third step: injecting aluminum ions by taking the oxide layer as an injection barrier layer to form a second P + contact region;
the fourth step: growing SiC epitaxially;
the fifth step: injecting aluminum ions by taking the oxide layer as an injection barrier layer to form a second P-body region activation annealing;
and a sixth step: growing SiC epitaxially;
the seventh step: etching the groove;
eighth step: generating a gate oxide layer by dry oxygen oxidation, annealing in a nitrogen atmosphere and patterning the gate oxide;
the ninth step: depositing polycrystalline silicon and etching the polycrystalline silicon;
the tenth step: isolating the polysilicon by wet oxygen oxidation;
the eleventh step: ion implantation is carried out to form a first P-body area, a first P + contact area and a first N + contact area, and activation annealing is carried out;
the twelfth step: etching the gate oxide at the bottom of the trench;
the thirteenth step: and depositing and etching the drain electrode, the source electrode and the grid electrode metal to form an ohmic contact electrode.
Example 2
As shown in fig. 16, the device structure of the present embodiment differs from that of embodiment 1 in that: a second source electrode 14 separated from the first source electrode 1 is arranged above the N-type epitaxial layer 11, the second source electrode 14 is positioned above the first P + contact region 4, and the second source electrode 14 and the N-type substrate 11 form Schottky contact. The benefits of this are: a Schottky contact is formed between the second source electrode 14 and the N-type epitaxial layer 11, an SBD diode is provided for the MOSFET, the body diode is prevented from being started to enable the MOSFET to enter a bipolar conduction mode when the third quadrant of the MOSFET works, the follow current capability of the third quadrant of the MOSFET is enhanced, and the reliability of the MOSFET is improved; when the SBD is reversely biased, the JFET formed between the first P + contact region 4 and the second P-body region 10 is pinched off, so that the leakage current of the SBD is reduced, and the loss of the device is further reduced.
Example 3
As shown in fig. 18, a low power consumption trench gate silicon carbide MOSFET device of the present embodiment includes: an N-type substrate 12, an N-type epitaxial layer 11 positioned above the N-type substrate 12, second P-body regions 10 positioned at the left side and the right side above the N-type epitaxial layer 11, a second P + contact region 8 and a second N + contact region 9 positioned inside the second P-body region 10, a source electrode 1 positioned above the second P + contact region 8 and the second N + contact region 9, a gate medium 7 arranged at the middle part above the N-type epitaxial layer 11, a trench gate 2 is arranged in the gate dielectric 7 in the middle, a gate dielectric 7 and an auxiliary trench gate 3 in the gate dielectric 7 are arranged above the second P-body regions 10 on the left side and the right side respectively, a first P + contact region 4 and a first N + contact region 5 are arranged between the gate dielectric 7 in the middle and the gate dielectrics 7 on the two sides below the source electrode 1, a first P-body region 6 is arranged below the first N + contact region 5, and a drain electrode 13 is arranged below the device and forms ohmic contact with an N-type substrate 12; the source electrode 1 forms ohmic contact with the first P + contact region 4, the first N + contact region 5, the second P + contact region 8, and the second N + contact region 9.
Example 3 the addition of a sub-trench gate 3, a second P + contact region 8, a second N + contact region 9 and a second P-body region 10 is based on a conventional double trench silicon carbide MOSFET device. The benefits of this are: 1: on the basis of not reducing the number of cellular channels and reducing the conduction capability of the device, the silicon carbide MOSFET device forms a second P-body region at the bottom of the source groove to protect the groove gate, so that the reliability of the gate medium of the device is enhanced, partial gate-drain capacitance is shielded, and the switching loss of the device is reduced; 2: due to the shielding effect of the second P-body region on the electric field at the tail end of the channel, the reverse channel of the device can be shortened, the on-resistance of the device is greatly reduced due to the short channel, and the conduction loss is reduced; 3: when the device is short-circuited, the drain voltage is higher, and at this time, the JFET region between the second P-body region 10 and the first P-body region 6 is pinched off, thereby reducing the saturation current of the device, improving the short-circuit capability of the device, and enhancing the reliability of the device.
Claims (7)
1. A low-power consumption high reliability half-package trench gate silicon carbide MOSFET device is characterized by comprising: the semiconductor device comprises an N-type substrate (12), an N-type epitaxial layer (11) positioned above the N-type substrate (12), a second P-body region (10) positioned above the N-type epitaxial layer (11), a second P + contact region (8) and a second N + contact region (9) positioned inside the second P-body region (10), a first source electrode (1) positioned above the second P + contact region (8) and the second N + contact region (9) and forming ohmic contact with the second P + contact region (8) and the second N + contact region (9), a gate medium (7) positioned on the left side above the second P-body region (10) and a gate medium (7) positioned on the right side, a trench gate (2) positioned inside the gate medium (7) on the left side, a sub-trench gate (3) positioned inside the gate medium (7) on the right side, and a first P + contact region (4) positioned on two sides of the second P-body region (10) below the first source electrode (1), The device comprises a first N + contact area (5) positioned between a first P + contact area (4) on the left side of the device and a gate dielectric (7) on the left side of the device, a first P-body area (6) positioned below the first N + contact area (5), and a drain electrode (13) positioned below the device and forming ohmic contact with an N-type substrate (12).
2. The low power consumption high reliability half-wrapped trench gate silicon carbide MOSFET device of claim 1, wherein: the first source electrode (1) is T-shaped and comprises a first source electrode (1) horizontal section and a first source electrode (1) vertical section, the first source electrode (1) horizontal section is located above a first P + contact area (4), a first N + contact area (5) and a grid medium (7), the first source electrode (2) vertical section is located between a left grid medium (7) and a right grid medium (7), the first source electrode (1) horizontal section forms ohmic contact with the first P + contact area (4) on two sides of a device and the first N + contact area (5) on the left side, and the first source electrode (1) vertical section forms ohmic contact with a second P + contact area (9) and a second N + contact area (8).
3. A low power consumption high reliability half-wrapped trench gate silicon carbide MOSFET device according to claim 1 or 2, wherein: the gate dielectric (7) is SiO 2 Or a high K dielectric.
4. A low power consumption high reliability half-wrapped trench gate silicon carbide MOSFET device according to claim 1 or 2, wherein: the doping types in the device are correspondingly changed into opposite doping, namely P-type doping is changed into N-type doping, and simultaneously N-type doping is changed into P-type doping.
5. The method for preparing the low-power-consumption high-reliability half-packaged trench gate silicon carbide MOSFET device as claimed in claim 1 or 2, wherein the method comprises the following steps:
the first step is as follows: cleaning the epitaxial wafer, and injecting aluminum ions on the N-epitaxy by taking the oxide layer as an injection barrier layer to form a second P-body area;
the second step is that: injecting nitrogen ions by taking the oxide layer as an injection barrier layer to form a second N + contact region;
the third step: injecting aluminum ions by taking the oxide layer as an injection barrier layer to form a second P + contact region;
the fourth step: growing SiC epitaxially;
the fifth step: injecting aluminum ions by taking the oxide layer as an injection barrier layer to form a second P-body region activation annealing;
and a sixth step: growing SiC epitaxially;
the seventh step: etching the groove;
eighth step: generating a gate oxide layer by dry oxygen oxidation, annealing in a nitrogen atmosphere and patterning the gate oxide;
the ninth step: depositing polycrystalline silicon and etching the polycrystalline silicon;
the tenth step: isolating the polysilicon by wet oxygen oxidation;
the eleventh step: ion implantation is carried out to form a first P-body area, a first P + contact area and a first N + contact area, and activation annealing is carried out;
the twelfth step: etching the gate oxide at the bottom of the trench;
the thirteenth step: and depositing and etching the drain electrode, the source electrode and the grid electrode metal to form an ohmic contact electrode.
6. The low power consumption high reliability half-wrapped trench gate silicon carbide MOSFET device of claim 1, wherein: and a second source electrode (14) separated from the first source electrode (1) is arranged above the N-type epitaxial layer (11), the second source electrode (14) is positioned above the first P + contact region (4), and the second source electrode (14) and the N-type substrate (11) form Schottky contact.
7. The utility model provides a low-power consumption high reliability half wraps trench gate silicon carbide MOSFET device which characterized in that: the method comprises the following steps: an N-type substrate (12), an N-type epitaxial layer (11) positioned above the N-type substrate (12), second P-body regions (10) positioned at the left side and the right side above the N-type epitaxial layer (11), a second P + contact region (8) and a second N + contact region (9) positioned inside the second P-body region (10), a source electrode (1) positioned above the second P + contact region (8) and the second N + contact region (9), a gate medium (7) is arranged in the middle above the N-type epitaxial layer (11), a trench gate (2) is arranged inside the gate medium (7) in the middle, a gate medium (7) and a sub-trench gate (3) inside the gate medium (7) are respectively arranged above the second P-body regions (10) at the left side and the right side, a first P + contact region (4) and a first N + contact region (5) are arranged between the gate medium (7) in the middle below the source electrode (1) and the gate mediums (7) at the two sides, a first P-body region (6) is arranged below the first N + contact region (5), and a drain electrode (13) is arranged below the device and forms ohmic contact with the N-type substrate (12); the source electrode (1) forms ohmic contact with the first P + contact region (4), the first N + contact region (5), the second P + contact region (8) and the second N + contact region (9).
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116581150A (en) * | 2023-07-13 | 2023-08-11 | 北京昕感科技有限责任公司 | Asymmetric double-groove SiC MOSFET cell structure, device and preparation method |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108615766A (en) * | 2016-12-13 | 2018-10-02 | 现代自动车株式会社 | Semiconductor devices and its manufacturing method |
| CN109166924A (en) * | 2018-08-28 | 2019-01-08 | 电子科技大学 | A kind of lateral MOS type power semiconductor and preparation method thereof |
| CN109698237A (en) * | 2017-10-23 | 2019-04-30 | 株洲中车时代电气股份有限公司 | A kind of trench gate silicon carbide MOSFET device and its manufacturing method |
| CN110518065A (en) * | 2019-09-07 | 2019-11-29 | 电子科技大学 | The groove-shaped silicon carbide MOSFET device of low power consumption and high reliability |
| CN111668312A (en) * | 2020-06-15 | 2020-09-15 | 东南大学 | Groove silicon carbide power device with low on-resistance and manufacturing process thereof |
| CN112201690A (en) * | 2020-09-24 | 2021-01-08 | 芜湖启源微电子科技合伙企业(有限合伙) | MOSFET transistor |
-
2022
- 2022-04-27 CN CN202210450145.6A patent/CN114843332B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108615766A (en) * | 2016-12-13 | 2018-10-02 | 现代自动车株式会社 | Semiconductor devices and its manufacturing method |
| CN109698237A (en) * | 2017-10-23 | 2019-04-30 | 株洲中车时代电气股份有限公司 | A kind of trench gate silicon carbide MOSFET device and its manufacturing method |
| CN109166924A (en) * | 2018-08-28 | 2019-01-08 | 电子科技大学 | A kind of lateral MOS type power semiconductor and preparation method thereof |
| CN110518065A (en) * | 2019-09-07 | 2019-11-29 | 电子科技大学 | The groove-shaped silicon carbide MOSFET device of low power consumption and high reliability |
| CN111668312A (en) * | 2020-06-15 | 2020-09-15 | 东南大学 | Groove silicon carbide power device with low on-resistance and manufacturing process thereof |
| CN112201690A (en) * | 2020-09-24 | 2021-01-08 | 芜湖启源微电子科技合伙企业(有限合伙) | MOSFET transistor |
Non-Patent Citations (1)
| Title |
|---|
| XU LI等: "A Novel SiC MOSFET With Embedded Auto-Adjust JFET With Improved Short Circuit Performance" * |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116581150A (en) * | 2023-07-13 | 2023-08-11 | 北京昕感科技有限责任公司 | Asymmetric double-groove SiC MOSFET cell structure, device and preparation method |
| CN116581150B (en) * | 2023-07-13 | 2023-09-05 | 北京昕感科技有限责任公司 | Asymmetric double-groove SiC MOSFET cell structure, device and preparation method |
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