CN110148629B - Groove type silicon carbide MOSFET device and preparation method thereof - Google Patents
Groove type silicon carbide MOSFET device and preparation method thereof Download PDFInfo
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- 229910010271 silicon carbide Inorganic materials 0.000 title claims abstract description 54
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 title claims abstract description 53
- 238000002360 preparation method Methods 0.000 title abstract description 6
- 239000002184 metal Substances 0.000 claims abstract description 34
- 239000000758 substrate Substances 0.000 claims abstract description 17
- 238000004519 manufacturing process Methods 0.000 claims abstract description 9
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 36
- 229920005591 polysilicon Polymers 0.000 claims description 24
- 238000005530 etching Methods 0.000 claims description 21
- 238000000151 deposition Methods 0.000 claims description 19
- 238000002347 injection Methods 0.000 claims description 15
- 239000007924 injection Substances 0.000 claims description 15
- 238000001259 photo etching Methods 0.000 claims description 13
- 150000002500 ions Chemical class 0.000 claims description 11
- 238000000059 patterning Methods 0.000 claims description 9
- 238000000137 annealing Methods 0.000 claims description 7
- 238000005468 ion implantation Methods 0.000 claims description 7
- 238000001465 metallisation Methods 0.000 claims description 7
- 238000000034 method Methods 0.000 claims description 7
- 230000008719 thickening Effects 0.000 claims description 6
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 5
- 239000001301 oxygen Substances 0.000 claims description 5
- 229910052760 oxygen Inorganic materials 0.000 claims description 5
- 230000008569 process Effects 0.000 claims description 5
- 238000004140 cleaning Methods 0.000 claims description 3
- 239000012299 nitrogen atmosphere Substances 0.000 claims description 3
- 238000001039 wet etching Methods 0.000 claims description 3
- 230000003647 oxidation Effects 0.000 claims 1
- 238000007254 oxidation reaction Methods 0.000 claims 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 2
- 229910052710 silicon Inorganic materials 0.000 abstract description 2
- 239000010703 silicon Substances 0.000 abstract description 2
- 238000010586 diagram Methods 0.000 description 7
- 230000015556 catabolic process Effects 0.000 description 4
- 230000000903 blocking effect Effects 0.000 description 2
- 238000006731 degradation reaction Methods 0.000 description 2
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- 239000000463 material Substances 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000001590 oxidative effect Effects 0.000 description 2
- 230000003071 parasitic effect Effects 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 229910052681 coesite Inorganic materials 0.000 description 1
- 229910052906 cristobalite Inorganic materials 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 230000007774 longterm Effects 0.000 description 1
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- 239000000377 silicon dioxide Substances 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
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- 229910052905 tridymite Inorganic materials 0.000 description 1
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66053—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide
- H01L29/66068—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
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- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
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Abstract
The invention provides a groove-type carbonThe silicon MOSFET device comprises a source electrode ohmic contact region, a drain electrode ohmic contact region, a silicon carbide N + substrate, a silicon carbide N-drift region, a P-type base region, and an N-type base region+The device is a groove type silicon carbide MOSFET device integrating a low-conduction voltage drop diode, when the device works at a third quadrant, positive voltage is applied to a source electrode, depletion layers of a P type base region and an N-drift region are reduced, a current path from the N + source region, the N-drift region and a silicon carbide N + substrate to drain electrode ohmic contact is formed, and low-voltage starting is achieved. The device has small chip area and lower third quadrant conduction voltage drop than a silicon carbide MOSFET device integrated with a Schottky diode. Meanwhile, compared with a silicon carbide MOSFET device integrated with a Schottky diode, the device provided by the invention does not need to additionally increase a Schottky metal contact preparation process, and is compatible with the existing silicon carbide MOSFET device manufacturing process.
Description
Technical Field
The invention belongs to the technical field of power semiconductors, and particularly relates to a trench type silicon carbide MOSFET device structure and a preparation method thereof.
Background
Silicon Carbide (Silicon Carbide) material is one of the representatives of the third generation wide bandgap semiconductor material, has the characteristics of large forbidden bandwidth, high critical breakdown electric field, high thermal conductivity, high electronic saturation drift velocity and the like, and has wide application prospect in the fields of high power, high temperature and high frequency power electronics.
Silicon carbide power MOSFET device structures have evolved from LDMOS (lateral planar double diffused MOSFET), VVMOS (V-groove MOSFET), to planar VDMOS (vertical double diffused MOSFET), to trench MOSFET (trench MOSFET). The LDMOS has a simple structure, but the diffusion region and the channel region are arranged on the surface of the wafer, so that the utilization rate of the area of the chip is not high. The VVMOS is formed with drain on the back of the wafer, so the diffusion region and the channel region are in the vertical direction, thus the on-current of the chip can be greatly improved, but the VVMOS has the defect that the V-shaped groove sharp pricks can cause the electric field concentration to reduce the breakdown voltage characteristic. Compared with a VDMOS device, the silicon carbide groove MOSFET has the advantages that the conducting channel is positioned in the vertical direction, parasitic JFET resistance of a plane VDMOS is eliminated, the cell size is reduced, current density is obviously improved, and meanwhile on-resistance is also reduced.
The silicon carbide has a wide forbidden band width, and the turn-on voltage of a body diode of the silicon carbide is very high (2.5-3V at room temperature) and much higher than that of a body diode of a silicon-based power device (0.7-0.8V at room temperature), so that the loss of the body diode of the silicon carbide MOSFET as a freewheeling diode is large. And more importantly, the bipolar degradation is likely to be caused by the body diode consisting of the P-type base region and the N-drift region, and the degradation problem brings a severe test to the long-term stable operation of the silicon carbide MOSFET and also brings a challenge to the safety design of the whole power electronic system. In the current advanced power electronic application field, an anti-parallel silicon carbide diode is generally adopted as a freewheeling diode, and current is ensured to flow through the silicon carbide diode when a system is in a dead zone state, so that dead zone loss is effectively reduced and the reliability of the system is improved. Although the design and optimization of the full silicon carbide module, namely the module in which a plurality of silicon carbide MOSFETs and anti-parallel silicon carbide diodes thereof realize different functions, have been greatly improved in recent years, since one power switch is always connected in parallel with one diode in an anti-parallel manner, the external diode itself introduces extra parasitic capacitance, and the bonding wire connected with the external diode introduces stray inductance, which restricts the application of the silicon carbide module in high frequency and miniaturization. In recent years, the performance of the third quadrant of the silicon carbide MOSFET is improved by using an integrated schottky diode method, and from the device structure level, integrating a schottky diode is a practical and effective method for improving the performance of the third quadrant of the silicon carbide MOSFET.
Disclosure of Invention
The device is a groove type silicon carbide MOSFET device integrated with a low-conduction voltage drop diode, when the device works in a third quadrant, positive voltage is applied to a source electrode, a depletion layer of a P-type base region and an N-drift region is reduced, a current path from an N + source region, the N-drift region and a silicon carbide N + substrate to drain electrode ohmic contact is formed, and low-voltage starting is achieved. The device has small chip area, has lower third quadrant conduction voltage drop than a silicon carbide MOSFET device integrated with a Schottky diode, can further optimize the third quadrant characteristic of the device, does not need to additionally increase a Schottky metal contact preparation process compared with the silicon carbide MOSFET device integrated with the Schottky diode, and is compatible with the existing silicon carbide MOSFET device manufacturing process.
In order to achieve the purpose, the invention adopts the following technical scheme:
a trench type silicon carbide MOSFET device comprises a drain metal 12, an N + substrate 11 above the drain metal 12, and an N-drift region 10 above the N + substrate 11 from bottom to top; a first P + shielding region 9 is arranged on the left side of the upper part inside the N-drift region 10, and a second P + shielding region 91 is arranged on the right side of the upper part inside the N-drift region 10; a first P-type base region 8 is arranged above the inside of the N-drift region 10 on the right side of the first P + shielding region 9; a second P-type base region 81 is arranged above the inside of the N-drift region 10 on the left side of the second P + shielding region 91; the first P-type base region 8 and the second P-type base region 81 are separated by an N-drift region 10, and a first N + source region 5 is arranged above the inner part of the first P-type base region 8; a second N + source region 51 is arranged above the inner part of the second P-type base region 81; a first P + ohmic contact region 6 is arranged on the right side of a first N + source region 5 above the inner part of the first P-type base region 8; a second P + ohmic contact region 61 is arranged on the left side of a second N + source region 51 above the inner part of the second P-type base region 81; a third N + source region 7 is arranged above the inside of the first P-type base region 8 and on the right side of the first P + ohmic contact region 6; a fourth N + source region 71 is arranged above the inner part of the second P-type base region 81 and on the left side of the second P + ohmic contact region 61; a source metal 1 is arranged above the first N + source region 5, the first P + ohmic contact region 6, the third N + source region 7, the N-drift region 10, the second N + source region 51, the second P + ohmic contact region 61 and the fourth N + source region 71; the source metal 1 is a source ohmic contact region;
the gate structure of the device comprises a first polysilicon 3, a second polysilicon 31, a first gate dielectric 4 surrounding the bottom and the side wall of the first polysilicon 3, a second gate dielectric 41 surrounding the bottom and the side wall of the second polysilicon 31, a first metal gate electrode 2 arranged on the upper surface of part of the first polysilicon 3, and a second metal gate electrode 21 arranged on the upper surface of part of the second polysilicon 31, wherein the thickness of a first P-type base region 8 is respectively greater than the thickness of a first N + source region 5, a second N + source region 51, a third N + source region 7, a fourth N + source region 71, a first P + ohmic contact region 6 and a second P + ohmic contact region 61, the thickness of a second P-type base region 81 is respectively greater than the thickness of the first N + source region 5, the second N + source region 51, the third N + source region 7, the fourth N + source region 71, the first P + ohmic contact region 6 and the second P + ohmic contact region 61, the first P + shielding region 9 and the second P + shielding region 91 are connected to a source electrode.
A region below the first N + source region 5 and between the left end of the first P-type base region 8 and the first gate dielectric 4 is a first vertical channel of the device; a region below the second N + source region 51 and between the right end of the second P-type base region 81 and the second gate dielectric 41 is a second vertical channel of the device;
preferably, the first P-type base region 8 and the second P-type base region 81 are implanted with ions; the first P-type base region 8 located below the first N + source region 5 is doped with low concentration, and the second P-type base region 81 located below the second N + source region 51 is doped with low concentration; the first P-type base region 8 below the third N + source region 7 is doped with high concentration, and the second P-type base region 81 below the fourth N + source region 71 is doped with high concentration.
The invention also provides a manufacturing method of the groove type silicon carbide MOSFET device, which comprises the following steps:
a. the first step is as follows: manufacturing an N-drift region on a silicon carbide substrate by adopting an epitaxial process, cleaning an epitaxial wafer, and making a photoetching mark by etching;
b. injecting a P-type base region, depositing an injection mask layer, obtaining a P-type base region injection pattern through photoetching, and performing ion injection;
c. injecting an N + source region, depositing a mask layer, obtaining an N + source region graph through photoetching, and injecting ions;
d. etching the groove, wherein the etching depth of the groove is greater than that of the P-type base region;
e. injecting the P + ohmic contact region and the P + shielding region, depositing a mask layer, obtaining an injection pattern of the P + ohmic contact region and the P + shielding region through photoetching, and performing ion injection;
f. growing gate oxide, namely, oxidizing the gate oxide by dry oxygen at 1300 ℃, and then respectively annealing the gate oxide in a nitrogen atmosphere to obtain a first gate dielectric 4 and a second gate dielectric 41;
g. depositing and etching polycrystalline silicon, depositing the polycrystalline silicon, performing ion implantation and annealing; patterning the polysilicon to obtain a first polysilicon 3 and a second polysilicon 31;
h. depositing a medium and etching an opening to obtain a gate-source contact region; thickening and patterning metal on the front surface, carrying out Al metal deposition, and obtaining a gate electrode and a source electrode in a wet etching mode;
i. and thickening and patterning the metal on the front surface, performing metal deposition, and obtaining a gate electrode and a source electrode in an etching mode.
The invention has the beneficial effects that: the invention is a groove type silicon carbide MOSFET device, the doping concentration near a first vertical channel and a second vertical channel is lower, so that the threshold voltage is reduced; the doping concentration of the P-type base regions under the third N + source region and the fourth N + source region is higher, when the device works at a first quadrant, the depletion layer of the PN junction is utilized to realize the turn-off of the device, and the effective blocking of the device is ensured; when the device works in a third quadrant, positive voltage is applied to the source electrode, the depletion layer of the P-type base region and the depletion layer of the N-drift region are reduced, a current path from the N + source region, the N-drift region and the silicon carbide N + substrate to the drain electrode ohmic contact is formed, and low-voltage starting is achieved. The device has small chip area, has lower third quadrant conduction voltage drop than a silicon carbide MOSFET device integrated with a Schottky diode, can further optimize the third quadrant characteristic of the device, does not need to additionally increase a Schottky metal contact preparation process compared with the silicon carbide MOSFET device integrated with the Schottky diode, and is compatible with the existing silicon carbide MOSFET device manufacturing process.
Drawings
FIG. 1 is a schematic diagram of a conventional trench-type silicon carbide MOSFET device structure;
FIG. 2 is a schematic view of a trench type silicon carbide MOSFET device provided in accordance with the present invention;
FIG. 3 is a schematic representation of a device of the present invention after forming an N-SiC epitaxial layer on a SiC N + substrate;
FIG. 4 is a schematic diagram of a P-type base region formed by photoetching and ion implantation in the P-type base region of the device of the present invention;
FIG. 5 is a schematic diagram of the device of the present invention in which an N + source region is formed by photolithography and ion implantation;
FIG. 6 is a schematic diagram of the structure of the device of the present invention for forming a silicon carbide MOSFET trench;
FIG. 7 is a schematic diagram of a P + ohmic contact region and a P + shielding region formed by photolithography and ion implantation in the device of the present invention;
FIG. 8 is a schematic structural view of the device of the present invention grown by thermal oxygen;
FIG. 9 is a schematic diagram of the structure of the device of the present invention after deposition and etching of polysilicon;
FIG. 10 is a schematic illustration of a device of the present invention with dielectric deposited and etched openings;
FIG. 11 is a schematic diagram of a device of the present invention with metal deposition and gate and source electrodes obtained by etching;
the structure of the transistor comprises a substrate, a source metal 1, a first metal gate electrode 2, a second metal gate electrode 21, a first polysilicon 3, a second polysilicon 31, a first gate dielectric 4, a second gate dielectric 41, a first N + source region 5, a second N + source region 51, a first P + ohmic contact region 6, a second P + ohmic contact region 61, a third N + source region 7, a fourth N + source region 71, a first P-type base region 8, a second P-type base region 81, a first P + shielding region 9, a second P + shielding region 91, an N-drift region 10, an N + substrate 11 and a drain metal 12.
Detailed Description
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.
The technical scheme of the invention is described in detail in the following with the accompanying drawings:
a trench-type silicon carbide MOSFET device of the present invention, as shown in fig. 2: the transistor comprises a drain metal 12, an N + substrate 11 above the drain metal 12 and an N-drift region 10 above the N + substrate 11 from bottom to top; a first P + shielding region 9 is arranged on the left side of the upper part inside the N-drift region 10, and a second P + shielding region 91 is arranged on the right side of the upper part inside the N-drift region 10; a first P-type base region 8 is arranged above the inside of the N-drift region 10 on the right side of the first P + shielding region 9; a second P-type base region 81 is arranged above the inside of the N-drift region 10 on the left side of the second P + shielding region 91; the first P-type base region 8 and the second P-type base region 81 are separated by an N-drift region 10, and a first N + source region 5 is arranged above the inner part of the first P-type base region 8; a second N + source region 51 is arranged above the inner part of the second P-type base region 81; a first P + ohmic contact region 6 is arranged on the right side of a first N + source region 5 above the inner part of the first P-type base region 8; a second P + ohmic contact region 61 is arranged on the left side of a second N + source region 51 above the inner part of the second P-type base region 81; a third N + source region 7 is arranged above the inside of the first P-type base region 8 and on the right side of the first P + ohmic contact region 6; a fourth N + source region 71 is arranged above the inner part of the second P-type base region 81 and on the left side of the second P + ohmic contact region 61; a source metal 1 is arranged above the first N + source region 5, the first P + ohmic contact region 6, the third N + source region 7, the N-drift region 10, the second N + source region 51, the second P + ohmic contact region 61 and the fourth N + source region 71, and the source metal 1 is a source ohmic contact region; the gate structure of the device comprises a first polysilicon 3, a second polysilicon 31, a first gate dielectric 4 surrounding the bottom and the side wall of the first polysilicon 3, a second gate dielectric 41 surrounding the bottom and the side wall of the second polysilicon 31, a first metal gate electrode 2 arranged on the upper surface of part of the first polysilicon 3, and a second metal gate electrode 21 arranged on the upper surface of part of the second polysilicon 31, wherein the thickness of a first P-type base region 8 is respectively greater than the thickness of a first N + source region 5, a second N + source region 51, a third N + source region 7, a fourth N + source region 71, a first P + ohmic contact region 6 and a second P + ohmic contact region 61, the thickness of a second P-type base region 81 is respectively greater than the thickness of the first N + source region 5, the second N + source region 51, the third N + source region 7, the fourth N + source region 71, the first P + ohmic contact region 6 and the second P + ohmic contact region 61, the first P + shielding region 9 and the second P + shielding region 91 are connected to a source electrode.
A region below the first N + source region 5 and between the left end of the first P-type base region 8 and the first gate dielectric 4 is a first vertical channel of the device; a region below the second N + source region 51 and between the right end of the second P-type base region 81 and the second gate dielectric 41 is a second vertical channel of the device;
the first P-type base region 8 and the second P-type base region 81 adopt ion implantation; the first P-type base region 8 located below the first N + source region 5 is doped with low concentration, and the second P-type base region 81 located below the second N + source region 51 is doped with low concentration; the first P-type base region 8 below the third N + source region 7 is doped with high concentration, and the second P-type base region 81 below the fourth N + source region 71 is doped with high concentration.
The manufacturing method of the groove type silicon carbide MOSFET device comprises the following steps:
a. the first step is as follows: manufacturing an N-drift region on a silicon carbide substrate by adopting an epitaxial process, cleaning an epitaxial wafer, and making a photoetching mark by etching; as shown in fig. 3;
b. injecting a P-type base region, depositing an injection mask layer, obtaining a P-type base region injection pattern through photoetching, and performing ion injection; as shown in fig. 4;
c. injecting an N + source region, depositing a mask layer, obtaining an N + source region graph through photoetching, and injecting ions; as shown in fig. 5;
d. etching the groove, wherein the etching depth of the groove is greater than that of the P-type base region; as shown in fig. 6; micro grooves are easy to form in the groove etching process, so that the grooves can have better appearance by increasing the content of oxygen;
e. injecting the P + ohmic contact region and the P + shielding region, depositing a mask layer, obtaining an injection pattern of the P + ohmic contact region and the P + shielding region through photoetching, and performing ion injection; as shown in fig. 7;
f. growing gate oxide, namely, oxidizing the gate oxide by dry oxygen at 1300 ℃, and then respectively annealing the gate oxide in a nitrogen atmosphere to obtain a first gate dielectric 4 and a second gate dielectric 41; as shown in FIG. 8, gate oxide growth will occur on SiC/SiO2The interface has higher interface state density, so that an NO annealing process can be adopted;
g. depositing and etching polycrystalline silicon, depositing the polycrystalline silicon, performing ion implantation and annealing; patterning the polysilicon to obtain a first polysilicon 3 and a second polysilicon 31; as shown in figure 9 of the drawings,
h. depositing a medium and etching an opening to obtain a gate-source contact region; thickening and patterning metal on the front surface, carrying out Al metal deposition, and obtaining a gate electrode and a source electrode in a wet etching mode; carrying out gate-source isolation on the device; as shown in figure 10 of the drawings,
i. and thickening and patterning the metal on the front surface, performing metal deposition, and obtaining a gate electrode and a source electrode in an etching mode. As shown in fig. 11.
The first P-type base region 8 positioned below the first N + source region 5 is doped with low concentration, and the second P-type base region 81 positioned below the second N + source region 51 is doped with low concentration, so that the threshold voltage of the MOSFET device during forward conduction can be effectively reduced; the first P-type base region 8 below the third N + source region 7 is doped with high concentration, and the second P-type base region 81 below the fourth N + source region 71 is doped with high concentration, so that under the condition that the device is not applied with working voltage, the pinch-off is realized by utilizing a depletion layer of a PN junction, no leakage current exists, and the device is ensured to have good blocking characteristics; a source metal 1 is arranged above the first N + source region 5, the first P + ohmic contact region 6, the third N + source region 7, the N-drift region 10, the second N + source region 51, the second P + ohmic contact region 61 and the fourth N + source region 71, and the source metal 1 is a source ohmic contact region; the addition of the third N + source region 7 and the fourth N + source region 71 is designed to enable good ohmic contact. When the device works in the third quadrant, positive voltage is applied to the source electrode, depletion layers of the P-type base region and the N-drift region are reduced, a current path from the third N + source region 7, the fourth N + source region 71, the N-drift region 10, the silicon carbide N + substrate 11 to the drain metal 12 is formed, low-voltage starting is achieved, and therefore the characteristics of the third quadrant are optimized.
The device is a groove type silicon carbide MOSFET device integrating a low-conduction-voltage-drop diode, has a smaller chip area than an anti-parallel silicon carbide diode device, also has a lower third-quadrant conduction voltage drop than an integrated Schottky diode device, and can further optimize the third-quadrant characteristic of the device.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.
Claims (2)
1. A trench type silicon carbide MOSFET device is characterized in that: the transistor comprises a drain metal (12), an N + substrate (11) above the drain metal (12) and an N-drift region (10) above the N + substrate (11) from bottom to top; a first P + shielding region (9) is arranged on the left side above the inside of the N-drift region (10), and a second P + shielding region (91) is arranged on the right side above the inside of the N-drift region (10); a first P-type base region (8) is arranged above the inner part of the N-drift region (10) on the right side of the first P + shielding region (9); a second P-type base region (81) is arranged above the inside of the N-drift region (10) on the left side of the second P + shielding region (91); the first P-type base region (8) and the second P-type base region (81) are separated by an N-drift region (10), and a first N + source region (5) is arranged above the inner part of the first P-type base region (8); a second N + source region (51) is arranged above the inner part of the second P-type base region (81); a first P + ohmic contact area (6) is arranged on the right side of a first N + source area (5) above the inner part of the first P-type base area (8); a second P + ohmic contact area (61) is arranged on the left side of a second N + source area (51) above the inner part of the second P-type base area (81); a third N + source region (7) is arranged above the inner part of the first P-type base region (8) and on the right side of the first P + ohmic contact region (6); a fourth N + source region (71) is arranged above the inner part of the second P-type base region (81) and on the left side of the second P + ohmic contact region (61); a source metal (1) is arranged above the first N + source region (5), the first P + ohmic contact region (6), the third N + source region (7), the N-drift region (10), the second N + source region (51), the second P + ohmic contact region (61) and the fourth N + source region (71), and the source metal (1) is a source ohmic contact region; the gate structure of the device comprises first polycrystalline silicon (3), second polycrystalline silicon (31), a first gate dielectric (4) surrounding the bottom and the side wall of the first polycrystalline silicon (3), a second gate dielectric (41) surrounding the bottom and the side wall of the second polycrystalline silicon (31), a first metal gate electrode (2) arranged on the upper surface of the part of the first polycrystalline silicon (3), and a second metal gate electrode (21) arranged on the upper surface of the part of the second polycrystalline silicon (31), wherein the thicknesses of a first P-type base region (8) are respectively greater than the thicknesses of a first N + source region (5), a second N + source region (51), a third N + source region (7), a fourth N + source region (71), a first P + ohmic contact region (6) and a second P + ohmic contact region (61), and the thickness of a second P-type base region (81) is respectively greater than the thicknesses of the first N + source region (5), the second N + source region (51), The thicknesses of a third N + source region (7), a fourth N + source region (71), a first P + ohmic contact region (6) and a second P + ohmic contact region (61), wherein the first P + shielding region (9) and the second P + shielding region (91) are connected with a source electrode; the first P-type base region (8) and the second P-type base region (81) are implanted by adopting ions; the first P-type base region (8) located below the first N + source region (5) is doped in low concentration, and the second P-type base region (81) located below the second N + source region (51) is doped in low concentration; and a first P-type base region (8) below the third N + source region (7) is doped with high concentration, and a second P-type base region (81) below the fourth N + source region (71) is doped with high concentration.
2. The method of making a trench silicon carbide MOSFET device of claim 1, comprising the steps of:
a. the first step is as follows: manufacturing an N-drift region on a silicon carbide substrate by adopting an epitaxial process, cleaning an epitaxial wafer, and making a photoetching mark by etching;
b. injecting a P-type base region, depositing an injection mask layer, obtaining a P-type base region injection pattern through photoetching, and performing ion injection;
c. injecting an N + source region, depositing a mask layer, obtaining an N + source region graph through photoetching, and injecting ions;
d. etching the groove, wherein the etching depth of the groove is greater than that of the P-type base region;
e. injecting a P + ohmic contact region and a P + shielding region: depositing a mask layer, obtaining a P + ohmic contact region and a P + shielding region injection pattern through photoetching, and performing ion injection;
f. growing gate oxide, generating a gate oxide layer by dry oxygen oxidation at 1300 ℃, and then respectively annealing in a nitrogen atmosphere to obtain a first gate dielectric (4) and a second gate dielectric (41);
g. depositing and etching polycrystalline silicon, depositing the polycrystalline silicon, performing ion implantation and annealing; patterning the polysilicon to obtain a first polysilicon (3) and a second polysilicon (31);
h. depositing a medium and etching an opening to obtain a gate-source contact region; thickening and patterning metal on the front surface, carrying out Al metal deposition, and obtaining a gate electrode and a source electrode in a wet etching mode;
i. and thickening and patterning the metal on the front surface, performing metal deposition, and obtaining a gate electrode and a source electrode in an etching mode.
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| CN111446293A (en) * | 2020-03-25 | 2020-07-24 | 浙江大学 | Silicon carbide power MOSFET device of enhanced body diode |
| CN112614892A (en) * | 2020-12-22 | 2021-04-06 | 成都杰启科电科技有限公司 | Silicon carbide MOSFET of PIN schottky diode |
| CN112736126B (en) * | 2020-12-31 | 2022-05-10 | 厦门市三安集成电路有限公司 | SiC MOSFET structure and manufacturing method thereof |
| CN113471290B (en) * | 2021-06-18 | 2023-08-04 | 电子科技大学 | Tunneling-assisted conduction silicon/silicon carbide heterojunction MOSFET power device |
| CN114023810B (en) * | 2022-01-05 | 2022-04-08 | 北京昕感科技有限责任公司 | SiC MOSFET cell structure with L-shaped base region, device and manufacturing method |
| CN114784107B (en) * | 2022-04-21 | 2023-04-28 | 电子科技大学 | SiC MOSFET integrated with junction barrier Schottky diode and manufacturing method thereof |
| CN114784108B (en) * | 2022-04-21 | 2023-05-05 | 电子科技大学 | Planar gate SiC MOSFET integrated with junction barrier Schottky diode and manufacturing method thereof |
| CN116995099B (en) * | 2023-09-08 | 2024-02-06 | 南京第三代半导体技术创新中心有限公司 | Voltage clamping type silicon carbide trench gate MOSFET device and manufacturing method thereof |
| CN116913973B (en) * | 2023-09-12 | 2024-06-21 | 成都蓉矽半导体有限公司 | Trench silicon carbide MOSFET with optimized current capability |
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