CN116525683B - Deep-well type SiC Mosfet device and preparation method thereof - Google Patents
Deep-well type SiC Mosfet device and preparation method thereof Download PDFInfo
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
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Abstract
The application discloses a deep well type SiC Mosfet device and a preparation method thereof, wherein the device comprises: the semiconductor device comprises a SiC substrate, a SiC epitaxial layer, a P+ deep well, a groove, a P-body region, an N+ source electrode, an isolation passivation layer, a front source electrode metal layer, a back drain electrode metal layer and a front grid electrode metal layer, wherein the P+ deep well, the groove, the P-body region, the N+ source electrode and the isolation passivation layer are arranged on the SiC epitaxial layer, the N+ source electrode and the P+ deep well are arranged in parallel and are isolated from each other, and the groove is arranged orthogonal to the P+ deep well. The deep-well type SiC Mosfet device adopts an orthogonal mode of a groove and deep-energy ion implantation P+ to reduce the on-resistance, the device withstand voltage and the device grid reliability of the power SiC MOSFET. According to the preparation method, a groove type Mosfet structure is adopted, a channel is formed on the side wall of the groove, a P+ deep well is formed at the bottom of the groove of the source region part of the device in an orthogonal mode of the groove and deep energy ion implantation P+, and a gate oxide layer at the bottom of the groove is better protected through deep implantation of the P+ region, so that the groove type Mosfet is not influenced by a high electric field, the on-resistance of the device is further reduced, and meanwhile, the withstand voltage of the device and the reliability of a grid electrode of the device are improved.
Description
Technical Field
The application relates to the technical field of semiconductor devices, in particular to a deep-well SiC Mosfet device and a preparation method thereof.
Background
Power devices are the core of power electronics, playing a vital role in the direction of power electronics development towards high frequency, high power density. Currently, the development of silicon (Si) devices has been very mature, and the application of 600V or less, si-based oxide-semiconductor field effect transistor (MOSFET) is the dominant one, while Si-based superjunction devices and insulated gate bipolar transistors (insulator gate bipolar transistor, IGBT) are the dominant markets for high voltage applications of 0.6-6.5 kV. Nevertheless, the development space of silicon devices has been limited by the limitations of the properties of silicon materials. For example, the withstand voltage limit of the current Si-based IGBT is 6.5kV, the working temperature is lower than 175 ℃, and the device switching speed is low due to the bipolar conduction mode, so that the popularization of the Si-based IGBT in high-frequency application is limited. The SiC material has a forbidden bandwidth which is 3 times that of the silicon material, a critical breakdown electric field strength which is 10 times that of the silicon material and a thermal conductivity which is 3 times that of the silicon material, so that the SiC power device is suitable for application occasions such as high frequency, high voltage, high temperature and the like, and is beneficial to improving the efficiency and the power density of a power electronic system.
The advantages of SiC devices over Si devices come mainly from three aspects: the energy loss in the electric energy conversion process is reduced, the miniaturization is easier to realize, and the high-temperature and high-pressure resistance is better.
1. The energy loss is reduced: the switching loss of the SiC material is extremely low, the switching loss of the all-SiC power module is greatly lower than that of the same IGBT module, and the higher the switching frequency is, the larger the loss difference between the all-SiC power module and the IGBT module is, which means that the all-SiC power module can not only greatly reduce the loss but also realize high-speed switching when the all-SiC power module is not good for high-speed switching operation of the IGBT module.
2. The low resistance makes it easier to achieve miniaturization: the SiC material has lower on-state resistance, the area of a chip can be reduced under the condition of the same resistance value, and the size of the SiC power module can be about 1/10 of that of Si.
3. More resistant to high temperatures: the forbidden bandwidth of SiC is 3.23ev, the corresponding intrinsic temperature can reach 800 ℃, and the born temperature is higher than Si; the SiC material has a thermal conductivity of 3.7W/cm/K, while the silicon material has a thermal conductivity of only 1.5W/cm/K, and the higher thermal conductivity can bring about remarkable improvement of power density, and meanwhile, the design of a heat dissipation system is simpler, or natural cooling is directly adopted.
SiC was developed from the 70 s of the last century, siC SBD was commercially available in 2001, siC MOSFET was commercially available in 2010, and SiC IGBT was under development. With the defect reduction and quality improvement of 6 inch SiC single crystal substrates and epitaxial wafers, siC device preparation can be performed on the existing 6 inch Si-based power device growth line, which further reduces SiC material and device cost and promotes popularization of SiC devices and modules. Currently, the main SiC MOSFET device structure comprises a Gree CIMOSFET structure, a Rohm double-groove MOSFET structure and an Infineon TMOSFET structure, wherein the Gree CIMOSFET structure is a planar structure and has larger on-resistance due to the influence of JFET resistance; the Rohm double-groove MOSFET structure can lead the duty ratio of a device conducting channel in the whole active area to be smaller due to the existence of the double-groove P+ well area, thereby being not beneficial to further reduction of on-resistance; the grooves and the P+ deep wells in the Infinion TMOSFET structure are parallel, so that the overall channel density of the device is not easy to shrink. It is therefore necessary for those skilled in the art to provide a SiC Mosfet device structure that is different from the one described above.
Disclosure of Invention
The first object of the application is to provide a deep-well type SiC Mosfet device which adopts a trench and deep-energy ion implantation P+ orthogonal mode to reduce the on-resistance, device withstand voltage and device gate reliability of a power SiC MOSFET; meanwhile, the device can further reduce on-resistance by increasing channel density in the direction of the conductive channel Ax.
The second object of the present application is to provide a method for manufacturing the deep-well SiC Mosfet device, in which a trench type Mosfet structure is first used to eliminate a JFET region caused by a conventional planar Mosfet structure by forming a trench in a trench sidewall, so as to achieve the purpose of reducing the on-resistance of the device, and in which mobility in the trench sidewall direction is higher than mobility in the horizontal direction of the planar Mosfet structure due to the characteristics of the SiC material, and the trench resistance of the trench type Mosfet structure is also lower than that of the conventional planar type. And secondly, forming a P+ deep well at the bottom of a part of the groove of the source region of the device in an orthogonal mode of injecting P+ into the groove and deep energy ions, and better protecting a grid oxide layer at the bottom of the groove by deep injection of the P+ region to prevent the grid oxide layer from being influenced by a high electric field, thereby improving the withstand voltage of the device and the reliability of a grid electrode of the device.
The technical scheme provided by the application is as follows:
the deep-well SiC Mosfet device is characterized by comprising:
a SiC substrate;
a SiC epitaxial layer grows on the SiC substrate, a P+ deep well, a groove, a P-body region, an N+ source electrode and an isolation passivation layer are arranged on the SiC epitaxial layer, a gate oxide layer grows on the inner surface of the groove and the surface of the SiC epitaxial layer, a gate polysilicon layer is etched on the surface of the gate oxide layer, a contact hole is formed in the isolation passivation layer region, a metal forming contact hole metal layer is deposited in the contact hole, and ohmic contact is formed between the contact hole metal layer and the N+ source electrode;
the front source electrode metal layer is arranged on the front of the deep-well type SiC Mosfet device;
the back drain electrode metal layer is arranged on the back of the SiC substrate;
the front grid electrode metal layer is arranged on the periphery of the deep well type SiC Mosfet device and is led out from the grid electrode polycrystalline silicon layer;
the N+ source electrode is arranged in parallel with the P+ deep well, and the groove is arranged orthogonally to the P+ deep well.
Further, the P+ deep well extends from one side to the other side of the P-body region along the X direction of the SiC epitaxial layer, the P+ deep well is arranged into a strip shape which is isolated from each other, and the N+ source electrode is arranged in the P-body region close to the P+ deep well;
the trenches are arranged in stripes spaced apart from each other in the Y-direction on the SiC epitaxial layer, and the trenches extend from one side of the SiC epitaxial layer to the other side.
Further, the contact hole metal layer is located on the surfaces of the N+ source electrode and the P+ deep well, and the isolation passivation layer is located on the surface of the grid polycrystalline silicon layer.
Further, the thickness of the SiC substrate is 200-500 um;
the thickness of the SiC epitaxial layer is 10-20 um;
the implantation depth of the P-body region is 0.5 um-1 um;
the width of the P+ deep well is 2-3 um, the interval is 0.5-1.5 um, and the implantation depth is 1.8-3.0 um;
the width of the groove is 0.5-2.0 um, and the depth is 0.5-2.0 um;
the implantation depth of the N+ source electrode is 0.1-0.5 um, and the width is 0.5-1.5 um.
Further, the SiC substrate and the SiC epitaxial layer are both doped with N type, the doping of the N+ source is heavily doped with N type, the P-body region is heavily doped with P type, and the grid polycrystalline silicon layer is heavily doped with N type.
The method for preparing the deep-well type SiC Mosfet device is used for preparing the deep-well type SiC Mosfet device and comprises the following steps of:
growing a lightly doped SiC epitaxial layer on the surface of the SiC substrate;
injecting a layer of P-body region on the SiC epitaxial layer, and performing high-temperature annealing for 10-30 min at 1500-1800 ℃ to activate the injected ions;
injecting a layer of P+ deep well on the SiC epitaxial layer along the X direction, and performing high-temperature annealing for 10-30 min at 1500-1800 ℃ to activate the injected ions;
etching a groove orthogonal to the P+ deep well on the SiC epitaxial layer along the Y direction, modifying the shape of the groove, and growing a layer of gate oxide layer on the inner surface of the groove and the surface of the SiC epitaxial layer;
depositing an N-type heavily doped gate polysilicon layer as a gate region of the device, and etching to the surface of the gate oxide layer;
injecting N-type heavily doped nitrogen ions into the surface of the SiC epitaxial layer along the X direction to form an N+ source electrode, and then carrying out high-temperature annealing for 10-30 min at 1500-1800 ℃ to activate the injected ions;
depositing an oxide layer or Si on the surface of the SiC epitaxial layer 3 N 4 Forming an isolation passivation layer;
forming a contact hole in the isolation passivation layer region, sputtering to form a Ti film, forming ohmic contact on the N+ source electrode through a sintering process at 800-1000 ℃, and depositing a metal layer to form a contact hole metal layer;
depositing a metal layer in a sputtering mode, forming a front source electrode metal layer on the front surface of the deep well type SiC Mosfet device, and then leading out a front grid electrode metal layer on the periphery of the deep well type SiC Mosfet device in a polysilicon leading-out mode;
and thinning the back of the SiC substrate, and then forming a back drain metal layer on the back of the SiC substrate.
Further, the modification of the morphology of the groove is specifically:
high-temperature passivation treatment is carried out for 10-30 min under the conditions that the temperature is 1400-1700 ℃ and the gas atmosphere is one or more of hydrogen, argon and silane.
Further, the thickness of the SiC substrate is 200-500 um, the doped ions of the SiC epitaxial layer are nitrogen ions, and the doping concentration of the nitrogen ions is 10 15 ～5×10 15 cm -3 The doping thickness is 10 um-20 um;
the P-body region is implanted by photoetching and ion implantation, the ion implanted in the P-body region is aluminum ion, the implantation depth of the aluminum ion is 0.5 um-1 um, and the implantation concentration of the aluminum ion is 10 17 ～5×10 18 cm -3 ；
The P+ deep well is implanted by photoetching, hard mask process and deep ion implantation, the width of the P+ deep well is 2-3 um, the interval is 0.5-1.5 um, the implantation depth is 1.8-3.0 um, the ion implanted by the P+ deep well is aluminum ion, and the implantation concentration of the aluminum ion is 10 17 ～10 19 cm -3 。
Further, the groove is formed through photoetching, a hard mask process and an ICP (inductively coupled plasma) etching process, and the width of the groove is 0.5-2.0 um, and the depth of the groove is 0.5-2.0 um;
the implantation mode of the N+ source electrode is a photoetching and ion implantation mode, the ion implanted into the N+ source electrode is N-type heavily doped nitrogen ion, and the doping concentration of the nitrogen ion is 10 19 ～5×10 20 cm -3 The implantation depth of the N+ source electrode is 0.1-0.5 um, and the width is 0.5-1.5 um;
the isolation passivation layer is formed by Chemical Vapor Deposition (CVD);
the contact hole and the front source electrode metal layer are formed by photoetching and dry etching processes;
the formation mode of the back drain electrode metal layer is an evaporation mode.
Compared with the prior art, the application has the beneficial effects that:
1. the application provides a deep-well type SiC Mosfet device, which adopts a trench and deep-energy ion implantation P+ orthogonal mode to reduce the on-resistance, the device withstand voltage and the device grid reliability of a power SiC MOSFET;
2. the application provides a preparation method of a deep-well type SiC Mosfet device, which comprises the steps of firstly adopting a groove type Mosfet structure to form a channel on the side wall of the groove, eliminating a JFET region caused by a traditional planar type Mosfet structure, thereby realizing the purpose of reducing the on-resistance of the device, and further, because of the characteristics of SiC materials, the mobility of the groove side wall is higher than the mobility of the planar type Mosfet structure in the horizontal direction, and the channel resistance of the groove type Mosfet structure is lower than that of the traditional planar type Mosfet structure. Secondly, forming a P+ deep well at the bottom of a part of the groove of the source region of the device in an orthogonal mode of injecting P+ into the groove and deep energy ions, and better protecting a grid oxide layer at the bottom of the groove by deep injecting the P+ region to prevent the grid oxide layer from being influenced by a high electric field, thereby improving the withstand voltage of the device and the reliability of a grid electrode of the device;
3. the grid electrode in the active region of the deep-well SiC Mosfet device is a polysilicon trench grid electrode, so that the resistance of the JFET region and the density of the device can be effectively reduced, the mobility of carriers can be increased, and the purposes of reducing the on-resistance of the device and increasing the power density of the device can be achieved;
4. the active region of the device adopts a groove type structure as a grid electrode of the device, and compared with a planar SiC MOSFET, the active region of the device can increase carrier mobility;
5. the active region of the device adopts a groove type structure as a grid electrode of the device, and compared with a planar SiC MOSFET, the active region of the device can reduce the resistance of a JEFT region;
6. the active region of the device adopts deep ion implantation P+ to form a P well and is orthogonal to the groove, so that the device can further reduce the on-resistance by increasing the channel density in the direction of the conducting channel Ax;
7. the active regions of the device are arranged in parallel and are isolated from each other to realize charge balance among the P+ deep wells, so that the withstand voltage of the device is improved by reducing the electric field at the bottom of the device groove, and meanwhile, the reliability of the grid electrode of the device is improved by protecting the grid oxygen at the bottom of the device groove from being influenced by a high electric field.
Drawings
Fig. 1 is a schematic diagram of a front layout structure of a deep well SiC Mosfet device in an embodiment of the present application;
FIG. 2 is a cross-sectional view taken along Ax in FIG. 1;
FIG. 3 is a cross-sectional view taken along Ay1 in FIG. 1;
FIG. 4 is a cross-sectional view taken along Ay2 in FIG. 1;
fig. 5 is a schematic diagram of a cross section along the X direction of a device in one of the preparation steps for preparing a deep-well SiC Mosfet device according to an embodiment of the present application;
fig. 6 is a schematic diagram of a cross section along the X direction of the device in one of the preparation steps for preparing a deep-well SiC Mosfet device according to an embodiment of the present application;
fig. 7 is a schematic diagram III of a cross section along the X direction of the device in one of the preparation steps for preparing a deep-well SiC Mosfet device according to an embodiment of the present application;
fig. 8 is a schematic diagram showing a cross section along the X direction of the device in one of the preparation steps for preparing a deep-well SiC Mosfet device according to an embodiment of the present application;
fig. 9 is a schematic diagram showing a cross section along the X direction of a device in one of the preparation steps for preparing a deep-well SiC Mosfet device according to an embodiment of the present application;
fig. 10 is a schematic diagram showing a cross section along the X direction of the device in one of the preparation steps for preparing a deep-well SiC Mosfet device according to an embodiment of the present application;
fig. 11 is a schematic diagram of a cross section along the X direction of a device in one of the preparation steps for preparing a deep-well SiC Mosfet device according to an embodiment of the present application;
fig. 12 is a schematic diagram eighth cross-section along the X direction of the device in one of the preparation steps for preparing a deep-well SiC Mosfet device according to an embodiment of the present application;
fig. 13 is a schematic diagram showing a cross section along the X direction of a device in one of the preparation steps for preparing a deep-well SiC Mosfet device according to an embodiment of the present application;
fig. 14 is a schematic cross-sectional view taken along the X direction of the device in one of the steps for fabricating a deep-well SiC Mosfet device according to an embodiment of the present application.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present application more clear, the technical solutions of the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application. It will be apparent that the embodiments described below are some, but not all, embodiments of the application. The components of the embodiments of the present application generally described and illustrated in the figures herein may be arranged and designed in a wide variety of different configurations.
Accordingly, the following detailed description of the embodiments of the application, taken in conjunction with the accompanying drawings, is intended to represent only selected embodiments of the application, and not to limit the scope of the application as claimed. All other embodiments, which can be made by one of ordinary skill in the art without undue burden on the person of ordinary skill in the art based on the embodiments of the present application, are within the scope of the present application.
Fig. 1 is a schematic diagram of a front structure of a deep well SiC Mosfet device according to a first embodiment of the present application; FIG. 2 is a cross-sectional view taken along Ax in FIG. 1; FIG. 3 is a cross-sectional view taken along Ay1 in FIG. 1; fig. 4 is a cross-sectional view taken along the direction Ay2 in fig. 1.
Referring to fig. 1-3, the present application provides a deep well SiC Mosfet device, comprising:
the SiC epitaxial layer is grown on the SiC substrate, a P+ deep well, a groove, a P-body region, an N+ source electrode and an isolation passivation layer are arranged on the SiC epitaxial layer, a layer of gate oxide layer (GOX) is grown on the inner surface of the groove and the surface of the SiC epitaxial layer, a gate polysilicon layer is etched on the surface of the gate oxide layer, a contact hole is formed in the isolation passivation layer region, a layer of metal is deposited in the contact hole to form a contact hole metal layer, and ohmic contact is formed between the contact hole metal layer and the N+ source electrode.
The front source electrode metal layer is arranged on the front of the deep-well type SiC Mosfet device;
the back drain electrode metal layer is arranged on the back of the SiC substrate;
the front grid electrode metal layer is arranged on the periphery of the deep well type SiC Mosfet device and is led out from the grid electrode polycrystalline silicon layer;
the N+ source electrode is arranged in parallel with the P+ deep well, and the groove is arranged orthogonally to the P+ deep well. In the embodiment of the application, the active region of the deep-well SiC Mosfet device is internally provided with the strip-type P+ deep well region which is perpendicular to the polysilicon trench-type gate, when the positive pressure is applied to the drain electrode, the P+ deep well/N junction formed at the bottom of the trench in parallel to the trench direction is reversely biased, and a fully depleted space charge region is formed in the N-region of the SiC epitaxial layer between the two P+ deep wells, so that the electric field of the gate oxide layer at the bottom of the trench is reduced, and the high reliability of the gate of the device is ensured while the breakdown voltage of the device is improved. In the embodiment of the application, the deep well type SiC Mosfet device adopts deep energy ion injection P+ to form a P+ deep well in the active region and is orthogonal to the groove, so that the device can further reduce the on-resistance by increasing the channel density in the direction of the conducting channel Ax.
Referring to fig. 1, p+ deep wells extend to the right along the X direction (Ax direction in the figure) of the SiC epitaxial layer from the left side of the P-body region, the p+ deep wells are arranged as strips isolated from each other, and n+ sources are arranged next to the p+ deep wells in the remaining P-body regions where the p+ deep wells are not arranged. It is also understood that p+ deep wells and n+ sources are alternately arranged with each other along the X direction of the SiC epitaxial layer.
The trenches are arranged in a stripe pattern isolated from each other in the Y direction (Ay 1 or Ay2 direction in the figure) on the SiC epitaxial layer, and also extend from one side of the SiC epitaxial layer to the other side. The groove is arranged orthogonally to the P+ deep well, the P+ deep well and the N+ source electrode are cut off, and the cut-off distance is the width of the groove.
In the embodiment of the application, the N+ source of the deep-well type SiC Mosfet device cannot cover all active region positions, the Meas (mesa) region between the grooves needs to be separated from the P+ deep well, the normal opening of a built-in diode at the S-D end of the device is ensured, and the follow current capability of the device is improved.
Referring to fig. 2 and 3, an isolation passivation layer is formed on the surfaces of the n+ source, the p+ deep well and the gate polysilicon layer at the beginning, and a contact hole metal layer is formed in the isolation passivation layer, specifically, on the surfaces of the n+ source, the p+ deep well. After the contact hole metal layer is formed, the isolation passivation layer is only left on the surface part of the gate polysilicon layer. The grid electrode in the active region of the deep-well SiC Mosfet device is a polysilicon trench grid electrode, so that the resistance of the JFET region and the density of the device can be effectively reduced, the mobility of carriers can be increased, and the purposes of reducing the on-resistance of the device and increasing the power density of the device can be achieved.
Optionally, the thickness of the SiC substrate is 200-500 um;
the thickness of the SiC epitaxial layer is 10-20 um;
the implantation depth of the P-body region is 0.5 um-1 um;
the width of the P+ deep well is 2-3 um, the interval is 0.5-1.5 um, and the implantation depth is 1.8-3.0 um;
the width of the groove is 0.5-2.0 um, and the depth is 0.5-2.0 um;
the implantation depth of the N+ source electrode is 0.1-0.5 um, and the width is 0.5-1.5 um.
Optionally, the SiC substrate and the SiC epitaxial layer are both N-doped, the n+ source is heavily doped with N-type, the P-body is heavily doped with P-type, and the gate polysilicon layer is heavily doped with N-type.
The P-type SiC trench MOSFET device is formed by interchanging the N-type doping and P-type doping mentioned above in the present application.
The application also provides a method for preparing the deep well type SiC Mosfet device, which comprises the following steps:
step 101, a lightly doped SiC epitaxial layer is grown on the surface of the SiC substrate, as shown in fig. 5, fig. 5 is a cross-sectional view along the X direction (i.e. the Ax direction in fig. 1) of the deep well SiC Mosfet device, and the drawings of the subsequent steps are all illustrated by taking this direction as an example.
Step 102, a layer of P-body region is implanted on the SiC epitaxial layer, high-temperature annealing is carried out for 10-30 min at 1500-1800 ℃, and the implanted ions are activated, as shown in fig. 6.
And 103, injecting a layer of P+ deep well on the SiC epitaxial layer along the X direction, performing high-temperature annealing for 10-30 min at 1500-1800 ℃ to activate the injected ions, wherein the depth of the P+ deep well exceeds the thickness of the P-body region as shown in FIG. 7, and extending into the SiC epitaxial layer.
And 104, etching the SiC epitaxial layer along the Y direction to form a groove orthogonal to the P+ deep well, modifying the shape of the groove, growing a layer of gate oxide layer on the inner surface of the groove and the surface of the SiC epitaxial layer, and extending the groove depth beyond the thickness of the P-body region into the SiC epitaxial layer as shown in fig. 8.
Step 105, depositing an N-type heavily doped gate polysilicon layer as the gate region of the device, and then etching to the surface of the gate oxide layer, as shown in fig. 9.
And 106, injecting N-type heavily doped nitrogen ions into the surface of the SiC epitaxial layer along the X direction to form an N+ source electrode, and then carrying out high-temperature annealing for 10-30 min at 1500-1800 ℃ to activate the injected ions, as shown in fig. 10.
Step 107, depositing an oxide layer or Si on the surface of the SiC epitaxial layer 3 N 4 An isolation passivation layer is formed as shown in fig. 11.
And 108, forming a contact hole in the isolation passivation layer region, sputtering to form a Ti film, forming ohmic contact on the N+ source electrode through a sintering process at 800-1000 ℃, and depositing a metal layer to form a contact hole metal layer, as shown in FIG. 12.
And 109, depositing a metal layer in a sputtering mode, forming a front source electrode metal layer on the front surface of the deep-well type SiC Mosfet device, and then leading out a front grid electrode metal layer on the periphery of the deep-well type SiC Mosfet device in a polysilicon leading-out mode, as shown in fig. 13.
Step 110, thinning the back of the SiC substrate, and then forming a back drain metal layer on the back of the SiC substrate, as shown in fig. 14.
Optionally, the modification of the trench morphology in step 104 is specifically:
high-temperature passivation treatment is carried out for 10-30 min under the mixed condition that the temperature is 1400-1700 ℃ and the gas atmosphere is one or more of hydrogen, argon and silane.
Optionally, the thickness of the SiC substrate is 200-500 um, the doped ions of the SiC epitaxial layer are nitrogen ions, and the doping concentration of the nitrogen ions is 10 15 ～5×10 15 cm -3 The doping thickness is 10 um-20 um.
The P-body region is implanted by photoetching and ion implantation, the ion implanted in the P-body region is aluminum ion, the implantation depth of the aluminum ion is 0.5 um-1 um, and the implantation concentration of the aluminum ion is 10 17 ～5×10 18 cm -3 。
The P+ deep well is implanted by photoetching, hard mask process and deep ion implantation, the width of the P+ deep well is 2-3 um, the interval is 0.5-1.5 um, the implantation depth is 1.8-3.0 um, the ion implanted by the P+ deep well is aluminum ion, and the implantation concentration of the aluminum ion is 10 17 ～10 19 cm -3 。
Optionally, the trench is formed by photolithography, a hard mask process and an ICP (inductively coupled plasma) etching process, and the width of the trench is 0.5um to 2.0um, and the depth is 0.5um to 2.0um.
The implantation mode of the N+ source electrode is a photoetching and ion implantation mode, the ion implanted into the N+ source electrode is N-type heavily doped nitrogen ion, and the doping concentration of the nitrogen ion is 10 19 ～5×10 20 cm -3 The implantation depth of the N+ source electrode is 0.1 um-0.5 um, and the width is 0.5 um-1.5 um.
The isolation passivation layer is formed by Chemical Vapor Deposition (CVD).
The contact hole and the front source electrode metal layer are formed by photoetching and dry etching processes.
The formation mode of the back drain electrode metal layer is an evaporation mode.
In summary, the application provides a deep-well SiC Mosfet device, which adopts an orthogonal mode of trench and deep-energy ion implantation p+ to reduce on-resistance and device withstand voltage of a power SiC Mosfet and device gate reliability. Meanwhile, the application provides a preparation method of a deep-well type SiC Mosfet device, which comprises the steps of firstly adopting a groove type Mosfet structure to form a channel on the side wall of the groove, eliminating a JFET region caused by a traditional planar type Mosfet structure, thereby realizing the purpose of reducing the on-resistance of the device, and further, because of the characteristics of SiC materials, the mobility of the groove side wall is higher than the mobility of the planar type Mosfet structure in the horizontal direction, and the channel resistance of the groove type Mosfet structure is lower than that of the traditional planar type Mosfet structure. And secondly, forming a P+ deep well at the bottom of a part of the groove of the source region of the device in an orthogonal mode of injecting P+ into the groove and deep energy ions, and better protecting a grid oxide layer at the bottom of the groove by deep injection of the P+ region to prevent the grid oxide layer from being influenced by a high electric field, thereby improving the withstand voltage of the device and the reliability of a grid electrode of the device.
The foregoing description is merely illustrative of the preferred embodiments of the present application, but the scope of the present application is not limited thereto, and any changes or substitutions within the technical scope of the present application should be covered. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.
Claims (5)
1. A deep well SiC Mosfet device, comprising:
a SiC substrate; a SiC epitaxial layer grows on the SiC substrate, a P+ deep well, a groove, a P-body region, an N+ source electrode and an isolation passivation layer are arranged on the SiC epitaxial layer, a gate oxide layer grows on the inner surface of the groove and the surface of the SiC epitaxial layer, a gate polysilicon layer is etched on the surface of the gate oxide layer, a contact hole is formed in the isolation passivation layer region, a metal forming contact hole metal layer is deposited in the contact hole, and ohmic contact is formed between the contact hole metal layer and the N+ source electrode;
the front source electrode metal layer is arranged on the front of the deep-well type SiC Mosfet device;
the back drain electrode metal layer is arranged on the back of the SiC substrate;
the front grid electrode metal layer is arranged on the periphery of the deep well type SiC Mosfet device and is led out from the grid electrode polycrystalline silicon layer;
the N+ source electrode and the P+ deep well are arranged in parallel and isolated from each other, and the groove and the P+ deep well are arranged in an orthogonal mode; the P+ deep well extends from one side to the other side of the P-body region along the X direction of the SiC epitaxial layer, the P+ deep well is arranged into a strip shape which is isolated from each other, and the N+ source electrode is arranged in the P-body region close to the P+ deep well; the depth of the P+ deep well is larger than that of the groove;
the contact hole metal layer is positioned on the surfaces of the N+ source electrode and the P+ deep well, and the isolation passivation layer is positioned on the surface of the grid polycrystalline silicon layer;
the deep-well SiC Mosfet device is prepared by the following steps:
growing a lightly doped SiC epitaxial layer on the surface of the SiC substrate;
injecting a layer of P-body region on the SiC epitaxial layer, and performing high-temperature annealing for 10-30 min at 1500-1800 ℃ to activate the injected ions;
injecting a layer of P+ deep well on the SiC epitaxial layer along the X direction, and performing high-temperature annealing for 10-30 min at 1500-1800 ℃ to activate the injected ions;
etching a groove orthogonal to the P+ deep well on the SiC epitaxial layer along the Y direction, performing high-temperature passivation treatment for 10-30 min under the mixed condition that the temperature is 1400-1700 ℃ and the gas atmosphere is one or more of hydrogen, argon and silane, and growing a layer of grid oxide layer on the inner surface of the groove and the surface of the SiC epitaxial layer;
depositing an N-type heavily doped gate polysilicon layer as a gate region of the device, and etching to the surface of the gate oxide layer;
injecting N-type heavily doped nitrogen ions into the surface of the SiC epitaxial layer along the X direction to form an N+ source electrode, and then carrying out high-temperature annealing for 10-30 min at 1500-1800 ℃ to activate the injected ions;
depositing an oxide layer or Si3N4 on the surface of the SiC epitaxial layer to form an isolation passivation layer;
forming a contact hole in the isolation passivation layer region, sputtering to form a Ti film, forming ohmic contact on the N+ source electrode through a sintering process at 800-1000 ℃, and depositing a metal layer to form a contact hole metal layer;
depositing a metal layer in a sputtering mode, forming a front source electrode metal layer on the front surface of the deep well type SiC Mosfet device, and then leading out a front grid electrode metal layer on the periphery of the deep well type SiC Mosfet device in a polysilicon leading-out mode;
and thinning the back of the SiC substrate, and then forming a back drain metal layer on the back of the SiC substrate.
2. The deep well SiC Mosfet device of claim 1, wherein:
the trenches are arranged in stripes spaced apart from each other in the Y-direction on the SiC epitaxial layer, and the trenches extend from one side of the SiC epitaxial layer to the other side.
3. The deep well SiC Mosfet device of claim 1, wherein:
the thickness of the SiC substrate is 200-500 um;
the thickness of the SiC epitaxial layer is 10-20 um;
the implantation depth of the P-body region is 0.5 um-1 um;
the width of the P+ deep well is 2-3 um, the interval is 0.5-1.5 um, and the implantation depth is 1.8-3.0 um;
the width of the groove is 0.5-2.0 um, and the depth is 0.5-2.0 um;
the implantation depth of the N+ source electrode is 0.1-0.5 um, and the width is 0.5-1.5 um.
4. A deep well SiC Mosfet device according to any one of claims 1-3, characterized in that:
the doped ions of the SiC epitaxial layer are nitrogen ions, and the doping concentration of the nitrogen ions is10 15 ～5×10 15 cm -3 ；
The P-body region is implanted by photoetching and ion implantation, the ion implanted in the P-body region is aluminum ion, and the implantation concentration of the aluminum ion is 10 17 ～5×10 18 cm -3 ；
The implantation mode of the P+ deep well is photoetching, hard mask technology and deep energy ion implantation mode, the ions implanted by the P+ deep well are aluminum ions, and the implantation concentration of the aluminum ions is 10 17 ～10 19 cm -3 。
5. The deep well SiC Mosfet device of claim 4, wherein:
the trench is formed by photolithography, a hard mask process and an ICP (inductively coupled plasma) etching process;
the injection mode of the N+ source electrode is a photoetching and ion injection mode;
the isolation passivation layer is formed by Chemical Vapor Deposition (CVD);
the contact hole and the front source electrode metal layer are formed by photoetching and dry etching processes;
the formation mode of the back drain electrode metal layer is an evaporation mode.
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