CN111755522B - Silicon carbide UMOSFET device integrated with TJBS - Google Patents
Silicon carbide UMOSFET device integrated with TJBS Download PDFInfo
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7827—Vertical transistors
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- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
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- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
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- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
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- H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System
- H01L29/1608—Silicon carbide
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- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
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- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
- H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
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- H01L29/66068—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7839—Field effect transistors with field effect produced by an insulated gate with Schottky drain or source contact
Abstract
The invention relates to a silicon carbide UMOSFET device integrated with TJBS, which comprises: the N + substrate region, the N-epitaxial region, the P-well region, the N + injection region, the first P + injection region, the second P + injection region, the grid electrode, the source electrode and the drain electrode, wherein the second P + injection region and the first P + injection region are arranged at intervals and have the same depth, a first groove is arranged in the first P + injection region, a second groove is arranged in the second P + injection region, the depth of the grid electrode is larger than that of the P-well region and smaller than that of the first P + injection region, the source electrode is in ohmic contact with the P-well region, the N + injection region, the first P + injection region and the second P + injection region, and the source electrode is in Schottky contact with the N-epitaxial region. According to the device, the groove structure is introduced into the Schottky diode structure integrated in the device, so that the depths of the first P + injection region and the second P + injection region are increased, and P + injection is performed on the surface of the thin N-epitaxial region formed by etching, so that the depth of the P + injection region is larger, and the avalanche resistance of the device is improved.
Description
Technical Field
The invention belongs to the technical field of semiconductors, and particularly relates to a silicon carbide UMOSFET device integrated with TJBS.
Background
In recent years, with the continuous development of power electronic systems, higher requirements are put on power devices in the systems. Silicon (Si) -based power electronic devices have not been able to meet the requirements of system applications due to the limitations of the materials themselves, and silicon carbide (SiC) materials, as a representative of third-generation semiconductor materials, are far better than silicon materials in many properties. A silicon carbide MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) device has a great potential to replace an existing IGBT (Insulated Gate Bipolar Transistor) in terms of on-resistance, switching time, switching loss, heat dissipation performance, and the like as a device commercialized in recent years.
Compared with the MOSFET with a transverse structure, the UMOSFET with the vertical structure has the advantages of small on-resistance and small cell size, and has wide application prospect. However, because the forbidden band width of the silicon carbide material is large, the turn-on voltage of a parasitic PiN diode integrated in the silicon carbide UMOSFET device is mostly about 3V, and the parasitic PiN diode cannot provide a freewheeling function for the device, so that the freewheeling capability of the device is weak. Therefore, in power electronic system applications such as full-bridge, an additional schottky diode is often connected in anti-parallel to be used as a freewheeling diode, which greatly increases the complexity and cost of the circuit system. In addition, in the blocking mode, a series of reliability problems are caused by the strong electric field of gate oxide at the corners of the gate trench.
Disclosure of Invention
In order to solve the above problems in the prior art, the present invention provides a TJBS-integrated silicon carbide UMOSFET device. The technical problem to be solved by the invention is realized by the following technical scheme:
the invention provides a silicon carbide UMOSFET device integrated with TJBS, which comprises:
an N + substrate region;
an N-epitaxial region disposed on the N + substrate region;
a P-well region disposed on the N-epitaxial region;
an N + injection region disposed on the P-well region;
the first P + injection region is positioned in the N-epitaxial region, and a first groove is formed in the first P + injection region;
the second P + injection region is positioned in the N-epitaxial region and is arranged at an interval with the first P + injection region, and a second groove is formed in the second P + injection region;
the grid electrode is arranged adjacent to the P-well region and the N + injection region, is partially positioned in the N-epitaxial region and the first P + injection region, and has a depth smaller than that of the first P + injection region;
the source electrode is arranged on the side walls of the P-well region and the N + injection region, the first P + injection region, the N-epitaxial region and the second P + injection region, and the interface of the source electrode and the N-epitaxial region is in Schottky contact;
and the drain electrode is arranged on the lower surface of the N + substrate region.
In an embodiment of the invention, the source and the P-well region, the N + implantation region, the first P + implantation region, and the second P + implantation region have ohmic contacts at their interfaces.
In one embodiment of the present invention, the depth of the second P + implant region coincides with the depth of the first P + implant region.
In one embodiment of the invention, the gate comprises a gate groove and a gate layer arranged inside the gate groove, and a gate dielectric layer is arranged between the inner wall of the gate groove and the gate layer.
In one embodiment of the invention, the depth of the gate trench is 0.7 μm to 2 μm and the width is 0.5 μm to 2 μm.
In one embodiment of the invention, the depth of the P-well region is 0.3-1.0 μm, the width is 0.3-1.0 μm, the P-well region is Gaussian doped, and the surface doping concentration is 5 x 1016cm-3Peak doping concentration of 5X 1018cm-3The depth of the N + injection region is 0.1-0.5 μm, the width is 0.3-1 μm, and the doping concentration is 1 × 1019-1×1020cm-3。
In one embodiment of the present invention, the first P + implantation region and the second P + implantation region have a depth of 1.7 μm to 5 μm and a doping concentration of 1 × 1019-1×1020cm-3The width of the first P + injection region is 1.2-1.5 μm, and the width of the second P + injection region is 0.5-1 μm.
In one embodiment of the present invention, the gate electrode inside the first P + implantation region has a width of 0.2 μm to 0.7 μm.
In one embodiment of the present invention, the first P + implant region and the second P + implant region have a spacing of 1.5 μm to 5 μm.
In one embodiment of the present invention, the first trench and the second trench have a depth of 0.3 μm to 2.3 μm and a width of 0.5 μm to 1.5 μm.
Compared with the prior art, the invention has the beneficial effects that:
1. according to the silicon carbide UMOSFET device integrated with the TJBS, the groove structure is introduced into the Schottky diode structure integrated in the device, so that the follow current capability of the device is improved, the cell area of the device is prevented from being wasted due to overlarge Schottky contact area, and the preparation cost of the device is reduced.
2. According to the TJBS-integrated silicon carbide UMOSFET device, the groove structures are introduced into the first P + injection region and the second P + injection region, so that the depths of the first P + injection region and the second P + injection region are increased, the surface electric field of a Schottky contact region can be effectively reduced, the blocking leakage current of a Schottky diode is effectively reduced, the avalanche resistance of the device is improved, the power consumption of the device is reduced, and the performance of the device is improved.
3. According to the TJBS-integrated silicon carbide UMOSFET device, the depth of the first P + injection region and the depth of the second P + injection region are larger than the depth of the gate groove, and the first P + injection region surrounds part of the gate groove, so that the electric field at the corner of the gate groove can be effectively reduced, and the breakdown characteristic of the device is further improved.
4. According to the silicon carbide UMOSFET device integrated with the TJBS, the groove structure is introduced into the surface of the thin N-epitaxial region formed by etching, so that the depths of the first P + injection region and the second P + injection region are greatly increased, the surface electric field of the Schottky contact region can be effectively reduced, the blocking leakage current of the Schottky diode is reduced, and the power consumption of the device is further reduced.
The foregoing description is only an overview of the technical solutions of the present invention, and in order to make the technical means of the present invention more clearly understood, the present invention may be implemented in accordance with the content of the description, and in order to make the above and other objects, features, and advantages of the present invention more clearly understood, the following preferred embodiments are described in detail with reference to the accompanying drawings.
Drawings
Fig. 1 is a schematic structural diagram of a TJBS-integrated silicon carbide UMOSFET device according to an embodiment of the present invention;
fig. 2 a-2 i are schematic process diagrams of a TJBS-integrated silicon carbide UMOSFET device according to an embodiment of the present invention.
A 1-N + substrate region; a 2-N-epitaxial region; a 3-P-well region; a 4-N + implant region; 5-a first P + implant region; 6-a first trench; 7-a second P + implant region; 8-a second trench; 9-a source electrode; 10-a drain electrode; 11-a gate trench; 12-a gate layer; 13-gate dielectric layer.
Detailed Description
To further illustrate the technical means and effects of the present invention for achieving the predetermined objects, a TJBS-integrated silicon carbide UMOSFET device according to the present invention will be described in detail with reference to the accompanying drawings and the following detailed description.
The foregoing and other technical matters, features and effects of the present invention will be apparent from the following detailed description of the embodiments, which is to be read in connection with the accompanying drawings. The technical means and effects of the present invention adopted to achieve the predetermined purpose can be more deeply and specifically understood through the description of the specific embodiments, however, the attached drawings are provided for reference and description only and are not used for limiting the technical scheme of the present invention.
Example one
Referring to fig. 1, fig. 1 is a schematic structural diagram of a TJBS (trench junction Barrier schottky) integrated silicon carbide UMOSFET device according to an embodiment of the present invention. As shown, the TJBS integrated silicon carbide UMOSFET device of the present embodiment includes:
an N + substrate region 1;
an N-epitaxial region 2 disposed on the N + substrate region 1;
a P-well region 3 disposed on the N-epitaxial region 2;
an N + injection region 4 disposed on the P-well region 3;
the first P + injection region 5 is positioned in the N-epitaxial region 2, and a first groove 6 is formed in the first P + injection region 5;
the second P + injection region 7 is positioned in the N-epitaxial region 2 and is arranged at an interval with the first P + injection region 5, and a second groove 8 is arranged in the second P + injection region 7;
the grid electrode is arranged adjacent to the P-well region 3 and the N + injection region 4, is partially positioned in the N-epitaxial region 2 and the first P + injection region 5, and has a depth smaller than that of the first P + injection region 5;
the source electrode 9 is arranged on the side walls of the P-well region 3 and the N + injection region 4, the first P + injection region 5, the N-epitaxial region 2 and the second P + injection region 7, and the interface of the source electrode 9 and the N-epitaxial region 2 is in Schottky contact;
and a drain electrode 10 disposed on the lower surface of the N + substrate region 1.
Specifically, the source 9 covers the P-well region 3, the side surface of the N + implantation region 4, the upper surface of a part of the N + implantation region 4, the inner surface of the first trench 6, the inner surface of the second trench 8, the upper surface of the N-epitaxial region 2 between the first P + implantation region 5 and the second P + implantation region 7, the upper surface of the second P + implantation region 7, and the upper surface of the first P + implantation region 5 on the side close to the second P + implantation region 7.
In the present embodiment, the source 9 and the P-well region 3, the N + implantation region 4, the first P + implantation region 5, and the second P + implantation region 7 are in ohmic contact at their interfaces.
In the present embodiment, the gate includes a gate trench 11 and a gate layer 12 disposed inside the gate trench 11, and a gate dielectric layer 13 is disposed between an inner wall of the gate trench 11 and the gate layer 12. The depth of the second P + implant region 7 coincides with the depth of the first P + implant region 5. I.e. the depth of both the first P + implant region 5 and the second P + implant region 7 is greater than the depth of the gate trench 11.
In this embodiment, the schottky contact is located between the first P + implant region 5 and the second P + implant region 7, i.e. the corresponding trench junction barrier schottky diode is located between two adjacent sources (the first P + implant region 5 and the second P + implant region 7) in the MOSFET device. In the Schottky diode structure integrated in the device, the groove structures (the first groove 6 and the second groove 8) are introduced, so that the follow current capability of the device is improved, the cell area of the device is prevented from being wasted due to overlarge Schottky contact area, and the preparation cost of the device is reduced.
Furthermore, due to the fact that the groove structures are introduced into the first P + injection region 5 and the second P + injection region 7, the depths of the first P + injection region 5 and the second P + injection region 7 are increased, the surface electric field of the Schottky contact region can be effectively reduced, the blocking leakage current of the Schottky diode is effectively reduced, the anti-avalanche capability of the device is improved, the power consumption of the device is reduced, and the performance of the device is improved.
In this embodiment, the depth of the first P + implantation region 5 and the second P + implantation region 7 is greater than the depth of the gate trench 11 (i.e., the gate), and the first P + implantation region 5 surrounds part of the gate trench 11, so that a high electric field at the corner of the gate trench 11 can be effectively shielded, the gate oxide reliability and the device voltage endurance capability are improved, and the breakdown characteristic of the device is further improved.
In the silicon carbide UMOSFET device integrated with the TJBS of the embodiment, the thin N-epitaxial region 2 is obtained by etching, and the trench structures (the first trench 6 and the second trench 8) are introduced into the surface of the etched N-epitaxial region 2, so that the depths of the first P + injection region 5 and the second P + injection region 7 are greatly increased, and the surface electric field of the schottky contact region can be effectively reduced, thereby reducing the blocking leakage current of the schottky diode, and further reducing the power consumption of the device.
Preferably, the gate groove 11 has a depth of 0.7 μm to 2 μm and a width of 0.5 μm to 2 μm. If the depth of the gate trench 11 is too large, the difficulty of manufacturing will be increased, and if the depth is too small, the effect of increasing the junction depth will not be obvious. Too small a width of the gate trench 11 is not favorable for a corresponding increase in junction depth.
Alternatively, the N + substrate region 1 has a thickness of 200 μm-500 μm and a doping concentration of 5 × 1018cm-3。
Optionally, the N-epitaxial region 2 has a thickness of 6 μm to 12 μm and a doping concentration of 6 × 1015cm-3。
Alternatively, the P-well region 3 has a depth of 0.3 μm to 1.0 μm and a width of 0.3 μm to 1.0 μm, the P-well region 3 is Gaussian doped, and the surface doping concentration is 5 × 1016cm-3Peak doping concentration of 5X 1018cm-3。
Optionally, the N + implant region 4 has a depth of 0.1 μm to 0.5 μmWidth of 0.3-1 μm, and doping concentration of 1 × 1019-1×1020cm-3。
Optionally, the depth of the first P + implantation region 5 and the second P + implantation region 7 is 1.7 μm to 5 μm, and the doping concentration is 1 × 1019-1×1020cm-3The width of the first P + implantation region 5 is 1.2 μm to 1.5 μm, and the width of the second P + implantation region 7 is 0.5 μm to 1 μm.
Alternatively, the gate electrode inside the first P + implantation region 5 has a width of 0.2 μm to 0.7 μm, that is, the left edge of the first P + implantation region 5 has a length of 0.2 μm to 0.7 μm from the right edge of the gate trench 11.
Preferably, the spacing between the first and second P + implant regions 5, 7 is between 1.5 μm and 5 μm. If the distance between the first P + injection region 5 and the second P + injection region 7 is too small, the corresponding schottky contact region cannot be well conducted, and if the distance between the first P + injection region 5 and the second P + injection region 7 is too large, the leakage current of the whole device is too large, and the area of the device is too large, which is not beneficial to the improvement of the performance of the device.
Preferably, the first trenches 6 and the second trenches 8 have a depth of 0.3 μm to 2.3 μm and a width of 0.5 μm to 1.5 μm. If the depth of the first trench 6 and the second trench 8 is too large, the manufacturing difficulty is increased, and if the depth is too small, the junction depth increasing effect is not obvious. Correspondingly, if the widths of the first trench 6 and the second trench 8 are too large, the device area will be wasted, and the width is too small, which is not favorable for increasing the junction depth.
In the present embodiment, the gate layer 12 is made of polysilicon material, and the gate dielectric layer 13 is made of SiO2A material. The source electrode 9 is made of titanium, nickel, molybdenum or tungsten material, and the drain electrode 10 is made of titanium, nickel or silver material.
The silicon carbide UMOSFET device integrated with the TJBS integrates a Schottky diode structure in the device, avoids the need of connecting extra Schottky diodes in an anti-parallel mode in the application process as freewheeling diodes, improves the freewheeling capacity of the device, reduces the cell area of the device and reduces the preparation cost of the device. The groove structures (the first groove 6 and the second groove 8) are introduced into the first P + injection region 5 and the second P + injection region 7, so that the depths of the first P + injection region 5 and the second P + injection region 7 are increased, the surface electric field of a Schottky contact region can be effectively reduced, the blocking leakage current of the Schottky diode is effectively reduced, the avalanche resistance of the device is improved, the power consumption of the device is reduced, and the performance of the device is improved.
In addition, the depth of the first P + implantation region 5 and the second P + implantation region 7 is greater than the depth of the gate trench 11, and the first P + implantation region 5 surrounds part of the gate trench 11, so that the electric field at the corner of the gate trench 11 can be effectively reduced, and the breakdown characteristic of the device can be further improved. And moreover, a groove structure is introduced into the surface of the thin N-epitaxial region 2 formed by etching, so that the depths of the first P + injection region 5 and the second P + injection region 7 are greatly increased, and the power consumption of the device is further reduced.
Example two
Referring to fig. 2a to fig. 2i, fig. 2a to fig. 2i are schematic process diagrams of a silicon carbide UMOSFET device integrated with TJBS according to an embodiment of the present invention, and the method includes the following steps:
step a: an N-epitaxial region 2 is formed by epitaxial growth on the N + substrate region 1 as shown in fig. 2 a.
Firstly, the thickness is 350 μm, the doping concentration is 5 × 1018cm-3The SiC substrate of (1) is subjected to RCA standard cleaning, and then is epitaxially grown on the N + substrate region 1 to a thickness of 10 μm and a doping concentration of 6 × 1015cm-3N-epitaxial region 2.
Step b: the etching forms a thinner N-epitaxial region 2 as shown in fig. 2 b.
Depositing a mask layer on the upper surface of the N-epitaxial region 2, forming a mask pattern by a photoetching process, etching the N-epitaxial region 2 with partial depth shown in figure 2b by an ICP (inductively coupled plasma) etching method to form a thinner N-epitaxial region 2, and finally removing the photoresist and etching the mask layer.
Step c: a first trench 6 and a second trench 8 are etched, as shown in fig. 2 c.
Depositing a mask layer on the N-epitaxial region 2, forming a mask pattern by a photoetching process, etching the N-epitaxial region 2 by an ICP (inductively coupled plasma) etching method to form a first groove 6 and a second groove 8, wherein the width of the first groove 6 and the depth of the second groove 8 are 1 mu m and 1.3 mu m, and finally removing the photoresist and etching the mask layer.
Step d: well implantation is performed on the upper surface of the N-epitaxial region 2 to form a P-well region 3, and N ion implantation is performed in the P-well region 3 to form an N + implantation region 4, as shown in fig. 2 d.
Depositing a mask layer on the N-epitaxial region 2, forming a mask pattern by a photoetching process, performing trap injection on the surface of the N-epitaxial region 2 of the protruding part, wherein the injected ions are Al ions and the doping concentration is 5 multiplied by 1016cm-3Forming a P-well region 3. N ion implantation is performed in the P-well region 3 with a doping concentration of 1 × 1019cm-3And forming an N + injection region 4, finally removing the photoresist and etching the mask layer.
Step e: ion implantation is performed on the upper surface of the N-epi region 2 to form a first P + implant region 5 and a second P + implant region 7, as shown in fig. 2 e.
Depositing a mask layer on the N-epitaxial region 2, forming a mask pattern by a photoetching process, and implanting partial surface of the N-epitaxial region 2 and inner walls of the first trench 6 and the second trench 8 by Al ion implantation with a doping concentration of 1 × 1019cm-3And forming a first P + injection region 5 and a second P + injection region 7, and finally removing the photoresist and etching the mask layer. Wherein the first P + implant region 5 surrounds the first trench 6 and the second P + implant region 7 surrounds the second trench 8. The first P + implant region 5 is located at the right side of the P-well region 3 and the N + implant region 4, the first P + implant region 5 has a spacing from the second P + implant region 7, and the distance of the spacing is controlled to be 2 μm. The first and second P + implant regions 5 and 7 are of equal depth and greater than the depth of the P-well region 3.
In this embodiment, after ion implantation is completed, a carbon film is formed on the upper surface of the device by using a carbon film sputtering machine, and then the implanted ions (all the implanted ions) are activated by high-temperature annealing at 1650 ℃ for 45min, and then the carbon film is removed by an oxidation method.
Step f: the gate trench 11 is etched as shown in figure 2 f.
Depositing a mask layer on the upper surface of the device, forming a mask pattern by a photoetching process, etching the N + injection region 4 with partial width, the P-well region 3 with partial width, the first P + injection region 5 with partial width and the N-epitaxial region 2 with partial depth by an ICP (inductively coupled plasma) etching method to form a gate groove 11, wherein the width of the gate groove 11 is 1.2 mu m, the depth is 1.4 mu m, and finally removing the photoresist and etching the mask layer. In this embodiment, the length of the right edge of the gate trench 11 from the left edge of the first P + implant region 5 is 0.4 μm.
Step g: and preparing a grid electrode, as shown in figure 2 g.
And performing sacrificial oxidation on the inner surface of the gate groove 11 to form a sacrificial oxide layer, removing the sacrificial oxide layer, growing a layer of silicon dioxide serving as a gate dielectric layer 13 by adopting a thermal oxidation method, and annealing in a nitrogen oxide atmosphere at the annealing temperature of 1200 ℃ for 1 h. And depositing a high-doped polycrystalline silicon layer by adopting a chemical vapor deposition method, and then photoetching and etching to form the polycrystalline silicon gate electrode layer 12.
Step h: a source electrode 9 is prepared as shown in fig. 2 h.
And depositing metal aluminum on the left side wall of the P-well region 3, the left side wall and part of the upper surface of the N + injection region 4, the upper surface of the first P + injection region 5 close to one side of the second P + injection region 7, the inner surface of the first groove 6, the upper surface of the second P + injection region 7 and the inner surface of the second groove 8, and performing a rapid thermal annealing process under an argon atmosphere at the annealing temperature of 1000 ℃ for 3min to form ohmic contact at the interfaces of the metal aluminum and the P-well region 3, the N + injection region 4, the first P + injection region 5 and the second P + injection region 7. And depositing metal titanium on the N-epitaxial region 2 between the first P + injection region 5 and the second P + injection region 7, and performing a low-temperature rapid thermal annealing process at the annealing temperature of 500 ℃ for 2min to form Schottky contact at the interface of the metal titanium and the N-epitaxial region 2. The source electrode 9 is composed of metal aluminum and metal titanium, and the ohmic contact and the Schottky contact are connected.
Step i: the drain 10 is prepared as shown in fig. 2 i.
Titanium metal is deposited on the lower surface of the N + substrate region 1 as a drain 10.
It is noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that an article or device that comprises a list of elements does not include only those elements but may include other elements not expressly listed. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of additional like elements in the article or device comprising the element. The terms "connected" or "coupled" and the like are not restricted to physical or mechanical connections, but may include electrical connections, whether direct or indirect. The directional or positional relationships indicated by "upper", "lower", "left", "right", etc., are based on the directional or positional relationships shown in the drawings, and are only for convenience of describing the present invention and simplifying the description, but do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus should not be construed as limiting the present invention.
The foregoing is a more detailed description of the invention in connection with specific preferred embodiments and it is not intended that the invention be limited to these specific details. For those skilled in the art to which the invention pertains, several simple deductions or substitutions can be made without departing from the spirit of the invention, and all shall be considered as belonging to the protection scope of the invention.
Claims (9)
1. A TJBS-integrated silicon carbide UMOSFET device, comprising:
an N + substrate region (1);
an N-epitaxial region (2) disposed on the N + substrate region (1);
a P-well region (3) disposed on the N-epitaxial region (2);
an N + injection region (4) disposed on the P-well region (3);
the first P + injection region (5) is positioned in the N-epitaxial region (2), and a first groove (6) is formed in the first P + injection region (5);
the second P + injection region (7) is positioned in the N-epitaxial region (2) and is arranged at a distance from the first P + injection region (5), and a second groove (8) is arranged in the second P + injection region (7); the second P + injection region (7) is arranged on one side far away from the P-well region (3);
a gate arranged adjacent to the P-well region (3) and the N + implant region (4) and partially inside the N-epitaxial region (2) and the first P + implant region (5), the depth of the gate being smaller than the depth of the first P + implant region (5); the corner of the lower end of the grid electrode, which is far away from the P-well region (3), is positioned inside the first P + injection region (5);
the source electrode (9) is arranged on the side walls of the P-well region (3) and the N + injection region (4) and on the N + injection region (4), the first P + injection region (5), the N-epitaxial region (2) and the second P + injection region (7), and the interface of the source electrode (9) and the N-epitaxial region (2) is in Schottky contact;
the drain electrode (10) is arranged on the lower surface of the N + substrate region (1);
the width of the grid electrode positioned in the first P + injection region (5) is 0.2-0.7 μm.
2. The TJBS-integrated silicon carbide UMOSFET device of claim 1, wherein the source (9) and P-well region (3), N + implant region (4), first P + implant region (5), and second P + implant region (7) interface is an ohmic contact.
3. The TJBS-integrated silicon carbide UMOSFET device of claim 1, wherein a depth of the second P + implant region (7) coincides with a depth of the first P + implant region (5).
4. The TJBS-integrated silicon carbide UMOSFET device according to claim 1, wherein the gate comprises a gate trench (11) and a gate layer (12) arranged inside the gate trench (11), and a gate dielectric layer (13) is arranged between the inner wall of the gate trench (11) and the gate layer (12).
5. The TJBS-integrated silicon carbide UMOSFET device according to claim 4, wherein the gate trench (11) has a depth of 0.7 μm to 2 μm and a width of 0.5 μm to 2 μm.
6. The TJBS-integrated silicon carbide UMOSFET device as claimed in claim 1, wherein the P-well region (3) has a depth of 0.3 μm to 1.0 μm and a width of 0.3 μm to 1.0 μm, the P-well region (3) is gaussian doped and has a surface doping concentration of 5 x 1016cm-3Peak doping concentration of 5X 1018cm-3The depth of the N + injection region (4) is 0.1-0.5 μm, the width is 0.3-1 μm, and the doping concentration is 1 × 1019-1×1020cm-3。
7. The TJBS-integrated silicon carbide UMOSFET device of claim 1, wherein the first P + implant region (5) and the second P + implant region (7) have a depth of 1.7 μm to 5 μm and a doping concentration of 1 x 1019-1×1020cm-3The width of the first P + injection region (5) is 1.2-1.5 μm, and the width of the second P + injection region (7) is 0.5-1 μm.
8. The TJBS-integrated silicon carbide UMOSFET device of claim 1, wherein a spacing between the first P + implant region (5) and the second P + implant region (7) is 1.5 μ ι η -5 μ ι η.
9. The TJBS-integrated silicon carbide UMOSFET device of claim 1, wherein the first trench (6) and the second trench (8) have a depth of 0.3 μ ι η to 2.3 μ ι η and a width of 0.5 μ ι η to 1.5 μ ι η.
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| CN101978502A (en) * | 2008-03-17 | 2011-02-16 | 三菱电机株式会社 | Semiconductor device |
| CN106298469A (en) * | 2015-05-13 | 2017-01-04 | 国网智能电网研究院 | A kind of ion injection method of SiC JBS device |
| CN109742148A (en) * | 2019-01-16 | 2019-05-10 | 厦门芯光润泽科技有限公司 | Silicon carbide UMOSFET device and preparation method thereof |
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