CN112838126A - Asymmetric silicon carbide UMOSFET device with shielding region and preparation method - Google Patents

Asymmetric silicon carbide UMOSFET device with shielding region and preparation method Download PDF

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CN112838126A
CN112838126A CN202110174578.9A CN202110174578A CN112838126A CN 112838126 A CN112838126 A CN 112838126A CN 202110174578 A CN202110174578 A CN 202110174578A CN 112838126 A CN112838126 A CN 112838126A
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region
groove
injection
injection region
silicon carbide
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施广彦
秋琪
李昀佶
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Global Power Technology Co Ltd
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Global Power Technology Co Ltd
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    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7827—Vertical transistors
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    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
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    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
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    • H01L29/1608—Silicon carbide
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    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66053—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide
    • H01L29/66068—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices

Abstract

The invention provides an asymmetric silicon carbide UMOSFET device with a shielding region and a preparation method thereof; the device comprises a second metal, an N + substrate and an N-epitaxial layer from bottom to top; the N-epitaxial layer is provided with a first P-well region, a first N + injection region, a first P + injection region, a second P + injection region, a first groove and a second groove; further comprising: a first metal covering a portion of the first N + injection region upper surface, the first P-well region side surface and the second P + injection region upper surface to form an ohmic contact; the electric field concentration phenomenon at two groove corners of the gate oxide layer is effectively shielded or relieved by utilizing the deep P + shielding region and the P + injection region partially surrounding the groove corners, so that the reverse voltage-resisting capability and the use reliability of the device are improved.

Description

Asymmetric silicon carbide UMOSFET device with shielding region and preparation method
[ technical field ] A method for producing a semiconductor device
The invention relates to the field of semiconductors, in particular to an asymmetric silicon carbide UMOSFET device with a shielding region and a preparation method thereof.
[ background of the invention ]
In recent years, with the continuous development of power electronic systems, higher requirements are put on power devices in the systems, and silicon (Si) -based power electronic devices cannot meet the requirements of system applications due to the limitation of materials per se.
Silicon carbide (SiC) materials, as representative of third generation semiconductor materials, are far superior to silicon materials in many properties. Silicon carbide MOSFET devices, as commercial devices in recent years, have great potential to replace existing IGBTs in terms of on-resistance, switching time, switching loss, heat dissipation performance, and the like.
In silicon carbide UMOSFETs, since the gate oxide layer has a trench-shaped configuration, the electric field generated at the corners is concentrated more than the electric field in the drift region of the device, so that the gate oxide layer may be broken down before the breakdown of the body region occurs, which greatly affects the reliability of the device. Therefore, researchers have used various gate oxide reinforcement structures to attenuate the electric field concentration phenomenon at the corners of the silicon carbide UMOSFET gate oxide, thereby improving device performance.
[ summary of the invention ]
The invention aims to solve the technical problem of providing an asymmetric silicon carbide MOSFET device with a shielding region and a preparation method thereof.
One of the present invention is realized by: an asymmetric silicon carbide UMOSFET device with a shielded region includes
A second metal as a drain electrode;
an N + substrate, one side of the N + substrate is connected to the second metal;
the other side of the N + substrate is connected to the N-epitaxial layer;
the first P + injection region is L-shaped and is connected with the N-epitaxial layer;
the second P + injection region is L-shaped and is connected with the N-epitaxial layer;
a first P-well region connected to the second P + implant region and the N-epitaxial layer;
a first N + implant region connected to the first P-well region;
the first groove is respectively connected with the N-epitaxial layer, the first P + injection region, the first P-well region and the first N + injection region;
the second groove is respectively connected with the second P + injection region, the first P-well region and the first N + injection region;
the gate dielectric layer covers the side surface of the first groove and the upper surface of the groove bottom;
the grid electrode covers the upper surface of the grid dielectric layer and fills the first groove;
and the first metal covers the set position of the upper surface of the first N + injection region, the side surface of the first P-well region and the upper surface of the second P + injection region to form ohmic contact.
Furthermore, the depth of the first groove is 1-3 μm, and the width is 0.5-2 μm; the depth of the second groove is 1-3 μm, and the width is 0.5-2 μm.
Furthermore, the depth of the first P + injection region is 1.5-3 μm, and the width is 0.8-2 μm; the depth of the second P + injection region is 2-3 mu m, and the width is 1-2 mu m.
Furthermore, the depth of the first P-well region is 0.3-1.0 μm, and the width is 0.3-1 μm; the depth of the first N + injection region is 0.1-0.5 μm, and the width is 0.3-1 μm.
Further, the depth of the first P + implantation region is greater than the depth of the first trench, and the depth of the second P + implantation region is greater than the depth of the second trench.
Further, the depth of the first trench and the second trench is greater than the depth of the first P-well region.
Further, the distance between the left side of the first P + injection region and the right side of the first groove is 0.5-0.7 μm.
Furthermore, the distance between the right side of the second P + injection region and the left side of the first groove is 0.1-0.3 μm.
The second invention is realized by the following steps: a preparation method of an asymmetric silicon carbide UMOSFET device with a shielding region comprises the following steps:
forming an N-epitaxial layer on an N + substrate;
performing P + region injection on the surface of part of the N-epitaxial layer to form a first P + injection region and a second P + injection region;
performing N + region implantation on a set position on the surface of the N-epitaxial layer to form a transition N + implantation region;
performing P-region implantation on the surface of the transition N + implantation region to form a first P-well region;
performing N + region injection on the surface of the P-region to form a first N + injection region;
etching the set positions of the first N + region, the first P-well region, the first P + injection region and the second P + injection region to form a first groove and a second groove;
the left side wall of the first groove is provided with a first P-well region and a first N + injection region;
the P + injection region on the right side wall of the first groove becomes a first P + injection region;
the right side wall of the second groove is provided with a first P-well region and a first N + injection region;
the right P + injection region on the right side wall of the second groove becomes a second P + injection region;
forming a gate dielectric layer to cover the surface of the first groove;
forming a grid electrode on the upper surface of the grid dielectric layer;
forming a first metal covering a portion of the first N + implantation region upper surface, the first N + implantation region side surface, the first P-well region side surface, and the second P + implantation region upper surface to form an ohmic contact;
a drain electrode is formed on the N + substrate.
Further, the forming process of the ohmic contact comprises the following steps: and carrying out a rapid thermal annealing process under an argon atmosphere.
The invention has the advantages that: according to the asymmetric silicon carbide MOSFET device with the shielding region and the preparation method, half of a channel is sacrificed in the device, and the deep P + injection region partially surrounding a groove corner is introduced, so that the electric field concentration phenomenon at the groove corner on the right side of a grid oxide layer is shielded on the premise of ensuring that the forward current is large enough.
A second groove is formed by etching part of the first N + injection region, the first P-well region and the second P + injection region, and the deeper second P + injection region is formed to serve as a P + shielding layer, so that the electric field concentration phenomenon at the groove corner on the left side of the gate oxide layer is effectively relieved, and the voltage endurance capability and the working reliability of the device are improved.
[ description of the drawings ]
The invention will be further described with reference to the following examples with reference to the accompanying drawings.
FIG. 1 is a schematic diagram of an asymmetric silicon carbide UMOSFET device with a shielded region according to the present invention;
FIG. 2 is a first schematic diagram of a corresponding structure of a step of fabricating an asymmetric silicon carbide UMOSFET device with a screening region;
FIG. 3 is a schematic diagram of a corresponding structure of the steps for fabricating an asymmetric silicon carbide UMOSFET device with a screening region;
FIG. 4 is a schematic diagram showing the structure corresponding to step three of fabricating an asymmetric silicon carbide UMOSFET device with a screening region;
FIG. 5 is a structural diagram four corresponding to the steps for fabricating an asymmetric silicon carbide UMOSFET device with a screening region;
FIG. 6 is a fifth structural schematic diagram corresponding to the steps for fabricating an asymmetric silicon carbide UMOSFET device with a screening region;
fig. 7 is a diagram six of the corresponding structure of the steps for fabricating an asymmetric silicon carbide UMOSFET device with a screening region.
[ detailed description ] embodiments
The embodiment of the invention provides an asymmetric silicon carbide MOSFET device with a shielding region and a preparation method thereof, solves the technical problems of poor withstand voltage capability and unreliable work in the prior art, and realizes the technical effects of effectively relieving the electric field concentration phenomenon at the left groove corner of a grid oxide layer, thereby improving the withstand voltage capability and the work reliability of the device.
In order to solve the above problems, the technical solution in the embodiments of the present invention has the following general idea:
example 1
As shown in fig. 1, the present embodiment provides an asymmetric silicon carbide UMOSFET device with a shielding region, the device comprising: a bottom-up second metal 29, an N + substrate 11 and an N-epitaxial layer 12.
The N-epitaxial layer 12 has a first P + implant region 23, a second P + implant region 20 and a first P-well region 21. The first P-well region 21 has a first N + implant region 22 therein (the depth of the first P-well region 21 is greater than the depth of the first N + implant region 22).
The device further comprises: a gate dielectric layer 26 covering the bottom and sidewalls of the first trench 24; a gate 27 located on the gate dielectric layer 26 and filling the first trench 24; a first metal 28, wherein the first metal 28 forms a first ohmic contact on the upper surface of a part of the first N + implantation region 22, the side surface of the first P-well region 21 and the upper surface of the second P + implantation region 20; the back side of the N + substrate 11 also has a second metal 29.
Wherein the first metal 28 forms the source electrode of the MOS device and the second metal 29 forms the drain electrode of the MOS device.
In this embodiment, the N + substrate 11 may be formed by doping with a concentration of 5 × 1018cm-3May have a thickness of 350 μm.
In this embodiment, the doping concentration of the N-epitaxial layer 12 may be 6 × 1015cm-3The thickness may be 10 μm.
In this embodiment, the doping concentration of the first P-well 21 is 6 × 1016cm-3The width was 0.7 μm and the depth was 1 μm.
In this embodiment, the doping concentration of the first N + implantation region 22 is 9 × 1018cm-3The width was 0.7 μm and the depth was 0.5. mu.m.
In the present embodiment, the first trench 24 has a width of 1.2 μm and a depth of 1.5 μm.
In this embodiment, the second trench 25 has a width of 0.7 μm and a depth of 1.8 μm.
In this embodiment, the doping concentration of the first P + implantation region 23 and the second P + implantation region 20 is 1 × 1019cm-3. First, theA P + implantation region 23 having a width of 1.3 μm and a depth of 2 μm; the second P + implant region 20 has a width of 1.2 μm and a depth of 2.3 μm.
In this embodiment, the distance between the left side of the first P + implantation region and the right side of the first trench is 0.6 μm, and the distance between the right side of the second P + implantation region and the left side of the first trench is 0.2 μm
This embodiment also provides a method for fabricating the above-mentioned silicon carbide UMOSFET device, please refer to fig. 2 to fig. 7 in combination, and refer back to fig. 1 for the finally formed structure. The manufacturing method comprises the following steps:
referring to fig. 2, an N-epitaxial layer 12 is formed on an N + substrate 11 by epitaxial growth, and the N + substrate 11 and the N-epitaxial layer 12 on which the N-epitaxial layer 12 is grown are referred to as an epitaxial wafer.
Referring to fig. 3, a first mask layer (not shown) is deposited on the N-epitaxial layer 12, the first mask having a thickness of 2 μm. A first mask pattern is formed by a photolithography etching process. And (3) performing trap implantation on the surface of part of the N-epitaxial layer 12, wherein the implanted ions are Al ions, and forming P + implantation regions 13 and 14.
Referring to fig. 4, the first mask layer is removed, a second mask layer (not shown) is formed on the newly exposed surface of the N-epitaxial layer, and a second mask pattern is formed through a photolithography and etching process; and then, performing trap implantation on the surface of part of the N-epitaxial layer 12 by an N ion implantation means to form a transition N + implantation region 16.
Referring to fig. 5, a well implantation is performed on a portion of the surface of the N-epitaxial layer 12 by an Al ion implantation method to form a P-well region 17.
Referring to fig. 6, a well implantation is performed on a portion of the surface of the N-epitaxial layer 12 by an N ion implantation method to form an N + implantation region 19.
Referring to fig. 7, the second mask layer is removed, a third mask layer (not shown) is formed on the newly exposed surface of the N-epi layer, and a third mask pattern is formed through a photolithography etching process. And etching part of the P-well region 18, the N + injection region 19, the P + injection region 13 and part of the high N-epitaxial layer 12 shown in fig. 6 by using an ICP etching method to form a first trench 24, and etching part of the P-well region 18, the N + injection region 19 and part of the high P + injection region 15 shown in fig. 6 to form a second trench 25. The left side wall of the first trench 24 forms a first P-well region 21 and a first N + injection region 22 at the left side, and the right side wall of the first trench 21 forms a first P + injection region 23 at the right side; the right sidewall of the second trench 25 forms a first P-well region 21 and a first N + implant region 22 on the right, and a second P + implant region 20 is partially surrounded below the second trench 25.
Referring back to fig. 1, a gate dielectric layer 26 is formed on the sidewalls and bottom surface of the first trench 24. Polysilicon is formed to fill the first trench 24 and a gate 27 is formed on the upper surface of the gate dielectric layer 26.
Referring back to fig. 1, the first metal 28 is formed as a source of the device, and the first metal 28 covers a portion of the upper surface of the first N + implantation region 22, the side surface of the first P-well region 21, and the upper surface of the second P + implantation region 20 to form a first ohmic contact. At or after the first metal 28 is formed, a second metal 29 is also formed on the back surface of the N + substrate 11 as a drain electrode.
In the present embodiment, forming a carbon film (not shown) on the surface of the N-epitaxial layer 12 for protection includes performing carbon film on the surface of the N-epitaxial layer 12 using a carbon film sputtering machine. Then, the implanted ions (implanted ions) were activated by high-temperature annealing at 1650 ℃ for 45min, and thereafter, the carbon film was removed by an oxidation method. Thereafter, the carbon film is removed by an oxidation method.
In this embodiment, the process of forming the gate dielectric layer 26 includes performing sacrificial oxidation on the surface of the first trench 24, and depositing silicon dioxide after removing the oxide layer. And then, photoetching and etching are adopted, and after the dielectric window is etched, a source region is formed. And growing a layer of silicon dioxide serving as a gate dielectric layer 26 by adopting a thermal oxidation method, and annealing in the atmosphere of nitric oxide at the annealing temperature of 1200 ℃ for 1 h.
In this embodiment, the process of forming the gate 27 includes depositing a highly doped polysilicon layer by a chemical vapor deposition method, and then forming the gate 27 of polysilicon by photolithography and etching.
In this embodiment, the process of depositing the first metal 28 and forming the first ohmic contact further includes: and (3) carrying out a rapid thermal annealing process under the argon atmosphere, wherein the annealing temperature is 1000 ℃, and the annealing time is 3 min. The first metal 28 is aluminum, forming an electrode pattern.
Not shown, after the first metal 28 is formed, another layer of thick metal, which may be titanium, nickel or silver, etc., may be deposited on the second metal 29, also on the back side of the epitaxial wafer, as part of the back electrode (which is part of the drain electrode).
Referring to fig. 1, an asymmetric silicon carbide UMOSFET device with a shielding region according to the present invention includes:
a second metal 29, the second metal 29 being a drain electrode;
an N + substrate 11, one side of the N + substrate 11 being connected to the second metal 29;
an N-epitaxial layer 12, the other side of the N + substrate 11 is connected to the N-epitaxial layer 12;
a first P + implantation region 23, wherein the first P + implantation region 23 is L-shaped, and the first P + implantation region 23 is connected to the N-epitaxial layer 12;
a second P + implantation region 20, wherein the second P + implantation region 20 is L-shaped, and the second P + implantation region 20 is connected to the N-epitaxial layer 12;
a first P-well region 21, said first P-well region 21 being connected to said second P + implant region 20 and to said N-epitaxial layer 12;
a first N + implantation region 22, the first N + implantation region 22 being connected to the first P-well region 21;
a first trench 24, wherein the first trench 24 is respectively connected to the N-epitaxial layer 12, the first P + implantation region 23, the first P-well region 21 and the first N + implantation region 22;
a second trench 25, wherein the second trench 25 is connected to the second P + implantation region 20, the first P-well region 21 and the first N + implantation region 22 respectively;
a gate dielectric layer 26 covering the side surface of the first trench 24 and the upper surface of the trench bottom;
a gate 27 covering the upper surface of the gate dielectric layer 26 and filling the first trench 24;
a first metal 28, wherein the first metal 28 covers a predetermined position of the upper surface of the first N + implantation region 22, a side surface of the first P-well region 21, and an upper surface of the second P + implantation region 20 to form an ohmic contact.
The distance between the left side of the first P + injection region 23 and the right side of the first trench 24 is 0.5-0.7 μm. If the spacing is too small, the ability of the first P + implant region 23 to shield the gate oxide spike electric field will be diminished; if the pitch is too large, the on-resistance of the entire device increases, causing the device to have large static loss.
The distance between the right side of the second P + implantation region 20 and the left side of the first trench 24 is 0.1 μm to 0.3 μm. If the distance is too small, the current path of the device is reduced, the on-resistance of the device is increased, and the device has larger static loss; if the spacing is too large, the ability of the P + shield layer to mitigate the gate oxide spike electric field will be diminished.
Although specific embodiments of the invention have been described above, it will be understood by those skilled in the art that the specific embodiments described are illustrative only and are not limiting upon the scope of the invention, and that equivalent modifications and variations can be made by those skilled in the art without departing from the spirit of the invention, which is to be limited only by the appended claims.

Claims (10)

1. The utility model provides a take asymmetric carborundum UMOSFET device in shielded area which characterized in that: the second metal is used as a drain electrode;
an N + substrate, one side of the N + substrate is connected to the second metal;
the other side of the N + substrate is connected to the N-epitaxial layer;
the first P + injection region is L-shaped and is connected with the N-epitaxial layer;
the second P + injection region is L-shaped and is connected with the N-epitaxial layer;
a first P-well region connected to the second P + implant region and the N-epitaxial layer;
a first N + implant region connected to the first P-well region;
the first groove is respectively connected with the N-epitaxial layer, the first P + injection region, the first P-well region and the first N + injection region;
the second groove is respectively connected with the second P + injection region, the first P-well region and the first N + injection region;
the gate dielectric layer covers the side surface of the first groove and the upper surface of the groove bottom;
the grid electrode covers the upper surface of the grid dielectric layer and fills the first groove;
and the first metal covers the set position of the upper surface of the first N + injection region, the side surface of the first P-well region and the upper surface of the second P + injection region to form ohmic contact.
2. The asymmetric silicon carbide UMOSFET device with a screening region of claim 1, wherein: the depth of the first groove is 1-3 μm, and the width is 0.5-2 μm; the depth of the second groove is 1-3 μm, and the width is 0.5-2 μm.
3. The asymmetric silicon carbide UMOSFET device with a screening region of claim 1, wherein: the depth of the first P + injection region is 1.5-3 mu m, and the width is 0.8-2 mu m; the depth of the second P + injection region is 2-3 mu m, and the width is 1-2 mu m.
4. The asymmetric silicon carbide UMOSFET device with a screening region of claim 1, wherein: the depth of the first P-well region is 0.3-1.0 μm, and the width is 0.3-1 μm; the depth of the first N + injection region is 0.1-0.5 μm, and the width is 0.3-1 μm.
5. The asymmetric silicon carbide UMOSFET device with a screening region of claim 1, wherein: the depth of the first P + injection region is greater than that of the first groove, and the depth of the second P + injection region is greater than that of the second groove.
6. The asymmetric silicon carbide UMOSFET device with a screening region of claim 1, wherein: the depth of the first trench and the second trench is greater than the depth of the first P-well region.
7. The asymmetric silicon carbide MOSFET device with a screening region of claim 1, wherein: the distance between the left side of the first P + injection region and the right side of the first groove is 0.5-0.7 mu m.
8. The asymmetric silicon carbide UMOSFET device with a screening region of claim 1, wherein: the distance between the right side of the second P + injection region and the left side of the first groove is 0.1-0.3 mu m.
9. A preparation method of an asymmetric silicon carbide UMOSFET device with a shielding region is characterized by comprising the following steps: the method comprises the following steps:
forming an N-epitaxial layer on an N + substrate;
performing P + region injection on the surface of part of the N-epitaxial layer to form a first P + injection region and a second P + injection region;
performing N + region implantation on a set position on the surface of the N-epitaxial layer to form a transition N + implantation region;
performing P-region implantation on the surface of the transition N + implantation region to form a first P-well region;
performing N + region injection on the surface of the P-region to form a first N + injection region;
etching the set positions of the first N + region, the first P-well region, the first P + injection region and the second P + injection region to form a first groove and a second groove;
the left side wall of the first groove is provided with a first P-well region and a first N + injection region;
the P + injection region on the right side wall of the first groove becomes a first P + injection region;
the right side wall of the second groove is provided with a first P-well region and a first N + injection region;
the right P + injection region on the right side wall of the second groove becomes a second P + injection region;
forming a gate dielectric layer to cover the surface of the first groove;
forming a grid electrode on the upper surface of the grid dielectric layer;
forming a first metal covering a portion of the first N + implantation region upper surface, the first N + implantation region side surface, the first P-well region side surface, and the second P + implantation region upper surface to form an ohmic contact;
a drain electrode is formed on the N + substrate.
10. The asymmetric silicon carbide UMOSFET device with a screening region of claim 9, wherein: the ohmic contact forming process comprises the following steps: and carrying out a rapid thermal annealing process under an argon atmosphere.
CN202110174578.9A 2021-02-07 2021-02-07 Asymmetric silicon carbide UMOSFET device with shielding region and preparation method Pending CN112838126A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117525154A (en) * 2024-01-05 2024-02-06 南京第三代半导体技术创新中心有限公司 Double-groove silicon carbide MOSFET device and manufacturing method thereof

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117525154A (en) * 2024-01-05 2024-02-06 南京第三代半导体技术创新中心有限公司 Double-groove silicon carbide MOSFET device and manufacturing method thereof
CN117525154B (en) * 2024-01-05 2024-03-22 南京第三代半导体技术创新中心有限公司 Double-groove silicon carbide MOSFET device and manufacturing method thereof

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