CN115602714A - Groove type IGBT terminal and manufacturing method thereof - Google Patents
Groove type IGBT terminal and manufacturing method thereof Download PDFInfo
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- CN115602714A CN115602714A CN202211382652.7A CN202211382652A CN115602714A CN 115602714 A CN115602714 A CN 115602714A CN 202211382652 A CN202211382652 A CN 202211382652A CN 115602714 A CN115602714 A CN 115602714A
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 11
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 40
- 239000004065 semiconductor Substances 0.000 claims description 32
- 239000000758 substrate Substances 0.000 claims description 31
- 239000002184 metal Substances 0.000 claims description 30
- 235000012239 silicon dioxide Nutrition 0.000 claims description 20
- 239000000377 silicon dioxide Substances 0.000 claims description 20
- 238000005530 etching Methods 0.000 claims description 15
- 238000001259 photo etching Methods 0.000 claims description 12
- 238000000151 deposition Methods 0.000 claims description 11
- 230000004888 barrier function Effects 0.000 claims description 7
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 6
- 238000011065 in-situ storage Methods 0.000 claims description 3
- 238000004220 aggregation Methods 0.000 abstract description 2
- 230000002776 aggregation Effects 0.000 abstract description 2
- 230000005684 electric field Effects 0.000 description 4
- 238000000034 method Methods 0.000 description 3
- 230000008569 process Effects 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 208000015778 Undifferentiated pleomorphic sarcoma Diseases 0.000 description 1
- 238000009825 accumulation Methods 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
- 238000004402 ultra-violet photoelectron spectroscopy Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66234—Bipolar junction transistors [BJT]
- H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
- H01L29/66333—Vertical insulated gate bipolar transistors
- H01L29/66348—Vertical insulated gate bipolar transistors with a recessed gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
- H01L29/7395—Vertical transistors, e.g. vertical IGBT
- H01L29/7396—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions
- H01L29/7397—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
Abstract
The invention discloses a groove type IGBT terminal and a manufacturing method thereof.A field limiting ring groove is arranged between adjacent field limiting rings, between a main junction area and a first field limiting ring, and electron aggregation is introduced near the field limiting ring groove by utilizing a high potential naturally generated when a device is subjected to voltage resistance, so that the transverse depletion of the previous field limiting ring is stopped, the requirement on voltage resistance can be ensured, and the distance between the rings can be effectively shortened, thereby reducing the area of the IGBT terminal.
Description
Technical Field
The invention relates to a groove type IGBT terminal and a manufacturing method thereof, and belongs to the technical field of semiconductor power devices.
Background
The IGBT (insulated gate bipolar transistor) is a composite full-control voltage-driven power semiconductor device formed by combining a BJT (bipolar junction transistor) and an MOSFET (insulated gate field effect transistor), and has high input impedance of the MOSFET and low on-state voltage drop of GTR (gas to liquid ratio). At present, the IGBT has become a mainstream device of power electronic equipment, and has been widely applied in the fields of switching power supplies, rectifiers, inverters, UPSs, and the like.
The IGBT device generally has a higher voltage level in practical application, and a high electric field is brought because the curvature of the surface of a chip junction is limited, so that the IGBT device is usually additionally provided with a circle of terminal design at the periphery of the chip for improving the voltage resistance of the device.
However, the field limiting ring needs to occupy a larger area on the periphery of the chip, and the terminal width required by higher voltage level is wider, so how to reduce the terminal area of the IGBT as much as possible while ensuring the requirement of withstand voltage becomes an important direction for optimizing the IGBT at present.
Disclosure of Invention
The invention provides a groove type IGBT terminal and a manufacturing method thereof, which solve the problems disclosed in the background technology.
In order to solve the technical problems, the technical scheme adopted by the invention is as follows:
a trench type IGBT terminal comprises a semiconductor substrate of a first conduction type, a stop ring trench and a main junction region of a second conduction type, wherein the stop ring trench and the main junction region are arranged on the upper surface of the semiconductor substrate;
a stop ring polycrystalline layer is filled in the stop ring groove, the upper surface of the stop ring polycrystalline layer is connected with a stop ring metal layer, and the stop ring metal layer is also connected with the upper surface of the semiconductor substrate;
the upper surface of the main region is connected with a source electrode metal layer, a plurality of field limiting rings of the second conductive type are arranged on the upper surface of the semiconductor substrate between the main region and the stop ring groove, field limiting ring grooves are formed in the upper surfaces of the semiconductor substrates between adjacent field limiting rings and between the main region and the first field limiting ring, field limiting ring polycrystalline layers are filled in the field limiting ring grooves, the upper surfaces of the field limiting ring polycrystalline layers are connected with field limiting ring metal layers, and the field limiting ring metal layers are further connected with the upper surfaces of the corresponding field limiting rings.
The semiconductor substrate is provided with a medium layer on the upper surface, the medium layer is provided with a plurality of contact holes, and the bottom of the metal layer penetrates through the contact holes to be connected with the connected components.
A gate oxide layer is arranged between the inner side of the field limiting ring groove and the outer side of the field limiting ring polycrystalline layer filled in the field limiting ring groove;
and a gate oxide layer or no gate oxide layer is arranged between the inner side of the stop ring groove and the outer side of the stop ring polycrystalline layer filled in the stop ring groove.
The section of the stop ring polycrystalline layer is in an inverted L shape, the vertical section is filled in the stop ring groove, and the bottom of the horizontal section is attached to the upper surface of the semiconductor substrate;
the section of the field limiting ring polycrystal layer is L-shaped, the vertical section is filled in the field limiting ring groove, and the bottom of the horizontal section is attached to the upper surface of the corresponding field limiting ring.
The depth of the stop ring groove and the field limiting ring groove is 3um to 10um.
A manufacturing method of a trench type IGBT terminal comprises the following steps:
photoetching and injecting the upper surface of a semiconductor substrate of a first conductive type to form a main junction area of a second conductive type and a plurality of field limiting rings on the upper surface of the semiconductor substrate;
growing a silicon dioxide dielectric layer on the semiconductor substrate, and etching off the silicon dioxide dielectric layer in a partial region;
depositing a silicon dioxide barrier layer, etching the silicon dioxide barrier layer in a partial region, opening a groove etching window, and performing deep groove etching to form a field limiting ring groove and a stop ring groove;
growing a silicon dioxide gate oxide layer, carrying out photoetching, reserving the gate oxide layer in the field limiting ring groove, and reserving or removing the gate oxide layer in the stopping ring groove;
depositing polycrystalline silicon, carrying out in-situ N-type doping, and carrying out photoetching to form a field limiting ring polycrystalline layer and a stop ring polycrystalline layer;
depositing a silicon dioxide ILD layer and etching to form a contact hole;
and depositing a metal layer and etching to form a source metal layer, a plurality of field limiting ring metal layers and a stop ring metal layer.
The invention achieves the following beneficial effects: according to the invention, the field limiting ring grooves are arranged between the adjacent field limiting rings, between the main junction area and the first field limiting ring, and by utilizing the naturally generated high potential during the voltage resistance of the device, electron accumulation is introduced near the field limiting ring groove, so that the transverse depletion of the previous field limiting ring is stopped, the voltage resistance requirement is ensured, the distance between the rings is effectively shortened, and the area of the IGBT terminal surface is reduced.
Drawings
Fig. 1 is a schematic cross-sectional view of a trench IGBT terminal.
Detailed Description
The invention is further described below with reference to the accompanying drawings. The following examples are only for illustrating the technical solutions of the present invention more clearly, and the protection scope of the present invention is not limited thereby.
As shown in fig. 1, a trench type IGBT terminal includes a semiconductor substrate 1 of a first conductivity type, and a stop ring trench 3 and a main junction region 2 of a second conductivity type provided on an upper surface of the semiconductor substrate 1; wherein, the main junction 2 and the stop ring groove 3 are respectively positioned at two opposite edges of the chip.
A plurality of field limiting rings 4 of the second conductivity type are arranged on the upper surface of the semiconductor substrate 1 between the main junction 2 and the stop ring groove 3, and field limiting ring grooves 6 are arranged on the upper surface of the semiconductor substrate 1 between adjacent field limiting rings 4 and between the main junction 2 and the first field limiting ring 4; wherein, the depths of the stop ring groove 3 and the field limiting ring groove 6 are 3um to 10um.
A stop ring polycrystalline layer 8 is filled in the stop ring groove 3, a gate oxide layer or no gate oxide layer is arranged between the inner side of the stop ring groove 3 and the outer side of the stop ring polycrystalline layer 8 filled in the stop ring groove 3, the cross section of the stop ring polycrystalline layer 8 is inverted L-shaped, the vertical section is filled in the stop ring groove 3, and the bottom of the horizontal section is attached to the upper surface of the semiconductor substrate 1.
The field limiting ring polycrystalline layer 7 is filled in the field limiting ring groove 6, a gate oxide layer is arranged between the inner side of the field limiting ring groove 6 and the outer side of the field limiting ring polycrystalline layer 7 filled in the field limiting ring groove 6, the cross section of the field limiting ring polycrystalline layer 7 is L-shaped, the vertical section is filled in the field limiting ring groove 6, and the bottom of the horizontal section is attached to the upper surface of the corresponding field limiting ring 4.
The upper surface of the semiconductor substrate 1 is provided with a dielectric layer 5, the dielectric layer covers the main junction 2, the field limiting rings 4, the field limiting ring polycrystalline layer 7 and the stop ring polycrystalline layer 8, and the dielectric layer 5 is provided with a plurality of contact holes 12; the dielectric layer 5 mainly comprises a silicon dioxide barrier layer and a silicon dioxide dielectric layer which are stacked in sequence from top to bottom.
A source electrode metal layer 9 is arranged on the dielectric layer 5 above the main junction 2, and the bottom of the source electrode metal layer 9 is connected with the upper surface of the main junction 2 through a contact hole 12; a stop ring metal layer 11 is arranged on the dielectric layer 5 above the stop ring polycrystalline layer 8, the bottom of the stop ring metal layer 11 is connected with the stop ring polycrystalline layer 8 through a contact hole 12, and is connected with the upper surface of the semiconductor substrate 1 through the contact hole 12; a field limiting ring metal layer 10 is arranged on the dielectric layer 5 above the field limiting ring polycrystalline layer 7, the bottom of the field limiting ring metal layer 10 is connected with the field limiting ring polycrystalline layer 7 through a contact hole 12, and is connected with the upper surface of the corresponding field limiting ring 4 through the contact hole 12
The trench type IGBT terminal is provided with the field limiting ring trenches 6 between the adjacent field limiting rings 4 and between the main junction region 2 and the first field limiting ring 4, and by utilizing high potential naturally generated when the device is in voltage resistance, electron aggregation is introduced near the field limiting ring trenches 6, so that the transverse depletion of the previous field limiting ring 4 is stopped, the requirement of voltage resistance can be ensured, and the distance between the rings can be effectively shortened, so that the area of the IGBT terminal is reduced; and the electric field is cut off by cutting off the annular groove 3, and the groove can be deeply embedded into the substrate body, so that the electric field cutting-off effect is better, and additional N-type local injection or Pbody version is not required.
The manufacturing method of the trench type IGBT terminal comprises the following steps:
1) Photoetching implantation is carried out on the upper surface of the semiconductor substrate 1 of the first conduction type, so that a main junction region 2 of the second conduction type and a plurality of field limiting rings 4 are formed on the upper surface of the semiconductor substrate 1.
2) And growing a silicon dioxide dielectric layer on the semiconductor substrate 1 in a thermal oxidation mode, and photoetching to etch the silicon dioxide dielectric layer in a partial area.
3) And depositing a silicon dioxide barrier layer, photoetching to remove the silicon dioxide barrier layer in a part of area, opening a groove etching window, and performing deep groove etching to form a field limiting ring groove 6 and a stop ring groove 3.
4) And growing a silicon dioxide gate oxide layer in a thermal oxidation mode, carrying out photoetching, reserving the gate oxide layer in the field limiting ring groove 6, and reserving or removing the gate oxide layer in the stop ring groove 3.
5) And depositing polycrystalline silicon, carrying out in-situ N-type doping, and carrying out photoetching to form a field limiting ring polycrystalline layer 7 and a stop ring polycrystalline layer 8.
6) A silicon dioxide ILD layer is deposited over the resulting structure and etched to form contact holes 12.
7) And depositing a metal layer on the formed structure and etching to form a source metal layer 9, a plurality of field limiting ring metal layers 10 and a stop ring metal layer 11.
The groove type IGBT terminal is provided with a stop ring groove 3, a gate oxide layer in a stop ring is removed by photoetching in combination with a conventional polycrystalline silicon deposition process in a groove structure of an active area of a chip, polycrystalline silicon in the stop ring groove 3 is contacted with silicon, n-type impurities in the polycrystalline silicon are diffused and moved in a subsequent annealing process, the n-type impurities are introduced near the stop ring groove 3, and the groove has a depth of 5 mu m, so that the groove has a good stop effect on an electric field at the outermost side, and the voltage resistance and the reliability of the chip are improved.
The terminal process and the whole chip manufacturing process can be well compatible, the manufacturing is simple, the process is stable, and the mass production is easy.
The above description is only a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, it is possible to make various improvements and modifications without departing from the technical principle of the present invention, and those improvements and modifications should be considered as the protection scope of the present invention.
Claims (6)
1. A groove type IGBT terminal is characterized by comprising a semiconductor substrate of a first conduction type, a stop ring groove arranged on the upper surface of the semiconductor substrate and a main junction region of a second conduction type;
a stop ring polycrystalline layer is filled in the stop ring groove, the upper surface of the stop ring polycrystalline layer is connected with a stop ring metal layer, and the stop ring metal layer is also connected with the upper surface of the semiconductor substrate;
the upper surface of the main region is connected with a source electrode metal layer, a plurality of field limiting rings of the second conductive type are arranged on the upper surface of the semiconductor substrate between the main region and the stop ring groove, field limiting ring grooves are formed in the upper surfaces of the semiconductor substrates between adjacent field limiting rings and between the main region and the first field limiting ring, field limiting ring polycrystalline layers are filled in the field limiting ring grooves, the upper surfaces of the field limiting ring polycrystalline layers are connected with field limiting ring metal layers, and the field limiting ring metal layers are further connected with the upper surfaces of the corresponding field limiting rings.
2. The trench type IGBT terminal as claimed in claim 1, wherein a dielectric layer is disposed on the upper surface of the semiconductor substrate, a plurality of contact holes are disposed on the dielectric layer, and the bottom of the metal layer is connected to the connected components through the contact holes.
3. The trench type IGBT terminal according to claim 2, wherein a gate oxide layer is arranged between the inner side of the field limiting ring trench and the outer side of the field limiting ring polycrystalline layer filled in the field limiting ring trench;
and a gate oxide layer or no gate oxide layer is arranged between the inner side of the stop ring groove and the outer side of the stop ring polycrystalline layer filled in the stop ring groove.
4. The trench type IGBT terminal as claimed in claim 3, wherein the cross section of the stop ring poly layer is inverted L-shaped, the vertical section is filled in the stop ring trench, and the bottom of the horizontal section is attached to the upper surface of the semiconductor substrate;
the section of the field limiting ring polycrystal layer is L-shaped, the vertical section is filled in the field limiting ring groove, and the bottom of the horizontal section is attached to the upper surface of the corresponding field limiting ring.
5. The trench type IGBT terminal as claimed in claim 1, 3 or 4, wherein the depths of the stop ring trench and the field limiting ring trench are from 3um to 10um.
6. A manufacturing method of a trench type IGBT terminal, characterized in that the trench type IGBT terminal is the terminal of any one of claims 3 to 5, and comprises the following steps:
photoetching and injecting the upper surface of a semiconductor substrate of a first conductive type to form a main junction area of a second conductive type and a plurality of field limiting rings on the upper surface of the semiconductor substrate;
growing a silicon dioxide dielectric layer on the semiconductor substrate, and etching off the silicon dioxide dielectric layer in a partial region;
depositing a silicon dioxide barrier layer, etching the silicon dioxide barrier layer in a partial region, opening a groove etching window, and performing deep groove etching to form a field limiting ring groove and a stop ring groove;
growing a silicon dioxide gate oxide layer, carrying out photoetching, reserving the gate oxide layer in the field limiting ring groove, and reserving or removing the gate oxide layer in the stop ring groove;
depositing polycrystalline silicon, carrying out in-situ N-type doping, and carrying out photoetching to form a field limiting ring polycrystalline layer and a stop ring polycrystalline layer;
depositing a silicon dioxide ILD layer and etching to form a contact hole;
and depositing a metal layer and etching to form a source metal layer, a plurality of field limiting ring metal layers and a stop ring metal layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202211382652.7A CN115602714A (en) | 2022-11-07 | 2022-11-07 | Groove type IGBT terminal and manufacturing method thereof |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202211382652.7A CN115602714A (en) | 2022-11-07 | 2022-11-07 | Groove type IGBT terminal and manufacturing method thereof |
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| CN115602714A true CN115602714A (en) | 2023-01-13 |
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| CN202211382652.7A Pending CN115602714A (en) | 2022-11-07 | 2022-11-07 | Groove type IGBT terminal and manufacturing method thereof |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116741821A (en) * | 2023-08-09 | 2023-09-12 | 深圳腾睿微电子科技有限公司 | IGBT device structure and corresponding manufacturing method |
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- 2022-11-07 CN CN202211382652.7A patent/CN115602714A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116741821A (en) * | 2023-08-09 | 2023-09-12 | 深圳腾睿微电子科技有限公司 | IGBT device structure and corresponding manufacturing method |
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