CN116314302A - Manufacturing method of groove type silicon carbide MOSFET device - Google Patents
Manufacturing method of groove type silicon carbide MOSFET device Download PDFInfo
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- CN116314302A CN116314302A CN202310086952.9A CN202310086952A CN116314302A CN 116314302 A CN116314302 A CN 116314302A CN 202310086952 A CN202310086952 A CN 202310086952A CN 116314302 A CN116314302 A CN 116314302A
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- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 title claims abstract description 37
- 229910010271 silicon carbide Inorganic materials 0.000 title claims abstract description 37
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 13
- 239000002184 metal Substances 0.000 claims abstract description 53
- 230000004888 barrier function Effects 0.000 claims abstract description 40
- 238000000151 deposition Methods 0.000 claims abstract description 23
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 22
- 238000005530 etching Methods 0.000 claims abstract description 17
- 229920005591 polysilicon Polymers 0.000 claims abstract description 17
- 239000000758 substrate Substances 0.000 claims abstract description 17
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 16
- 238000005468 ion implantation Methods 0.000 claims abstract description 10
- 238000002955 isolation Methods 0.000 claims abstract description 10
- 238000001259 photo etching Methods 0.000 claims abstract description 8
- 238000000034 method Methods 0.000 claims abstract description 6
- 238000000137 annealing Methods 0.000 claims abstract description 4
- 230000001590 oxidative effect Effects 0.000 claims abstract description 4
- 238000001465 metallisation Methods 0.000 claims description 3
- 230000015556 catabolic process Effects 0.000 abstract description 10
- 238000006731 degradation reaction Methods 0.000 abstract description 10
- 230000000694 effects Effects 0.000 abstract description 7
- 239000000463 material Substances 0.000 description 5
- 230000005684 electric field Effects 0.000 description 4
- 230000000903 blocking effect Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000000407 epitaxy Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66053—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide
- H01L29/66068—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7839—Field effect transistors with field effect produced by an insulated gate with Schottky drain or source contact
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
- Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
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- General Physics & Mathematics (AREA)
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Abstract
The invention provides a manufacturing method of a groove type silicon carbide MOSFET device, which comprises the following steps: forming an epitaxial layer on a silicon carbide substrate, depositing a barrier layer on the epitaxial layer, etching, and performing ion implantation to form a lightly doped region, a source region and a heavily doped region; etching the epitaxial layer to form a gate region, oxidizing the gate region and forming a gate oxide layer; photoetching to form a photoresist mask of a set area, removing a gate oxide layer of the area uncovered by the photoresist by a wet method, depositing to form Schottky contact metal, and stripping to obtain a Schottky contact interface; annealing to form a Schottky contact metal layer; depositing a dielectric layer, photoetching a photoresist mask in a set area, removing the dielectric layer in the area which is not covered by the photoresist, and forming an isolation dielectric layer; respectively depositing a polysilicon layer, a source electrode metal layer, a drain electrode metal layer and a grid electrode metal layer; degradation of device performance due to bipolar degradation effect can be prevented.
Description
Technical Field
The invention relates to a manufacturing method of a groove type silicon carbide MOSFET device.
Background
Silicon carbide (SiC) material is one of the representatives of the third generation semiconductor materials, and has excellent characteristics such as large forbidden bandwidth, high critical electric field, high carrier saturation rate, and the like. Compared with Si devices, the silicon carbide MOSFET has the advantages of high switching speed, high reverse blocking voltage and the like. Compared with a planar MOSFET, the trench MOSFET developed in recent years has the advantages that the conducting channel is changed from the transverse direction to the vertical direction, the cell size is effectively reduced, the JFET effect is eliminated, and the on-resistance of the device is reduced.
The body diode in the silicon carbide MOSFET has the third quadrant conduction capability, and the excellent body diode reverse freewheeling capability can prevent the current from suddenly changing to generate an excessively high voltage peak when the MOSFET is used as a switching device. In the prior art, a reverse freewheeling diode is often connected in parallel outside, but this is disadvantageous for high frequency and brings about an area cost problem.
Because the silicon carbide material has a larger forbidden bandwidth, and the turn-on voltage of the body diode is higher (about 3V), the problem of higher reverse freewheeling power consumption can be caused when the self-body PN junction diode is used for reverse freewheeling. In addition, stacking fault defects in the SiC epitaxial material which are not solved at present can generate bipolar degradation effect when a body diode is bipolar in operation, so that the performance of the trench type silicon carbide MOSFET device is degraded; therefore, new structural designs for trench silicon carbide MOSFETs are necessary.
Disclosure of Invention
The invention aims to solve the technical problem of providing a manufacturing method of a groove type silicon carbide MOSFET device, which can be used for preferentially conducting a Schottky diode at the bottom of a groove when the device is conducted reversely, so that the opening of a body diode is inhibited, and the performance degradation of the device caused by a bipolar degradation effect is prevented.
The invention is realized in the following way: the manufacturing method of the groove type silicon carbide MOSFET device specifically comprises the following steps:
and 11, removing all the barrier layers, and depositing a drain metal layer on the silicon carbide substrate.
The invention has the advantages that: according to the manufacturing method of the groove type silicon carbide MOSFET device, the Schottky contact metal layer is introduced into the bottom of the groove, so that the Schottky diode at the bottom of the groove can be conducted preferentially when the device is conducted reversely, the opening of the body diode is restrained, and the performance degradation of the device caused by bipolar degradation effect is prevented. The lightly doped region surrounds the structure of the bottom corner of the gate oxide layer, so that the high electric field at the corner of the gate oxide layer can be effectively restrained while the Schottky interface is protected, and the reliability of the device is improved.
Drawings
The invention will be further described with reference to examples of embodiments with reference to the accompanying drawings.
Fig. 1 is a flow chart of a method of fabricating a trench silicon carbide MOSFET device in accordance with the present invention.
Fig. 2 is a schematic diagram of a trench silicon carbide MOSFET device according to the present invention.
Fig. 3 is a schematic diagram of a trench silicon carbide MOSFET device according to the present invention.
1-epitaxial layer, 2-silicon carbide substrate, 3-drain metal layer, 4-source region, 5-heavily doped region, 6-lightly doped region, 7-gate oxide layer, 8-doped polysilicon layer, 9-Schottky contact metal layer, 10-isolation dielectric layer, 11-gate dielectric layer, 12-source metal layer, and 13-gate metal layer.
Detailed Description
Referring to fig. 1 to 3, the method for manufacturing a trench silicon carbide MOSFET device according to the present invention specifically includes the following steps:
and 11, removing all the barrier layers, and depositing a drain metal layer 3 on the silicon carbide substrate.
The epitaxial layer 1, the silicon carbide substrate 2, the source region 4 and the polysilicon layer 8 are all of a first conductivity type; the lightly doped region 6 and the heavily doped region 5 are both of the second conductivity type.
As shown in fig. 2 and 3, the device obtained by the manufacturing method of the present invention includes:
a silicon carbide substrate 2;
the epitaxial layer 1 is arranged on one side surface of the silicon carbide substrate 2, a lightly doped region 6 is arranged on the epitaxial layer 1, a source region 4 and a heavily doped region 5 are arranged on the lightly doped region 6, and the source region 4 is connected with the heavily doped region 5;
the bottom of the U-shaped gate oxide layer 7 is respectively connected with the epitaxial layer 1 and the lightly doped region 6, and the side wall of the U-shaped gate oxide layer 7 is respectively connected with the lightly doped region 6 and the source region 4; the bottom of the U-shaped gate oxide layer 7 is provided with a through hole;
a schottky contact metal layer 9, wherein the schottky contact metal layer 9 is disposed on the through hole, and the lower side surface of the schottky contact metal layer 9 is connected to the epitaxial layer 1;
the isolation medium layer 10 is arranged in the U-shaped gate oxide layer 7, and the lower side surface of the isolation medium layer 10 is connected with the upper side surface of the Schottky contact metal layer 9;
the polysilicon layer 8 is arranged on the U-shaped gate oxide layer 7, and the lower side surface of the polysilicon layer 8 is connected to the upper side surface of the isolation medium layer 10;
a source metal layer 12, wherein the source metal layer 12 is respectively connected with the source region 4, the heavily doped region 5, the lightly doped region 6 and the epitaxial layer 1;
the gate dielectric layer 11 is respectively connected with the polysilicon layer 8 and the U-shaped gate oxide layer 7, the gate dielectric layer 11 covers the polysilicon layer, the source metal layer 12 covers the gate dielectric layer 11, and the gate dielectric layer 11 covers part of the polysilicon layer 8 and the source region 4;
a gate metal layer 13, the gate metal layer 13 being connected to the polysilicon layer 8;
and, with the drain metal layer 3, the drain metal layer 3 is connected to the other side face of the silicon carbide substrate 2.
The epitaxial layer 1, the silicon carbide substrate 2, the source region 4 and the polysilicon layer 8 are all of a first conductivity type; the lightly doped region 6 and the heavily doped region 5 are both of the second conductivity type.
A first conductive type epitaxial layer 1, a first conductive type silicon carbide substrate 2 under the first conductive type epitaxial layer 1, and a drain metal 3 contacting a lower surface of the first conductive type silicon carbide substrate 2;
a second conductive type lightly doped region 6, a first conductive type source region 4 and a second conductive type heavily doped region 5 on the surface of the first conductive type epitaxial layer 1, wherein the first conductive type source region 4 and the second conductive type heavily doped region 5 are adjacent and contained by the second conductive type lightly doped region 6;
the trench structure comprises a gate oxide layer 7 covered on the side wall of the trench, a Schottky contact metal layer 9 positioned at the bottom of the trench, an isolation medium layer 10 positioned above and in contact with the Schottky contact metal layer 9, and a first conductive type doped polysilicon layer 8 filled in the trench and in contact with the gate oxide layer 7 and the isolation medium layer 10;
wherein the first conductive type source region 4 is positioned at two sides of the groove structure and is contacted with the outer wall of the gate oxide layer 7, and the lower edge depth of the second conductive type lightly doped region 6 is larger than the bottom depth of the groove and surrounds the corner at the bottom of the gate oxide layer 7;
the lower surface of the Schottky contact metal layer 9 is contacted with the first conductive type epitaxial layer 1 to form a Schottky contact interface, and the upper surface is in short circuit with the source metal 12 through a through hole; a gate dielectric layer 11 over the trench structure and source metal 12 over the first conductivity type source region 4 and the second conductivity type heavily doped region 5.
The first conductive type is N type, the second conductive type is P type, and the substrate and the epitaxy are made of silicon carbide materials. The working principle of the device is as follows: when the device is turned on in the forward direction, the N-type polysilicon layer 8 and the drain electrode 3 are connected to a high potential, and the source electrode 12 is grounded. The channel region on the side surface of the P-type lightly doped region 6 is in inversion, a channel is formed, and the device is conducted in the forward direction. Because the schottky contact metal layer 9 is in short circuit with the source electrode 12, the potential of the drain electrode 3 is higher than the voltage of the Yu Xiaote schottky contact metal layer 9, so that the schottky diode at the bottom of the groove is reversely biased and cannot be conducted.
When the device is blocked in reverse, the N-type polysilicon layer 8 and the source electrode 12 are grounded, and the drain electrode 3 is connected to a high potential. At this time, the potential of the schottky contact metal layer 9 is low due to the ground, and the schottky barrier is reversely biased, so that electric leakage is not caused by conduction. In addition, due to the design that the P-type lightly doped region 6 surrounds the corner of the gate oxide layer 7, the formation of high electric field intensity at the Schottky interface can be effectively inhibited during reverse blocking, and the Schottky interface and the gate oxide layer are protected.
When the device is turned on reversely, the N-type polysilicon layer 8 and the drain electrode 3 are grounded, and the source electrode 12 is connected to a high potential. The schottky contact metal layer 9 has a higher potential than the drain electrode 3 at this time, and has a lower schottky barrier and a lower turn-on voltage than the PN junction formed by the P-type lightly doped region 6 and the N-type epitaxial layer. Therefore, when the schottky diode is reversely conducted, the schottky diode at the bottom of the channel is preferentially conducted, the conduction of the body diode formed by the P-type lightly doped region 6 and the N-type epitaxial layer is restrained, and the bipolar degradation effect is prevented.
The beneficial effects are as follows: because the Schottky contact metal layer 9 is introduced at the bottom of the channel, the Schottky diode at the bottom of the channel can be conducted preferentially when the device is conducted reversely, the opening of the body diode is restrained, and the performance degradation of the device caused by the bipolar degradation effect is prevented. The lightly doped region 6 of the second conductivity type surrounds the bottom corner structure of the gate oxide layer 7, so that the high electric field at the corner of the gate oxide layer 7 can be effectively restrained while the Schottky interface is protected, and the reliability of the device is improved.
While specific embodiments of the invention have been described above, it will be appreciated by those skilled in the art that the specific embodiments described are illustrative only and not intended to limit the scope of the invention, and that equivalent modifications and variations of the invention in light of the spirit of the invention will be covered by the claims of the present invention.
Claims (3)
1. The manufacturing method of the groove type silicon carbide MOSFET device is characterized by comprising the following steps:
step 1, forming an epitaxial layer on a silicon carbide substrate, depositing a barrier layer on the epitaxial layer, etching the barrier layer to form a through hole, and performing ion implantation through the through hole to form a lightly doped region;
step 2, redeposit the barrier layer, etch the barrier layer to form the through hole, carry on the ion implantation through the through hole, form the source region;
step 3, redeposit the barrier layer, etch the barrier layer to form the through hole, carry on the ion implantation through the through hole, form the heavily doped region;
step 4, etching the epitaxial layer to form a gate region, oxidizing the gate region and forming a gate oxide layer;
step 5, photoetching to form a photoresist mask of a set area, removing a gate oxide layer of the area uncovered by the photoresist by a wet method, depositing to form Schottky contact metal, and stripping to obtain a Schottky contact interface;
step 6, annealing to form a Schottky contact metal layer, and removing the mask;
step 7, depositing a formed dielectric layer, photoetching a photoresist mask for forming a set area, and removing the dielectric layer of the area which is not covered by the photoresist to form an isolation dielectric layer;
step 8, depositing and etching polycrystalline silicon to form a polycrystalline silicon layer; depositing a dielectric layer and etching to form a gate dielectric layer;
step 9, redeposit the barrier layer, etch the barrier layer and form the metal through hole of source region, deposit the source region through the metal through hole of source region, form the metal layer of source;
step 10, redeposit the barrier layer, etch the barrier layer and form the metal deposition area of grid, deposit and form the metal layer of grid;
and 11, removing all the barrier layers, and depositing a drain metal layer on the silicon carbide substrate.
2. The method for manufacturing a trench silicon carbide MOSFET device according to claim 1, wherein said step 8 is further specifically: redeposit the barrier layer, etch the barrier layer to form the via hole, deposit and form the polycrystalline silicon layer through the via hole; and redeposition the barrier layer, etching the barrier layer to form a through hole, and depositing the through hole to form a gate dielectric layer.
3. The method of fabricating a trench silicon carbide MOSFET device of claim 1, wherein said epitaxial layer, silicon carbide substrate, source region, and polysilicon layer are of a first conductivity type; the lightly doped region and the heavily doped region are both of the second conductivity type.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202310086952.9A CN116314302A (en) | 2023-02-09 | 2023-02-09 | Manufacturing method of groove type silicon carbide MOSFET device |
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| CN202310086952.9A CN116314302A (en) | 2023-02-09 | 2023-02-09 | Manufacturing method of groove type silicon carbide MOSFET device |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117238968A (en) * | 2023-11-10 | 2023-12-15 | 安建科技(深圳)有限公司 | Trench gate silicon carbide MOSFET device and preparation method thereof |
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- 2023-02-09 CN CN202310086952.9A patent/CN116314302A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117238968A (en) * | 2023-11-10 | 2023-12-15 | 安建科技(深圳)有限公司 | Trench gate silicon carbide MOSFET device and preparation method thereof |
| CN117238968B (en) * | 2023-11-10 | 2024-03-15 | 安建科技(深圳)有限公司 | Trench gate silicon carbide MOSFET device and preparation method thereof |
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