CN116825780B - Semiconductor device and method for manufacturing the same - Google Patents

Semiconductor device and method for manufacturing the same Download PDF

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Publication number
CN116825780B
CN116825780B CN202311107760.8A CN202311107760A CN116825780B CN 116825780 B CN116825780 B CN 116825780B CN 202311107760 A CN202311107760 A CN 202311107760A CN 116825780 B CN116825780 B CN 116825780B
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field effect
effect transistor
layer
groove
semiconductor device
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CN116825780A (en
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任真伟
王晓
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Chongqing Pingchuang Semiconductor Research Institute Co ltd
Shenzhen Pingchuang Semiconductor Co ltd
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Chongqing Pingchuang Semiconductor Research Institute Co ltd
Shenzhen Pingchuang Semiconductor Co ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0266—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using field effect transistors as protective elements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/8213—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using SiC technology
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/07—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common
    • H01L27/0705—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common comprising components of the field effect type

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

The invention provides a semiconductor device and a manufacturing method thereof, wherein a junction field effect transistor and a metal oxide field effect transistor which are arranged in parallel and share a source electrode groove structure are integrated on the same semiconductor device, the junction field effect transistor and the metal oxide field effect transistor can be synchronously controlled in a switching manner, the channel closing capability of the junction field effect transistor is weaker than that of the metal oxide field effect transistor, when the junction field effect transistor and the metal oxide field effect transistor are synchronously closed, surge current preferentially passes through a conductive channel of the junction field effect transistor, the problem of current leakage of the metal oxide field effect transistor in a reverse surge state is solved, the avalanche heating phenomenon and avalanche dislocation phenomenon of the metal oxide field effect transistor caused by the reverse surge current can be avoided, the anti-surge capability is improved, and the reliability is improved; meanwhile, the corresponding manufacturing method is compatible with the manufacturing process of the groove type metal oxide field effect transistor, and the manufacturing method is simple in process flow and low in cost.

Description

Semiconductor device and method for manufacturing the same
Technical Field
The invention relates to the technical field of semiconductors, in particular to a semiconductor device and a manufacturing method thereof.
Background
Silicon carbide material is used as a wide forbidden band semiconductor material, has more excellent characteristics than silicon material, and has a forbidden band width of 3 times that of silicon, a critical breakdown electric field of 10 times that of silicon and a thermal conductivity of 4 times that of silicon. The power device made of the silicon carbide material has higher working frequency, smaller loss and higher working temperature and power density than the silicon device, and is suitable for being applied to power electronic devices with high voltage, high power, high temperature and radiation resistance.
In recent years, silicon carbide metal oxide field effect transistors (SiC MOSFETs) have been pushed to the power device market. Under the same voltage withstand capability, siC MOSFETs have higher operating temperatures, lower switching losses, and higher switching frequencies than conventional silicon-on-insulator bipolar field effect transistors (Si IGBTs). Although the performance of the SiC MOSFET is excellent, the SiC MOSFET device can enter an avalanche state under reverse surge current, the heat productivity at an avalanche site is large, the condition of material internal ablation is easy to generate, and the reliability of the device is seriously affected. Meanwhile, avalanche sites tend to cause an increase in dislocations inside the material, degrading the MOSFET body diode performance.
Therefore, improving the anti-surge capability and reliability of the SiC MOSFET is a technical problem which needs to be solved at present.
Disclosure of Invention
In view of the above-mentioned drawbacks of the prior art, the present invention aims to provide a technical solution for a semiconductor device, in which a junction field effect transistor and a metal oxide field effect transistor which are arranged in parallel and share a source trench structure are integrated on the semiconductor device, so that synchronous switching control can be performed on the junction field effect transistor and the metal oxide field effect transistor on the semiconductor device, and when the semiconductor device is turned off, the channel closing capability of the junction field effect transistor is weaker than that of the metal oxide field effect transistor, so that under a reverse surge condition, surge current preferentially passes through the channel of the junction field effect transistor, thereby realizing good protection on the metal oxide field effect transistor, solving the problem of current leakage under the reverse surge condition, improving the anti-surge capability of the device, and improving the reliability of the device.
In order to achieve the above object and other related objects, the present invention provides the following technical solutions.
A semiconductor device on which a junction field effect transistor and a metal oxide field effect transistor arranged in parallel are integrated, the junction field effect transistor and the metal oxide field effect transistor sharing a source trench structure, the semiconductor device comprising:
A substrate of a first doping type having oppositely disposed front and back surfaces;
a buffer layer of a first doping type disposed on the front surface of the substrate;
the epitaxial layer with the first doping type is arranged on the buffer layer, a base region with the second doping type and a plurality of first doping regions with the first doping type are arranged in a region far away from the buffer layer, the first doping regions are sequentially and dispersedly arranged along a first direction, one first doping region is positioned in the base region, and the rest of first doping regions are partially overlapped with the base region;
the first grid electrode groove structure is arranged in the epitaxial layer and sequentially penetrates through the first doping region and the base region in the base region along a second direction;
the second grid electrode groove structure is arranged in the epitaxial layer and located outside the base region, and penetrates through the first doping region which is partially overlapped with the base region along the second direction;
the source electrode groove structure is arranged in the epitaxial layer, penetrates through the base region along the second direction and extends to one side, close to the buffer layer, of the epitaxial layer;
wherein the first direction and the second direction are perpendicular to each other.
Optionally, two junction field effect transistors and one metal oxide field effect transistor are integrated on the semiconductor device, the metal oxide field effect transistor includes a double-trench metal oxide field effect transistor, the semiconductor device includes three first doped regions, two second gate trench structures and two source trench structures, and the first second gate trench structures, the first source trench structures, the first gate trench structures, the second source trench structures and the second source trench structures are sequentially and dispersedly arranged along the first direction.
Optionally, the junction field effect transistor and the metal oxide field effect transistor are integrated on the semiconductor device, the metal oxide field effect transistor includes a double-trench metal oxide field effect transistor, the semiconductor device includes two first doped regions, one second gate trench structure and two source trench structures, and the second gate trench structure, the first source trench structure, the first gate trench structure and the second source trench structure are sequentially and dispersedly arranged along the first direction.
Optionally, the junction field effect transistor and the metal oxide field effect transistor are integrated on the semiconductor device, the metal oxide field effect transistor includes a single trench type metal oxide field effect transistor, the semiconductor device includes two first doped regions, one second gate trench structure and one source trench structure, and the second gate trench structure, the source trench structure and the first gate trench structure are sequentially and dispersedly arranged along the first direction.
Optionally, the semiconductor device further includes:
the insulating medium layer is arranged on the epitaxial layer and covers the first grid electrode groove structure and the second grid electrode groove structure;
the source electrode ohmic contact layer is arranged on the epitaxial layer and contacts with and covers the source electrode groove structure;
a source metal layer covering the insulating dielectric layer and the source ohmic contact layer;
a drain ohmic contact layer disposed on a back surface of the substrate;
and the drain electrode metal layer covers the drain electrode ohmic contact layer.
Optionally, the first doping type is doped with a conductivity type opposite to the second doping type.
A method for manufacturing a semiconductor device includes the steps of:
providing a substrate, wherein the substrate is provided with a front surface and a back surface which are oppositely arranged, a buffer layer is formed on the front surface of the substrate, an epitaxial layer is formed on the buffer layer, and the substrate, the buffer layer and the epitaxial layer are all of a first doping type;
performing ion implantation on the epitaxial layer, forming a base region of a second doping type and a plurality of first doping regions of a first doping type in a region of the epitaxial layer far away from the buffer layer, wherein the first doping regions are sequentially and dispersedly arranged along a first direction, one first doping region is positioned in the base region, and the rest first doping regions are partially overlapped with the base region;
etching to form a first groove, a second groove and a third groove, wherein the first groove sequentially penetrates through the first doping region and the base region which are positioned in the base region along a second direction, the second groove penetrates through the first doping region which partially overlaps with the base region along the second direction, and the third groove penetrates through the base region along the second direction and extends to one side of the epitaxial layer close to the buffer layer;
forming a first gate trench structure along the first trench, forming a second gate trench structure along the second trench, and forming a source trench structure along the third trench;
Forming an insulating medium layer and a source electrode ohmic contact layer on the epitaxial layer, and forming a source electrode metal layer, wherein the insulating medium layer covers the first grid electrode groove structure and the second grid electrode groove structure, the source electrode ohmic contact layer contacts with and covers the source electrode groove structure, and the source electrode metal layer covers the insulating medium layer and the source electrode ohmic contact layer;
forming a drain ohmic contact layer and a drain metal layer on the back surface of the substrate, wherein the drain ohmic contact layer is positioned on the back surface of the substrate, and the drain metal layer covers the drain ohmic contact layer;
wherein the first direction is perpendicular to the second direction.
Optionally, the step of performing ion implantation on the epitaxial layer to form a base region of a second doping type and a plurality of first doping regions of a first doping type in a region of the epitaxial layer away from the buffer layer, includes:
performing ion implantation of the second doping type on the epitaxial layer, and forming the base region in a region of the epitaxial layer away from the buffer layer;
and carrying out ion implantation of the first doping type on the epitaxial layer, and forming a plurality of mutually independent first doping regions in the region of the epitaxial layer far away from the buffer layer, wherein the doping depth of the first doping regions along the second direction is smaller than that of the base regions along the second direction, and the size of the first doping regions along the first direction is smaller than that of the base regions along the first direction.
Optionally, the step of etching to form the first trench, the second trench and the third trench includes:
performing first etching on the epitaxial layer to form the third groove;
performing second etching on the epitaxial layer to synchronously form the first groove and the second groove;
the depth of the first groove is the same as that of the second groove, and the depth of the third groove is larger than that of the first groove.
Optionally, forming a first gate trench structure along the first trench, forming a second gate trench structure along the second trench, and forming a source trench structure along the third trench, including:
performing ion implantation of the second doping type along the second groove and the third groove and annealing, and forming a second doping region wrapping the second groove or the third groove in the epitaxial layer;
performing thermal oxidation along the first groove, the second groove and the third groove to form a groove insulating layer, and removing the groove insulating layer in the second groove and the groove insulating layer in the third groove;
and filling and forming conductive medium layers in the first groove, the second groove and the third groove respectively through deposition and surface planarization treatment.
As described above, the semiconductor device and the manufacturing method thereof provided by the invention have at least the following beneficial effects:
1) The junction field effect transistor and the metal oxide field effect transistor which are arranged in parallel are integrated on the semiconductor device, and the junction field effect transistor and the metal oxide field effect transistor share a source electrode groove structure, so that synchronous switching control can be carried out on the junction field effect transistor and the metal oxide field effect transistor on the semiconductor device, meanwhile, the channel closing capacity of the junction field effect transistor is weaker than that of the metal oxide field effect transistor, and under the reverse surge condition, surge current preferentially passes through the channel of the junction field effect transistor, so that the metal oxide field effect transistor is well protected, the current leakage problem under the reverse surge condition is solved, the anti-surge capacity of the device is improved, and the reliability of the device is improved;
2) The corresponding manufacturing method is compatible with the manufacturing process of the mainstream trench type metal oxide field effect transistor at present, has simple process flow and low cost, and is suitable for mass production.
Drawings
Fig. 1 is a schematic structural diagram of a semiconductor device according to a first embodiment of the invention.
Fig. 2 is a schematic view showing an inrush current bleeding path of the semiconductor device in fig. 1.
Fig. 3 is a schematic diagram showing steps of a method for fabricating a semiconductor device according to a first embodiment of the present invention.
Fig. 4-14 are process flow diagrams illustrating a method of fabricating a semiconductor device according to a first embodiment of the invention.
Fig. 15 is a schematic structural diagram of a semiconductor device according to a second embodiment of the present invention.
Fig. 16 is a schematic view showing an inrush current bleeding path of the semiconductor device in fig. 15.
Fig. 17 is a schematic view showing a structure of a semiconductor device in a third embodiment of the present invention.
Fig. 18 is a schematic view showing an inrush current bleeding path of the semiconductor device in fig. 17.
Description of the reference numerals
1-substrate, 2-buffer layer, 3-epitaxial layer, 4-base region, 5-first doped region, 6-first gate trench structure, 60-gate insulation layer, 61-conductive medium layer, 7-second gate trench structure, 70-second doped region, 71-conductive medium layer, 8-source trench structure, 80-second doped region, 81-conductive medium layer, 9-insulating medium layer, 10-source ohmic contact layer, 11-source metal layer, 12-drain ohmic contact layer, 13-drain metal layer, T1-first trench, T2-second trench, T3-third trench.
Detailed Description
Other advantages and effects of the present invention will become apparent to those skilled in the art from the following disclosure, which describes the embodiments of the present invention with reference to specific examples. The invention may be practiced or carried out in other embodiments that depart from the specific details, and the details of the present description may be modified or varied from the spirit and scope of the present invention.
Please refer to fig. 1 to 18. It should be noted that, the illustrations provided in the present embodiment merely illustrate the basic concept of the present invention by way of illustration, and only the components related to the present invention are shown in the illustration, rather than being drawn according to the number, shape and size of the components in actual implementation, and the form, number and proportion of each component in actual implementation may be arbitrarily changed, and the layout of the components may be more complex. The structures, proportions, sizes, etc. shown in the drawings are shown only in connection with the present disclosure for the purpose of understanding and reading by those skilled in the art, and are not intended to limit the scope of the invention, so that any structural modifications, proportional changes, or dimensional adjustments should not be construed as essential to the invention, but should still fall within the scope of the invention as defined by the appended claims without affecting the efficacy or achievement of the invention.
As described in the foregoing background, the inventors have studied to find: although the silicon carbide metal oxide field effect transistor has excellent performance, the silicon carbide metal oxide field effect transistor can enter an avalanche state under reverse surge current, the heat productivity at an avalanche site is large, the condition of material internal ablation is easy to generate, and the reliability of the device is seriously affected; meanwhile, the avalanche site easily causes the dislocation in the material to increase, so that the performance of the body diode in the silicon carbide metal oxide field effect transistor is degraded.
Based on the above, the invention provides a technical scheme for improving the surge resistance of the metal oxide field effect transistor: the junction field effect transistor and the metal oxide field effect transistor which are arranged in parallel and share the source electrode groove structure are integrated on the same semiconductor chip, so that the junction field effect transistor is connected with a conductive channel of the metal oxide field effect transistor, synchronous switching control can be carried out on the junction field effect transistor and the metal oxide field effect transistor, and then the principle that the channel closing capacity of the junction field effect transistor is weaker than that of the metal oxide field effect transistor is utilized, when the junction field effect transistor and the metal oxide field effect transistor are synchronously closed, surge current under a reverse surge condition preferentially passes through the conductive channel of the junction field effect transistor, and the surge current under the reverse surge state hardly flows through the metal oxide field effect transistor, so that the avalanche heating phenomenon and avalanche dislocation phenomenon of the metal oxide field effect transistor caused by the reverse surge current are avoided, the anti-surge capacity of the device is improved, and the reliability of the device is improved.
Example 1
As shown in fig. 1, an embodiment of the present invention provides a semiconductor device, on which a junction field effect transistor and a metal oxide field effect transistor are integrated and arranged in parallel, the junction field effect transistor and the metal oxide field effect transistor share a source trench structure, the semiconductor device includes:
A substrate 1 of a first doping type having oppositely disposed front and back surfaces;
a buffer layer 2 of a first doping type disposed on the front surface of the substrate 1;
an epitaxial layer 3 of a first doping type, which is disposed on the buffer layer 2, and a region far away from the buffer layer 2 is provided with a base region 4 of a second doping type and a plurality of first doping regions 5 of the first doping type, wherein the plurality of first doping regions 5 are sequentially and dispersedly disposed along a first direction (i.e., the positive direction of the X axis in FIG. 1), one first doping region 5 is disposed in the base region 4, and the rest of first doping regions 5 partially overlap with the base region 4;
the first gate trench structure 6 is disposed in the epitaxial layer 3, and sequentially penetrates through the first doped region 5 and the base region 4 in the base region 4 along the second direction (i.e., the negative Z-axis direction in fig. 1);
a second gate trench structure 7 disposed in the epitaxial layer 3 and located outside the base region 4, penetrating the first doped region 5 partially overlapping the base region 4 along the second direction;
a source trench structure 8 disposed in the epitaxial layer 3, penetrating the base region 4 along the second direction and extending to a side of the epitaxial layer 3 close to the buffer layer 2;
wherein the first direction and the second direction are perpendicular to each other.
It should be noted that, the substrate 1 is heavily doped, the buffer layer 2 is middle doped, the epitaxial layer 3 is lightly doped, the base region 4 is middle doped, the first doped region 5 is heavily doped, and the second doped region 70 and the second doped region 80 are both heavily doped; the substrate 1, the buffer layer 2 and the epitaxial layer 3 are all made of silicon carbide, the substrate 1 is mainly used as a drain region of a semiconductor device, the epitaxial layer 3 is used as a drift region of the semiconductor device, and it is understood that the materials of the substrate 1, the buffer layer 2 and the epitaxial layer 3 may be silicon, gallium arsenide or the like, and are not limited herein.
In detail, as shown in fig. 1, in the embodiment of the present invention, two junction field effect transistors (junction field effect transistor JFET1 and junction field effect transistor JFET 2) and one metal oxide field effect transistor MOSFET are integrated on a semiconductor device, where the metal oxide field effect transistor MOSFET includes a double-trench MOSFET, and the semiconductor device includes three first doped regions 5, two second gate trench structures 7 and two source trench structures 8, and the first second gate trench structures 7 (i.e., the second gate trench structures 7 on the left side in fig. 1), the first source trench structures 8 (i.e., the source trench structures 8 on the left side in fig. 1), the first gate trench structures 6, the second source trench structures 8 (i.e., the source trench structures 8 on the right side in fig. 1) and the second gate trench structures 7 (i.e., the second gate trench structures 7 on the right side in fig. 1) are sequentially arranged in a dispersed manner.
In more detail, as shown in fig. 1, the first gate trench structure 6 includes a gate insulating layer 60 and a conductive dielectric layer 61, the conductive dielectric layer 61 sequentially penetrates through the first doped region 5 and the base region 4 located in the base region 4 along the second direction, and the gate insulating layer 60 is disposed in the epitaxial layer 3 and covers the conductive dielectric layer 61; the second gate trench structure 7 comprises a second doped region 70 of a second doping type and a conductive medium layer 71, the conductive medium layer 71 penetrates through the first doped region 5 partially overlapped with the base region 4 along a second direction, the second doped region 70 is arranged in the epitaxial layer 3, and the second doped region 70 covers the conductive medium layer 71 and is in contact with the conductive medium layer 71; the source trench structure 8 includes a second doped region 80 of a second doping type and a conductive dielectric layer 81, the conductive dielectric layer 81 penetrates the base region 4 along a second direction and extends to the bottom of the epitaxial layer 3, the second doped region 80 is disposed in the epitaxial layer 3, and the second doped region 80 wraps the conductive dielectric layer 81 and contacts the conductive dielectric layer 81.
In detail, as shown in fig. 1, in an embodiment of the present invention, the semiconductor device further includes:
an insulating dielectric layer 9 disposed on the epitaxial layer 3 and covering the first gate trench structure 6 and the second gate trench structure 7;
a source ohmic contact layer 10 disposed on the epitaxial layer 3, contacting and covering the source trench structure 8;
a source metal layer 11 covering the insulating dielectric layer 9 and the source ohmic contact layer 10;
a drain ohmic contact layer 12 disposed on the back surface of the substrate 1;
and a drain metal layer 13 covering the drain ohmic contact layer 12.
The first doping type is opposite to the second doping type, namely the first doping type is one of P type doping and N type doping, and the second doping type is the other of P type doping and N type doping.
In more detail, as shown in fig. 1 to 2, the semiconductor device proposed in the embodiment of the present invention is mainly divided into two parts, a trench junction field effect transistor (junction field effect transistor JFET1 and junction field effect transistor JFET 2) and a trench metal oxide field effect transistor MOSFET. Wherein, the junction field effect tube JFET1 and the junction field effect tube JFET2 are depletion type junction field effect tubes.
Specifically, the junction field effect tube JFET1 is formed on the left side of fig. 1 and 2, the first second gate trench structure 7 forms the gate of the junction field effect tube JFET1, the second gate trench structure 7 is of the second doping type, the insulating dielectric layer 9 electrically isolates the source metal layer 11 from the gate, the first source trench structure 8 is shorted to the source ohmic contact layer 10 to form the source of the junction field effect tube JFET1, the source trench structure 8 is of the second doping type, the base region 4 of the second doping type at the side wall of the first source trench structure 8 forms the base region structure of the junction field effect tube JFET1, a conductive channel of the junction field effect tube JFET1 is formed between the second doping region 70 of the side wall of the second gate trench structure 7 and the base region structure, and due to the existence of the deep trench in the source, when the junction field effect tube JFET1 is turned off, the electric field intensity received at the conductive channel position can be greatly reduced, and the device leakage is reduced. Similarly, on the right side of fig. 1 and 2, a junction field effect transistor JFET2 is formed based on the second source trench structure 8 and the second gate trench structure 7, which will not be described herein.
Specifically, in the middle position of fig. 1 and 2, a double-trench MOSFET is formed based on the first source trench structure 8, the first gate trench structure 6 and the second source trench structure 8, the top of the first gate trench structure 6 is covered by the insulating dielectric layer 9, a gate of the MOSFET is formed, the conductive dielectric layers 81 in the two source trench structures 8 on two sides of the gate are in contact with the source ohmic contact layer 10, a source of the MOSFET is formed, and the source is a double-trench structure, and the double-trench structure can weaken the electric field strength of the gate oxide layer when the device is turned off, reduce low leakage of the device, and improve the reliability of the device.
In more detail, as shown in fig. 2, in the semiconductor device provided in the embodiment of the present invention, the junction field effect transistor JFET1, JFET2 and the metal oxide field effect transistor MOSFET have different driving voltages and channel turn-on capabilities, but the junction field effect transistor JFET1, JFET2 and the metal oxide field effect transistor MOSFET are arranged in parallel and share the source trench structure 8, by adjusting different driving voltage differences between the junction field effect transistor JFET1, JFET2 and the metal oxide field effect transistor MOSFET, the junction field effect transistor and the metal oxide field effect transistor integrated on the same semiconductor device can be synchronously controlled, and simultaneously, the channel turn-off capabilities of the junction field effect transistor JFET1, JFET2 and the metal oxide field effect transistor MOSFET have different channel turn-off capabilities than those of the junction field effect transistor JFET MOSFET, and the junction field effect transistor JFET2 are weaker than those of the metal oxide field effect transistor MOSFET when the junction field effect transistor JFET1, JFET2 and the metal oxide field effect transistor MOSFET are synchronously turned off, the junction field effect transistor JFET1, the junction field effect transistor JFET2 and the metal oxide MOSFET are more turned off, the reverse current can be prevented from flowing through the reverse surge condition of the junction field effect transistor MOSFET, and the reverse surge current can be prevented from flowing through the reverse surge condition of the metal transistor MOSFET.
Meanwhile, as shown in fig. 3 to 14, the embodiment of the invention further provides a method for manufacturing a semiconductor device, which includes the steps of:
s1, as shown in FIG. 4, providing a substrate 1, wherein the substrate 1 is provided with a front surface and a back surface which are oppositely arranged, a buffer layer 2 is formed on the front surface of the substrate 1, an epitaxial layer 3 is formed on the buffer layer 2, and the substrate 1, the buffer layer 2 and the epitaxial layer 3 are all of a first doping type;
s2, as shown in fig. 5-6, performing ion implantation on the epitaxial layer 3, forming a base region 4 of a second doping type and a plurality of first doping regions 5 of a first doping type in a region of the epitaxial layer 3 far from the buffer layer 2, wherein the plurality of first doping regions 5 are sequentially and dispersedly arranged along a first direction, one first doping region 5 is positioned in the base region 4, and the rest of first doping regions 5 are partially overlapped with the base region 4;
s3, as shown in FIGS. 7-8, etching to form a first trench T1, a second trench T2 and a third trench T3, wherein the first trench T1 sequentially penetrates through a first doped region 5 and the base region 4 in the base region 4 along a second direction, the second trench T2 penetrates through the first doped region 5 partially overlapped with the base region 4 along the second direction, and the third trench T3 penetrates through the base region 4 along the second direction and extends to one side of the epitaxial layer 3 close to the buffer layer 2;
S4, forming a first grid groove structure 6 along the first groove T1, forming a second grid groove structure 7 along the second groove T2, and forming a source groove structure 8 along the third groove T3;
s5, forming an insulating medium layer 9 and a source ohmic contact layer 10 on the epitaxial layer 3, and forming a source metal layer 11, wherein the insulating medium layer 9 covers the first grid groove structure 6 and the second grid groove structure 7, the source ohmic contact layer 10 contacts and covers the source groove structure 8, and the source metal layer 11 covers the insulating medium layer 9 and the source ohmic contact layer 10;
s6, forming a drain ohmic contact layer 12 and a drain metal layer 13 on the back surface of the substrate 1, wherein the drain ohmic contact layer 12 is positioned on the back surface of the substrate 1, and the drain metal layer 13 covers the drain ohmic contact layer 12;
wherein the first direction is perpendicular to the second direction.
In detail, as shown in fig. 4, in step S1, a substrate 1 is provided and a buffer layer 2 and an epitaxial layer 3 are formed on the substrate 1 by a deposition process and a doping process, wherein the substrate 1 mainly serves as a drain region of a semiconductor device, the epitaxial layer 3 serves as a drift region of the semiconductor device, the substrate 1, the buffer layer 2 and the epitaxial layer 3 may be made of silicon carbide materials so as to form a silicon carbide device later, and it is understood that the materials of the substrate 1, the buffer layer 2 and the epitaxial layer 3 may also be silicon, gallium arsenide, etc., which are not limited herein. Meanwhile, the substrate 1 is heavily doped, the buffer layer 2 is medium doped, and the epitaxial layer 3 is lightly doped.
Wherein the doping types and specific parameters of the substrate 1, the buffer layer 2 and the epitaxial layer 3 can be flexibly designed, for example, the first doping type is set to be N-type doping, i.e. the doping types of the substrate 1, the buffer layer 2 and the epitaxial layer 3 are all N-type doping (such as phosphorus ions or arsenic ions), the thickness of the substrate 1 is set to be 200-350 μm, and the doping concentration of the substrate 1 is set to be (1-9) ×10 19 cm -3 The thickness of the buffer layer 2 is set to 0.1-1 μm, preferably 0.5 μm, and the doping concentration of the buffer layer 2 is set to (1-9). Times.10 18 cm -3 The thickness of the epitaxial layer 3 is set to 2-40 μm, and the doping concentration of the epitaxial layer 3 is set to 1×10 14 ~1×10 17 cm -3 。
In detail, between the step S1 and the step S2, the method for manufacturing the semiconductor device further includes the steps of: and a photoetching alignment mark is formed on the epitaxial layer 3 by adopting an industry passing method, so that alignment of subsequent process steps is facilitated. Details can be found in the prior art and are not described in detail here.
In detail, as shown in fig. 5 to 6, the step S2 of performing ion implantation on the epitaxial layer 3 to form a base region 4 of the second doping type and a plurality of first doping regions 5 of the first doping type in a region of the epitaxial layer 3 remote from the buffer layer 2, further includes:
s21, as shown in FIG. 5, performing ion implantation of a second doping type on the epitaxial layer 3, and forming a base region 4 in a region of the epitaxial layer 3 away from the buffer layer 2;
S22, as shown in fig. 6, the epitaxial layer 3 is subjected to ion implantation of the first doping type, a plurality of first doping regions 5 which are independent of each other are formed in the region of the epitaxial layer 3 far from the buffer layer 2, the doping depth of the first doping regions 5 along the second direction is smaller than the doping depth of the base region 4 along the second direction, and the dimension of the first doping regions 5 along the first direction is smaller than the dimension of the base region 4 along the first direction.
In more detail, as shown in fig. 5, in step S21, the epitaxial layer 3 is ion-implanted with a second doping type, the second doping type being P-type doping, the doping impurity being Al, the doping concentration being 1×10 16 -5×10 18 cm -3 A base region 4 is formed in a region of the epitaxial layer 3 remote from the buffer layer 2.
In more detail, as shown in fig. 6, in step S22, the epitaxial layer 3 is ion-implanted with a first doping type, which is N-type doping, at a doping concentration of 1×10 18 -9×10 19 cm -3 Forming 3 mutually independent first doped regions 5 in the region of the epitaxial layer 3 far from the buffer layer 2, wherein the doping depth of the first doped regions 5 along the second direction is smaller than that of the base region 4 along the second direction, and the size of the first doped regions 5 along the first direction is smaller than that of the base region 4 along the first direction; meanwhile, 3 first doped 5 regions are sequentially and dispersedly arranged along the first direction, along the first direction To this end, a first doped region 5 (first doped region 5 on the left in fig. 1) overlaps with the base region 4, a second first doped region 5 (first doped region 5 in the middle in fig. 1) is located in the base region 4, and a third first doped region 5 (first doped region 5 on the right in fig. 1) overlaps with the base region 4.
In detail, as shown in fig. 7 to 8, the step S3 of etching to form the first trench T1, the second trench T2 and the third trench T3 further includes:
s31, as shown in FIG. 7, performing first etching on the epitaxial layer 3 to form a third groove T3;
s32, as shown in FIG. 8, performing second etching on the epitaxial layer 3 to synchronously form a first groove T1 and a second groove T2;
the depth of the first trench T1 is the same as the depth of the second trench T2, and the depth of the third trench T3 is greater than the depth of the first trench T1.
In more detail, as shown in fig. 7, in step S31, the epitaxial layer 3 is etched for the first time, and deep trench etching is performed between two adjacent first doped regions 5 along the first direction, so as to form two third trenches T3, where the third trenches T3 penetrate the base region 4 along the second direction and extend to a side of the epitaxial layer 3 near the buffer layer 2, and the depth of the third trenches T3 is greater than the doping depth of the base region 4.
In more detail, as shown in fig. 8, in step S32, the epitaxial layer 3 is etched for the second time, and shallow trench etching is performed inside each first doped region 5 along the first direction to form a first trench T1 and two second trenches T2, the first trench T1 penetrates the second first doped region 5 and the base region 4 in sequence along the second direction as seen along the first direction, the first second trench T2 penetrates the first doped region 5 along the second direction, the second trench T2 penetrates the third first doped region 5 along the second direction, and based on synchronous etching, the depth of the first trench T1 is the same as the depth of the second trench T2, and the depth of the first trench T1 is slightly larger than the doping depth of the base region 4, so that the depth of the third trench T3 is larger than the depth of the first trench T1.
In detail, as shown in fig. 9 to 11, the step S4 of forming the first gate trench structure 6 along the first trench T1, forming the second gate trench structure 7 along the second trench T2, and forming the source trench structure 8 along the third trench T3, further includes:
s41, as shown in fig. 9, performing ion implantation of a second doping type along the second trench T2 and the third trench T3 and annealing, forming a second doping region 70 covering the second trench T2 and a second doping region 80 covering the third trench T3 in the epitaxial layer 3;
S42, as shown in fig. 10, performing thermal oxidation along the first trench T1, the second trench T2, and the third trench T3 to form a trench insulating layer 60, and removing the trench insulating layer 60 in the second trench T2 and the trench insulating layer 60 in the third trench T3;
s43, as shown in fig. 11, the first trench T1 is filled with the conductive medium layer 61, the second trench T2 is filled with the conductive medium layer 71, and the third trench T3 is filled with the conductive medium layer 81 by deposition and surface planarization.
In more detail, as shown in fig. 9, in step S41, the first trench T1 is masked to expose the second trench T2 and the third trench T3, ion implantation of a second doping type is performed along the second trench T2 and the third trench T3, and annealing is performed, the corresponding doping impurity is Al, and the doping concentration is 1×10 19 -1×10 20 cm -3 The second doped region 70 is formed along the sidewall and bottom of the second trench T2, and the second doped region 80 is formed along the sidewall and bottom of the third trench T3.
In more detail, as shown in fig. 10, in step S42, the masking of the first trench T1 is removed, the first trench T1, the second trench T2 and the third trench T3 are exposed, thermal oxidation is performed along the first trench T1, the second trench T2 and the third trench T3, trench insulating layers 60 are formed on the side walls and the bottom of each trench, respectively, and the trench insulating layers 60 in the second trench T2 and the trench insulating layers 60 in the third trench T3 are removed, only the trench insulating layers 60 on the side walls and the bottom of the first trench T1 remain, the thickness of the trench insulating layers 60 is 40-200nm, and the material of the trench insulating layers 60 is silicon oxide (SiO 2 ). It will be appreciated that the trench insulating layer 60 can be realized not only by a thermal oxidation process, but also by a deposition processNow, the material is not limited to silicon oxide, but may be silicon nitride (SiN), hafnium oxide (HfO) 2 ) And the like, are not limited herein.
In more detail, as shown in fig. 11, in step S43, the corresponding deposition filling material may be one of N-type doped polysilicon and P-type doped polysilicon, the first trench T1 is filled with the formation of the conductive medium layer 61, the second trench T2 is filled with the formation of the conductive medium layer 71, and the third trench T3 is filled with the formation of the conductive medium layer 81 by deposition and surface planarization processes. The conductive medium layer 71 and the conductive medium layer 81 are both of the second doping type, and the conductive medium layer 61 may be of the first doping type or the second doping type, which will not be described herein.
In detail, as shown in fig. 12 to 13, step S5 of forming the insulating dielectric layer 9 and the source ohmic contact layer 10 on the epitaxial layer 3, and forming the source metal layer 11, further includes:
s51, as shown in FIG. 12, an insulating medium layer 9 is formed on the epitaxial layer 3 by adopting a deposition process and an etching process, and the insulating medium layer 9 covers the first gate trench structure 6 and the second gate trench structure 7;
S52, as shown in fig. 13, a deposition process, an etching process, a deposition process and a surface planarization process are sequentially used to form a source ohmic contact layer 10 on the epitaxial layer 3, and form a source metal layer 11, where the source ohmic contact layer 10 contacts and covers the source trench structure 8, and the source metal layer 11 covers the insulating dielectric layer 9 and the source ohmic contact layer 10.
In more detail, as shown in fig. 12, in step S51, an insulating dielectric layer 9 is formed on the epitaxial layer 3 by deposition followed by etching, the insulating dielectric layer 9 covers the first gate trench structure 6, the second gate trench structure 7 and a partial region of the first doped region 5 to electrically isolate the first gate trench structure 6, the second gate trench structure 7 from a source ohmic contact layer 10 and a source metal layer 11 which are subsequently formed, and the insulating dielectric layer 9 may be made of silicon oxide (SiO 2 ) The thickness of the insulating dielectric layer 9 is 0.5-2 μm.
In more detail, as shown in fig. 13, in step S52, a deposition process and an etching process are sequentially used to form a source ohmic contact layer 10 on the epitaxial layer 3, wherein the source ohmic contact layer 10 covers the source trench structure 8, a partial region of the base region 4 and a partial region of the first doped region 5, and forms a good ohmic contact with the above regions, and the material of the source ohmic contact layer 10 includes but is not limited to Ti/Ni/W and the like; and then a deposition process and a surface planarization process are sequentially adopted to form a source metal layer 11, wherein the source metal layer 11 is positioned above the insulating dielectric layer 9 and the source ohmic contact layer 10 and forms good contact with the source ohmic contact layer 10 to form a source of the semiconductor device, and materials of the source metal layer 11 comprise but are not limited to Al/AlSi/AlCu/AlSiCu and the like.
In detail, as shown in fig. 14, in step S6, the drain ohmic contact layer 12 and the drain metal layer 13 are formed on the back surface of the substrate 1 by two deposition processes in sequence, the drain ohmic contact layer 12 is located on the back surface of the substrate 1, the drain ohmic contact layer 12 forms ohmic contact with the substrate 1 at the interface, the material of the drain ohmic contact layer 12 includes but is not limited to Ti/Ni, etc., the drain metal layer 13 covers the drain ohmic contact layer 12, and the drain metal layer 13 forms good contact with the drain ohmic contact layer 12, the material of the drain metal layer 13 includes but is not limited to TiNiAg, etc.
Finally, based on the manufacturing method of the semiconductor device, the semiconductor device shown in fig. 1, 2 or 14 is manufactured, two junction field effect transistors and one metal oxide field effect transistor are integrated on the semiconductor device, one junction field effect transistor is respectively integrated on two sides of the metal oxide field effect transistor, the junction field effect transistor and the metal oxide field effect transistor are arranged in parallel and share a source electrode groove structure, synchronous switching control can be carried out on the junction field effect transistor and the metal oxide field effect transistor integrated on the same semiconductor device, the channel closing capacity of the junction field effect transistor is weaker than that of the metal oxide field effect transistor, when the junction field effect transistor and the metal oxide field effect transistor are closed synchronously, the closing degree of a conductive channel of the junction field effect transistor is smaller, surge current under a reverse surge condition preferentially passes through conductive channels of the junction field effect transistor on two sides, the surge current under the reverse surge condition almost does not flow through the metal oxide field effect transistor, the phenomenon that the reverse surge current causes avalanche effect transistor and avalanche effect transistor can be effectively avoided, and the reliability of the metal oxide field effect transistor is improved. Meanwhile, the manufacturing method of the semiconductor device is compatible with the manufacturing process of the mainstream trench type metal oxide field effect transistor at present, the process flow is simple, the cost is low, and the manufacturing method is suitable for mass production.
In addition, the steps of the above embodiments omit other basic steps and simple procedures commonly known and obvious in the industry, such as cleaning, which are well known to those skilled in the art, and are not described in detail herein.
Example two
In the first embodiment of the invention, two junction field effect transistors and one metal oxide field effect transistor are integrated on the semiconductor device, one junction field effect transistor is respectively integrated on two sides of the metal oxide field effect transistor, the junction field effect transistor and the metal oxide field effect transistor are arranged in parallel and share a source electrode groove structure, so that synchronous switching control can be carried out on the junction field effect transistor and the metal oxide field effect transistor on the semiconductor device, the channel closing capability of the junction field effect transistor is weaker than that of the metal oxide field effect transistor, when the junction field effect transistor and the metal oxide field effect transistor are synchronously closed, the closing degree of a conductive channel of the junction field effect transistor is smaller, and surge current generated under a reverse surge condition preferentially flows through the conductive channels of the two junction field effect transistors integrated on two sides of the metal oxide field effect transistor, thereby improving the avalanche resistance of the metal oxide field effect transistor and improving the reliability of the metal oxide field effect transistor.
However, the two junction field effect transistors cooperate with the discharging treatment of the surge current generated when the metal oxide field effect transistor is turned off, the structure of the corresponding semiconductor device is complex, the corresponding process steps are complex, and the cost performance and the practicability of the semiconductor device are questionable.
Based on this, the embodiment of the present invention is improved based on the first embodiment, and one junction field effect transistor is removed, and only one junction field effect transistor is integrated on one side of the metal oxide field effect transistor, that is, one junction field effect transistor and one metal oxide field effect transistor are integrated on the semiconductor device, as shown in fig. 15, the junction field effect transistor JFET1 and the metal oxide field effect transistor MOSFET which are arranged in parallel are integrated on the semiconductor device. In which, the MOSFET is also a double-trench MOSFET, compared with the first embodiment, the semiconductor device has one less second gate trench structure 7 on the rightmost side.
In detail, as shown in fig. 15, the semiconductor device includes two first doped regions 5, one second gate trench structure 7 and two source trench structures 8, and the second gate trench structure 7, the first source trench structure 8, the first gate trench structure 6 and the second source trench structure 8 are sequentially arranged in a dispersed manner as viewed along the first direction. The second gate trench structure 7 and the first source trench structure 8 cooperate with the corresponding doped region, the corresponding ohmic contact layer and the corresponding electrode metal layer to form a junction field effect transistor JFET1, and the first gate trench structure 6 and the two source trench structures 8 cooperate with the corresponding doped region, the corresponding ohmic contact layer and the corresponding electrode metal layer to form a metal oxide field effect transistor MOSFET, and the junction field effect transistor JFET1 and the metal oxide field effect transistor MOSFET are arranged in parallel and share the first source trench structure 8.
It should be noted that the detailed structure of the semiconductor device in the embodiment of the present invention can be analyzed by analogy with the related description in the first embodiment, and will not be described herein.
In more detail, as shown in fig. 16, the semiconductor device in the embodiment of the invention is integrated with the junction field effect transistor JFET1 and the metal oxide field effect transistor MOSFET, the junction field effect transistor JFET1 and the metal oxide field effect transistor MOSFET are arranged in parallel and share the first source trench structure 8, when the junction field effect transistor JFET1 and the metal oxide field effect transistor MOSFET are synchronously turned off, the closing degree of the conductive channel of the junction field effect transistor JFET1 is smaller, and the surge current generated under the reverse surge condition is preferentially discharged through the conductive channel of the junction field effect transistor JFET1, so that the avalanche resistance of the metal oxide field effect transistor MOSFET can be improved, and the reliability of the metal oxide field effect transistor MOSFET can be improved. Meanwhile, compared with the first embodiment, the junction field effect transistor is integrated on one side of the metal oxide field effect transistor, the structure corresponding to the semiconductor device is simpler, the corresponding process steps are simpler, the cost performance and the practicability are higher, and the junction field effect transistor can be used in application scenes with low requirements on the discharge of certain surge currents.
In addition, the embodiment of the present invention further provides a method for manufacturing a semiconductor device, which is used for manufacturing the semiconductor device shown in fig. 15 and 16, and the detailed process thereof can be analyzed by analogy with the related description in the first embodiment, and will not be repeated here.
Example III
In the second embodiment of the invention, a junction field effect transistor and a metal oxide field effect transistor are integrated on the semiconductor device, when the junction field effect transistor and the metal oxide field effect transistor are closed synchronously, surge current generated under a reverse surge condition is discharged preferentially through a conductive channel of the junction field effect transistor, and hardly flows through the conductive channel of the metal oxide field effect transistor, so that avalanche resistance of the metal oxide field effect transistor is improved, and reliability of the metal oxide field effect transistor is improved; the structure corresponding to the semiconductor device is simpler, the corresponding process steps are simpler, the cost performance and the practicability are higher, and the semiconductor device can be used in application scenes with low discharge requirements of certain surge currents.
However, the structure of the semiconductor device in the second embodiment is still relatively complex, and the trade-off between the surge current resistance and the structural complexity is further optimized.
Based on this, the embodiment of the present invention is improved based on the second embodiment, and on the basis of integrating a junction field effect transistor and a metal oxide field effect transistor on the semiconductor device, compared with the second embodiment, the semiconductor device has one less right-side source trench structure 8, and the metal oxide field effect transistor MOSFET is changed from a double trench structure to a single trench structure, so as to further optimize the structure of the simplified semiconductor device.
In detail, as shown in fig. 17, a junction field effect transistor JFET1 and a metal oxide field effect transistor MOSFET are integrated on a semiconductor device, wherein the metal oxide field effect transistor MOSFET includes a single trench type metal oxide field effect transistor, the semiconductor device includes two first doped regions 5, a second gate trench structure 7 and a source trench structure 8, and the second gate trench structure 7, the source trench structure 8 and the first gate trench structure 6 are sequentially and dispersedly arranged as seen along a first direction.
The second gate trench structure 7 and the source trench structure 8 cooperate with the corresponding doped region, the corresponding ohmic contact layer and the corresponding electrode metal layer to form a junction field effect transistor JFET1, the first gate trench structure 6 and the source trench structure 8 cooperate with the corresponding doped region, the corresponding ohmic contact layer and the corresponding electrode metal layer to form a single trench type metal oxide field effect transistor MOSFET, and the junction field effect transistor JFET1 and the single trench type metal oxide field effect transistor MOSFET are arranged in parallel and share the source trench structure 8.
It should be noted that the detailed structure of the semiconductor device in the embodiment of the present invention can be analyzed by analogy with the related description in the first embodiment, and will not be described herein.
In more detail, as shown in fig. 18, the semiconductor device in the embodiment of the invention is integrated with the junction field effect transistor JFET1 and the single trench type metal oxide field effect transistor MOSFET, the junction field effect transistor JFET1 and the single trench type metal oxide field effect transistor MOSFET are arranged in parallel and share the first source trench structure 8, when the junction field effect transistor JFET1 and the metal oxide field effect transistor MOSFET are synchronously turned off, the closing degree of the conductive channel of the junction field effect transistor JFET1 is smaller, and the surge current generated under the reverse surge condition is preferentially discharged through the conductive channel of the junction field effect transistor JFET1, so that the avalanche resistance of the metal oxide field effect transistor MOSFET can be improved, and the reliability of the metal oxide field effect transistor MOSFET can be improved. Meanwhile, compared with the second embodiment, the surge current discharging capability during closing is better, the structure of the metal oxide field effect transistor MOSFET is simplified, the structure of the corresponding semiconductor device is further simplified, the corresponding process steps are simpler, the cost performance and the practicability are higher, and the surge current discharging device can be used in certain application scenes with low requirements on the use performance of the metal oxide field effect transistor MOSFET and low requirements on the discharging of the surge current.
In addition, the embodiment of the present invention further provides a method for manufacturing a semiconductor device, which is used for manufacturing the semiconductor device shown in fig. 17 and 18, and the detailed process thereof can be analyzed by analogy with the related description in the first embodiment, and will not be repeated here.
In summary, in the semiconductor device and the manufacturing method thereof provided by the invention, the junction field effect transistor and the metal oxide field effect transistor which are arranged in parallel and share the source electrode groove structure are integrated on the same semiconductor device, so that the junction field effect transistor is interconnected with the conductive channel of the metal oxide field effect transistor, the junction field effect transistor and the metal oxide field effect transistor can be synchronously controlled in a switching manner, the principle that the channel closing capability of the junction field effect transistor is weaker than that of the metal oxide field effect transistor is utilized, when the junction field effect transistor and the metal oxide field effect transistor are synchronously closed, the surge current under the reverse surge condition is preferentially caused to pass through the conductive channel of the junction field effect transistor, the surge current under the reverse surge condition is hardly caused to flow through the metal oxide field effect transistor, the current leakage problem of the metal oxide field effect transistor under the reverse surge condition is solved, the avalanche heating phenomenon and the avalanche dislocation phenomenon of the metal oxide field effect transistor caused by the reverse surge current can be effectively avoided, the anti-surge capability of the metal oxide field effect transistor is improved, and the reliability of the metal oxide field effect transistor is improved; meanwhile, the corresponding manufacturing method is compatible with the manufacturing process of the mainstream trench type metal oxide field effect transistor at present, the process flow is simple, the cost is low, and the method is suitable for mass production.
The above embodiments are merely illustrative of the principles of the present invention and its effectiveness, and are not intended to limit the invention. Modifications and variations may be made to the above-described embodiments by those skilled in the art without departing from the spirit and scope of the invention. Accordingly, it is intended that all equivalent modifications and variations of the invention be covered by the claims, which are within the ordinary skill of the art, be within the spirit and scope of the present disclosure.

Claims (10)

1. A semiconductor device, wherein a junction field effect transistor and a metal oxide field effect transistor arranged in parallel are integrated on the semiconductor device, the junction field effect transistor and the metal oxide field effect transistor share a source trench structure, the semiconductor device comprising:
a substrate of a first doping type having oppositely disposed front and back surfaces;
a buffer layer of a first doping type disposed on the front surface of the substrate;
the epitaxial layer with the first doping type is arranged on the buffer layer, a base region with the second doping type and a plurality of first doping regions with the first doping type are arranged in a region far away from the buffer layer, the first doping regions are sequentially and dispersedly arranged along a first direction, one first doping region is positioned in the base region, and the rest of first doping regions are partially overlapped with the base region;
The first grid electrode groove structure is arranged in the epitaxial layer and sequentially penetrates through the first doping region and the base region in the base region along a second direction;
the second grid electrode groove structure is arranged in the epitaxial layer and located outside the base region, and penetrates through the first doping region which is partially overlapped with the base region along the second direction;
the source electrode groove structure is arranged in the epitaxial layer, penetrates through the base region along the second direction and extends to one side, close to the buffer layer, of the epitaxial layer;
wherein the first direction and the second direction are perpendicular to each other.
2. The semiconductor device of claim 1, wherein two junction field effect transistors and one metal oxide field effect transistor are integrated on the semiconductor device, the metal oxide field effect transistor comprises a double-trench metal oxide field effect transistor, the semiconductor device comprises three first doped regions, two second gate trench structures and two source trench structures, and the first second gate trench structure, the first source trench structure, the first gate trench structure, the second source trench structure and the second gate trench structure are sequentially arranged in a scattered manner when viewed along the first direction.
3. The semiconductor device of claim 1, wherein one junction field effect transistor and one metal oxide field effect transistor are integrated on the semiconductor device, the metal oxide field effect transistor comprises a double-trench metal oxide field effect transistor, the semiconductor device comprises two first doped regions, one second gate trench structure and two source trench structures, and the second gate trench structure, the first source trench structure, the first gate trench structure and the second source trench structure are sequentially arranged in a scattered manner when viewed along the first direction.
4. The semiconductor device of claim 1, wherein the semiconductor device is integrated with one junction field effect transistor and one metal oxide field effect transistor, the metal oxide field effect transistor comprises a single trench type metal oxide field effect transistor, and the semiconductor device comprises two first doped regions, one second gate trench structure and one source trench structure, and the second gate trench structure, the source trench structure and the first gate trench structure are sequentially arranged in a scattered manner as viewed along the first direction.
5. The semiconductor device according to claim 1, wherein the semiconductor device further comprises:
the insulating medium layer is arranged on the epitaxial layer and covers the first grid electrode groove structure and the second grid electrode groove structure;
the source electrode ohmic contact layer is arranged on the epitaxial layer and contacts with and covers the source electrode groove structure;
a source metal layer covering the insulating dielectric layer and the source ohmic contact layer;
a drain ohmic contact layer disposed on a back surface of the substrate;
and the drain electrode metal layer covers the drain electrode ohmic contact layer.
6. The semiconductor device of any of claims 1-5, wherein the first doping type is doped with a conductivity type opposite to the conductivity type doped with the second doping type.
7. A method of fabricating a semiconductor device, comprising the steps of:
providing a substrate, wherein the substrate is provided with a front surface and a back surface which are oppositely arranged, a buffer layer is formed on the front surface of the substrate, an epitaxial layer is formed on the buffer layer, and the substrate, the buffer layer and the epitaxial layer are all of a first doping type;
performing ion implantation on the epitaxial layer, forming a base region of a second doping type and a plurality of first doping regions of a first doping type in a region of the epitaxial layer far away from the buffer layer, wherein the first doping regions are sequentially and dispersedly arranged along a first direction, one first doping region is positioned in the base region, and the rest first doping regions are partially overlapped with the base region;
Etching to form a first groove, a second groove and a third groove, wherein the first groove sequentially penetrates through the first doping region and the base region which are positioned in the base region along a second direction, the second groove penetrates through the first doping region which partially overlaps with the base region along the second direction, and the third groove penetrates through the base region along the second direction and extends to one side of the epitaxial layer close to the buffer layer;
forming a first gate trench structure along the first trench, forming a second gate trench structure along the second trench, and forming a source trench structure along the third trench;
forming an insulating medium layer and a source electrode ohmic contact layer on the epitaxial layer, and forming a source electrode metal layer, wherein the insulating medium layer covers the first grid electrode groove structure and the second grid electrode groove structure, the source electrode ohmic contact layer contacts with and covers the source electrode groove structure, and the source electrode metal layer covers the insulating medium layer and the source electrode ohmic contact layer;
forming a drain ohmic contact layer and a drain metal layer on the back surface of the substrate, wherein the drain ohmic contact layer is positioned on the back surface of the substrate, and the drain metal layer covers the drain ohmic contact layer;
Wherein the first direction is perpendicular to the second direction.
8. The method of manufacturing a semiconductor device according to claim 7, wherein the step of performing ion implantation on the epitaxial layer to form a base region of the second doping type and a plurality of first doping regions of the first doping type in a region of the epitaxial layer away from the buffer layer, comprises:
performing ion implantation of the second doping type on the epitaxial layer, and forming the base region in a region of the epitaxial layer away from the buffer layer;
and carrying out ion implantation of the first doping type on the epitaxial layer, and forming a plurality of mutually independent first doping regions in the region of the epitaxial layer far away from the buffer layer, wherein the doping depth of the first doping regions along the second direction is smaller than that of the base regions along the second direction, and the size of the first doping regions along the first direction is smaller than that of the base regions along the first direction.
9. The method of manufacturing a semiconductor device according to claim 8, wherein the step of etching to form the first trench, the second trench, and the third trench comprises:
Performing first etching on the epitaxial layer to form the third groove;
performing second etching on the epitaxial layer to synchronously form the first groove and the second groove;
the depth of the first groove is the same as that of the second groove, and the depth of the third groove is larger than that of the first groove.
10. The method of manufacturing a semiconductor device according to claim 9, wherein the step of forming a first gate trench structure along the first trench, forming a second gate trench structure along the second trench, and forming a source trench structure along the third trench, comprises:
performing ion implantation of the second doping type along the second groove and the third groove and annealing, and forming a second doping region wrapping the second groove or the third groove in the epitaxial layer;
performing thermal oxidation along the first groove, the second groove and the third groove to form a groove insulating layer, and removing the groove insulating layer in the second groove and the groove insulating layer in the third groove;
and filling and forming conductive medium layers in the first groove, the second groove and the third groove respectively through deposition and surface planarization treatment.
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