CN111081759A - Enhanced silicon carbide MOSFET device and manufacturing method thereof - Google Patents
Enhanced silicon carbide MOSFET device and manufacturing method thereof Download PDFInfo
- Publication number
- CN111081759A CN111081759A CN201911258411.XA CN201911258411A CN111081759A CN 111081759 A CN111081759 A CN 111081759A CN 201911258411 A CN201911258411 A CN 201911258411A CN 111081759 A CN111081759 A CN 111081759A
- Authority
- CN
- China
- Prior art keywords
- layer
- ions
- type body
- body region
- groove
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 229910010271 silicon carbide Inorganic materials 0.000 title claims abstract description 60
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 title claims abstract description 55
- 238000004519 manufacturing process Methods 0.000 title claims description 11
- 239000002184 metal Substances 0.000 claims abstract description 71
- 229910052751 metal Inorganic materials 0.000 claims abstract description 71
- 239000000758 substrate Substances 0.000 claims abstract description 28
- 230000004888 barrier function Effects 0.000 claims abstract description 26
- 210000000746 body region Anatomy 0.000 claims description 83
- 150000002500 ions Chemical class 0.000 claims description 67
- 238000002513 implantation Methods 0.000 claims description 37
- 238000005530 etching Methods 0.000 claims description 28
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 28
- 230000003647 oxidation Effects 0.000 claims description 26
- 238000007254 oxidation reaction Methods 0.000 claims description 26
- -1 boron ions Chemical class 0.000 claims description 22
- 238000000034 method Methods 0.000 claims description 21
- 229920005591 polysilicon Polymers 0.000 claims description 20
- 229910052796 boron Inorganic materials 0.000 claims description 16
- 238000000151 deposition Methods 0.000 claims description 13
- 238000005468 ion implantation Methods 0.000 claims description 13
- 239000012535 impurity Substances 0.000 claims description 12
- 239000000463 material Substances 0.000 claims description 11
- 238000001259 photo etching Methods 0.000 claims description 10
- 238000002347 injection Methods 0.000 claims description 9
- 239000007924 injection Substances 0.000 claims description 9
- 239000013078 crystal Substances 0.000 claims description 7
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 7
- 239000010936 titanium Substances 0.000 claims description 7
- 238000000137 annealing Methods 0.000 claims description 6
- 238000001312 dry etching Methods 0.000 claims description 6
- 230000008569 process Effects 0.000 claims description 6
- 229910052681 coesite Inorganic materials 0.000 claims description 5
- 229910052906 cristobalite Inorganic materials 0.000 claims description 5
- 230000008021 deposition Effects 0.000 claims description 5
- 239000007789 gas Substances 0.000 claims description 5
- 239000007943 implant Substances 0.000 claims description 5
- 229910052698 phosphorus Inorganic materials 0.000 claims description 5
- 239000011574 phosphorus Substances 0.000 claims description 5
- 239000000377 silicon dioxide Substances 0.000 claims description 5
- 229910052682 stishovite Inorganic materials 0.000 claims description 5
- 229910052905 tridymite Inorganic materials 0.000 claims description 5
- 239000000203 mixture Substances 0.000 claims description 4
- 229910052757 nitrogen Inorganic materials 0.000 claims description 4
- IJGRMHOSHXDMSA-UHFFFAOYSA-N nitrogen Substances N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 4
- QJGQUHMNIGDVPM-UHFFFAOYSA-N nitrogen group Chemical group [N] QJGQUHMNIGDVPM-UHFFFAOYSA-N 0.000 claims description 4
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 3
- 229910052719 titanium Inorganic materials 0.000 claims description 3
- 238000001039 wet etching Methods 0.000 claims description 3
- 238000001459 lithography Methods 0.000 claims description 2
- 238000005498 polishing Methods 0.000 claims description 2
- 239000000126 substance Substances 0.000 claims description 2
- 238000013461 design Methods 0.000 abstract description 4
- 230000000694 effects Effects 0.000 abstract description 4
- 230000005684 electric field Effects 0.000 abstract description 4
- 230000003247 decreasing effect Effects 0.000 abstract description 2
- 238000010586 diagram Methods 0.000 description 15
- 239000004065 semiconductor Substances 0.000 description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- 239000006227 byproduct Substances 0.000 description 3
- 230000003071 parasitic effect Effects 0.000 description 3
- 238000000206 photolithography Methods 0.000 description 3
- 229910004298 SiO 2 Inorganic materials 0.000 description 2
- 230000001186 cumulative effect Effects 0.000 description 2
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 239000000243 solution Substances 0.000 description 2
- XPDWGBQVDMORPB-UHFFFAOYSA-N Fluoroform Chemical compound FC(F)F XPDWGBQVDMORPB-UHFFFAOYSA-N 0.000 description 1
- 230000004075 alteration Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 238000011982 device technology Methods 0.000 description 1
- 238000005265 energy consumption Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 230000008092 positive effect Effects 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 238000003825 pressing Methods 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 230000003313 weakening effect Effects 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
- H01L27/0617—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type
- H01L27/0629—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type in combination with diodes, or resistors, or capacitors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/0445—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising crystalline silicon carbide
- H01L21/048—Making electrodes
- H01L21/0485—Ohmic electrodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/0445—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising crystalline silicon carbide
- H01L21/048—Making electrodes
- H01L21/0495—Schottky electrodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/8213—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using SiC technology
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
- H01L29/0623—Buried supplementary region, e.g. buried guard ring
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1095—Body region, i.e. base region, of DMOS transistors or IGBTs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/401—Multistep manufacturing processes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
- H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/45—Ohmic electrodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/47—Schottky barrier electrodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66053—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide
- H01L29/6606—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66053—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide
- H01L29/66068—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7827—Vertical transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
- H01L29/872—Schottky diodes
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
The invention discloses an enhanced silicon carbide MOSFET device, which sequentially comprises the following components from bottom to top: the device comprises a back metal, an N + type heavily doped SiC substrate, an N-epitaxial layer, an insulating medium layer and a front metal. The Schottky diode is integrated into the MOSFET device, and the area of the Schottky barrier metal layer is flexibly increased or decreased to adjust and adapt the current and the specification of the MOSFET and the Schottky diode, so that the switching speed of the MOSFET is increased, the switching loss is reduced, the performance and the reliability of the device can be greatly improved, and the application cost of the device is reduced. The design of the groove type SiC MOSFET is adopted, and a conductive channel is changed from the traditional horizontal direction to the vertical direction, so that the JFET effect among the cells of the traditional MOSFET is eliminated, and the current capacity of the device is improved. The gate bottom P region at the bottom of the trench can protect and weaken the electric field at the bottom of the trench, plays a certain role in electrostatic shielding of the gate oxide at the bottom of the trench, and improves the reliability of the device. Meanwhile, the voltage resistance of the device is also helped to a certain extent.
Description
Technical Field
The invention belongs to the technical field of semiconductor chip manufacturing processes, and particularly relates to an enhanced silicon carbide MOSFET device and a manufacturing method thereof.
Background
The third generation semiconductor material, silicon carbide (SiC), has many characteristics different from the traditional silicon semiconductor material, and the energy band gap of the third generation semiconductor material is 2.8 times of that of silicon, and reaches 3.09 electron volts; the dielectric breakdown field strength is 5.3 times of that of silicon and is as high as 3.2MV/cm, and the thermal conductivity is 3.3 times of that of silicon and is 49 w/cm.K. Therefore, the material becomes an ideal semiconductor material in the application occasions of high temperature, high frequency, high power and radiation resistance. Because the silicon carbide power device can obviously reduce the energy consumption of electronic equipment, the silicon carbide power device is widely applied in the field of new energy.
A Metal-Oxide-Semiconductor Field-effect transistor (MOSFET) is a core device of the next generation of high-efficiency power electronic device technology. Compared with a Si-MOSFET, the SiC MOSFET has smaller on-resistance, higher switching voltage, higher application frequency and better temperature performance, and is particularly suitable for power switch application. After years of research in the field, some prior arts have been able to prepare SiC MOSFET devices. In many practical application scenarios, the problems of slow switching speed and excessive switching loss of the SiC MOSFET device exist, and the current capability of the device is not reliable enough. Therefore, a solution is proposed in the prior art, i.e. to work with a diode in anti-parallel in a SiCMOSFET device. Therefore, the switching speed of the switching device can be increased, the switching loss is reduced, and the current capability and reliability of the device are improved.
However, the following problems exist in the prior art:
1. in the prior art, the source electrode and the p-well are often electrically connected and short-circuited, and the design mode of the device is actually equivalent to the parallel connection of a reverse bias diode between the source electrode and the channel. Due to the high forbidden band width of the SiC material, the turn-on voltage of the PN diode connected in anti-parallel is very high, and the corresponding loss is also large.
2. The current driving capability of the anti-parallel PN diode in the prior art is reduced, and the loss is increased.
Therefore, a solution is needed to increase the switching speed of the device, reduce the switching loss, and improve the current driving capability of the device. And the overall reliability of the device is improved.
Disclosure of Invention
Aiming at the problems in the prior art, the invention discloses an enhanced silicon carbide MOSFET and a manufacturing method thereof. This enhancement mode carborundum MOSFET device adopts the groove type structure, compares traditional plane type structure, and its conducting channel becomes vertical channel from the horizontal direction, and parasitic JFET resistance change schottky device between primitive cell and the primitive cell plays positive effects such as increase switching speed to carborundum MOSFET device, reduces switching loss. And because of the difference of the structure, the parasitic JFET resistance in the traditional structure does not exist any more, thereby playing the role of reducing the on-resistance of the MOSFET and improving the current capability of the MOSFET.
An enhanced silicon carbide MOSFET device according to the present invention is characterized in that it is formed sequentially from bottom to topComprises the following steps: a back metal formed from a combination of metal Ti, metal Ni, and metal Ag; an N + type heavily doped SiC substrate; the upper surface of the N-epitaxial layer comprises a plurality of P-type body regions which are arranged in parallel at intervals in the horizontal direction, the P-type body regions are formed downwards on the upper surface of the N-epitaxial layer and comprise first ions, and the P-type body regions are connected through Schottky barrier metal layers; a central region of the at least three P-type body region upper surfaces includes an N + source formed downward in the P-type body region upper surface central region, the N + source including second ions; a groove is arranged below the central region of the N + source electrode, and the depth of the groove is deeper than the P-type body region but is not contacted with the N + type heavily doped SiC substrate; the groove comprises a gate bottom P region, the gate bottom P region is arranged at the bottom of the groove and comprises third ions; the groove also comprises a polysilicon grid, and the polysilicon grid is filled in the whole groove; the N-epitaxial layer and the groove also comprise a gate oxide layer, and the gate oxide layer grows on the inner wall of the groove; the outer side of the N + source electrode on the upper surface of the P type body region also comprises a P type body region contact layer, the P type body region contact layer is formed on the upper surface of the P type body region in a downward arrangement mode, and the P type body region contact layer comprises fourth ions; the P-type body region further comprises a P + buried layer, the P + buried layer is arranged in the center of the P-type body region and outside the groove, and the P + buried layer comprises fifth ions; an ohmic contact metal layer is arranged above the N + source electrode, the P-type body region contact layer and the Schottky barrier metal layer; an insulating medium layer made of SiO2Composition is carried out; the insulating medium layer is arranged above the polycrystalline silicon grid electrode and the P-type body region contact layer; a front metal consisting of Al and having a thickness of 1-5 μm.
Preferably, the silicon carbide single crystal material used by the silicon carbide substrate can be one of 2H-SiC single crystal and 4H-SiC single crystal, and the doping concentration of the N + type heavily doped SiC substrate is 3 multiplied by 1019-3×1020ion/CM3。
Preferably, the doping concentration of the N-epitaxial layer is 1 × 1015-1×1016Ion of a single crystal/CM3The thickness is 10-30 μm, and the doped impurity is nitrogen element.
Preferably, the depth of the P-type body region is 1-3 μm, the first ions are boron ions, the depth of the N + source electrode is 0.2-0.8 μm, and the second ions are phosphorus ions.
Preferably, the third ion, the fourth ion and the fifth ion are boron ions.
Preferably, the doping concentration of the polysilicon is more than 1 × 1020ion/CM3。
Preferably, the thickness of the gate oxide layer is 0.04-0.1 μm.
Preferably, the thickness of the insulating medium layer isThe Schottky barrier metal layer is TiMo or TiW, and the thickness of the Schottky barrier metal layer isThe thickness of the ohmic contact metal layer is
According to one aspect of the invention, a method of fabricating an enhanced silicon carbide MOSFET device comprises: step 1: selecting an N + type heavily doped SiC substrate, and growing an N-epitaxial layer on the upper surface of the N + type heavily doped SiC substrate; step 2: first ions are downwards implanted into the upper surface of the N-epitaxial layer in a photoetching and ion implantation mode to form at least three P-type body regions which are arranged in parallel at intervals in the horizontal direction, and second ions are downwards implanted into the central regions of the upper surfaces of the at least three P-type body regions in an ion implantation mode to form an N + source electrode; and step 3: etching downwards to form a groove in the central area of the N + source electrode in a groove photoetching and groove etching mode, wherein the depth of the groove is 1.2-1.5 times of that of the P-type body area; and 4, step 4: injecting third ions downwards at the bottom of the groove in an ion injection mode to form a grid bottom P region; and 5: growing a first epitaxial layer on the upper surface of the N-epitaxial layer and the inner wall of the groove by a rapid thermal oxidation mode for 5-10 timesStripping the first gate oxide layer by a wet etching mode, and then forming a second gate oxide layer on the upper surface of the N-epitaxial layer and the inner wall of the groove by a furnace tube thermal oxidation mode; step 6: depositing polycrystalline silicon on the upper surface of the N-epitaxial layer and in the groove, and etching the polycrystalline silicon on the upper surface of the N-epitaxial layer through a CMP (chemical mechanical polishing) process; and 7: injecting fourth ions into the upper surface of the N-epitaxial layer below the second gate oxide layer to form a P-type body region contact layer; and 8: growing an insulating medium layer on the upper surface of the second gate oxide layer, wherein the insulating medium layer is made of SiO2Composition is carried out; and step 9: etching the insulating medium layer by photoetching and etching modes to form at least six channels, wherein the channels lead to the upper surface of the P-type body region and the upper surface of the N + source electrode, and the region formed by the at least six channels is a first region; step 10: implanting fifth ions on the upper surface of the P-type body region to which the channel leads in an ion implantation mode to form a P + buried layer, wherein the implantation depth of the fifth ions is 0.4-0.6 times of the depth of the P-type body region; step 11: etching through the P type body region contact layer, the second gate oxide layer and the insulating medium layer above the regions among the P type body regions in a dry etching mode to form a second region, depositing barrier metal on the second region to form a Schottky barrier metal layer, and depositing N type body region contact layer, the second gate oxide layer and the insulating medium layer after the deposition is finished to form a Schottky barrier metal layer2Carrying out high-temperature annealing in the atmosphere; step 12: depositing metal titanium on the first area and the second area to form an ohmic contact metal layer; step 13: and growing Al on the ohmic contact metal layer and the insulating medium layer to form front metal.
Preferably, the first ions are boron ions, the implantation times of the first ions are multiple times, and the single implantation dose is 2 × 1013-1×1014ion/CM2Cumulative implant dose of 1X 1014-5×1014ion/CM2The implantation energy is 50Kev-1.5Mev, and the implantation depth is 1 μm-2.5 μm.
Preferably, the second ions are phosphorus ions, and the implantation dose of the second ions is 3 × 1015-2×1016ion/CM2The implantation energy is 150Kev-500Kev, and the implantation depth isThe degree is 0.3-0.5 μm.
Preferably, the P + source electrode and the P type body region are advanced at high temperature, wherein the temperature of the advanced high temperature is 1700-1900 ℃, and the time of the advanced high temperature is 60-300 min.
Preferably, the depth of the groove is 1-4 μm, the width is 0.4-1 μm, and the bottom of the groove needs to be smoothed after the groove is etched and etched.
Preferably, the third ions are boron ions, and the implantation dose is 1 × 1013-1×1014ion/CM2The implantation energy is 30-80 Kev.
Preferably, the time of the rapid thermal oxidation mode is 30S-2min, and the thickness of the single rapid thermal oxidation is less thanCumulative rapid thermal oxidation thickness greater than
Preferably, the furnace tube thermal oxidation mode adopts CL-based gas, and the thickness of the second oxidation layer formed by the furnace tube thermal oxidation mode is 0.04-0.1 μm.
Preferably, the impurity concentration of the polycrystalline silicon is 1 × 1020ion/CM3Above, the thickness of the polysilicon is
Preferably, the fourth ion is implanted at an energy of 50 to 150Kev and at an implant dose of 1X 1013-5×1013ion/CM2。
Preferably, the implantation energy of the fifth ions is 300-800Kev, and the implantation dose is 2 × 1013-2×1014ion/CM2。
Preferably, after the deposition of the ohmic contact metal layer is finished, high-temperature annealing is carried out, wherein the annealing temperature is 900-1100 ℃.
Has the advantages that:
compared with the prior art, the invention has the main advantages that:
(1) the schottky diode is integrated into the MOSFET device by a unique design. And the current and specification of the MOSFET and the Schottky diode can be adjusted and adapted by flexibly increasing and decreasing the area of the Schottky barrier metal layer. Therefore, the functions of increasing the switching speed of the MOSFET, reducing the switching loss and the like are achieved, the performance and the reliability of the device can be greatly improved, and the application cost of the device is reduced.
(2) The design of the groove type SiC MOSFET is adopted, and a conductive channel is changed from the traditional horizontal direction to the vertical direction, so that the JFET effect among the cells of the traditional MOSFET is eliminated, and the current capacity of the device is improved. A JFET area of a traditional MOS is ingeniously converted into a Schottky area, and the effects of protecting devices and improving the performance are achieved.
(3) Ohmic contact and Schottky contact are separately manufactured through a Lift-off process, and the optimal characteristics of the two contacts (ohmic contact and Schottky contact) can be respectively debugged on the premise of not additionally increasing a photoetching plate.
(4) The gate bottom P region at the bottom of the trench can protect and weaken the electric field at the bottom of the trench, plays a certain role in electrostatic shielding of the gate oxide at the bottom of the trench, and improves the reliability of the device. Meanwhile, the voltage resistance of the device is also helped to a certain extent.
(5) The Schottky barrier metal layer is etched by adopting ICP plasma coupling with dominant chemistry, so that interface damage can be reduced. And dry etching can remove surface SiO by etching2The Schottky device comprises a material, a gate oxide layer and a P-type body region contact layer, so that an interface state caused by an oxidation step and an ion implantation step is removed, and the performance of the Schottky device is finally improved.
(6) The P-type impurity injection below the contact holes of the N + source and the P-type body region can reduce Pbase resistance (P-based resistance), and can effectively improve the anti-surge capability of the device. The implantation step also does not need to add an additional mask.
Drawings
Fig. 1 is a schematic structural diagram of an enhanced silicon carbide MOSFET device according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of an enhanced silicon carbide MOSFET device in accordance with an embodiment of the present invention;
FIG. 3 is a schematic view of a device structure including an N + type heavily doped SiC substrate and an N-epitaxial layer in an embodiment of the present invention;
FIG. 4 is a schematic diagram of a device structure including a P-type body region according to an embodiment of the present invention;
FIG. 5 is a schematic diagram of a device structure including N + source formed in an embodiment of the present invention;
FIG. 6 is a schematic diagram of a device structure including a trench in an embodiment of the present invention;
FIG. 7 is a schematic diagram of a device structure including a gate bottom P region according to an embodiment of the present invention;
FIG. 8 is a schematic diagram of a device structure including a gate oxide layer in an embodiment of the invention;
fig. 9 is a schematic diagram of a device structure including a polysilicon gate in an embodiment of the invention;
FIG. 10 is a schematic diagram of a device structure with surface polysilicon etched away according to an embodiment of the present invention;
FIG. 11 is a schematic diagram of a device structure including a P-type body region contact layer in an embodiment of the invention;
FIG. 12 is a schematic diagram of a device structure including a layer of insulating dielectric in an embodiment of the invention;
FIG. 13 is a schematic diagram of a device structure including a channel in an embodiment of the invention;
fig. 14 is a schematic view of a device structure including a P + buried layer in an embodiment of the present invention;
FIG. 15 is a schematic structural diagram of a device etched by a dry etching method in the embodiment of the present invention;
FIG. 16 is a schematic diagram of a device structure including a Schottky barrier metal layer in an embodiment of the present invention;
fig. 17 is a schematic diagram of a device structure including an ohmic contact metal layer and a front side metal in an embodiment of the invention.
The structure comprises a back metal 1, an N + type heavily doped SiC substrate 2, an N-epitaxial layer 3, a P type body region 4, an N + source electrode 5, a groove 6, a gate oxide layer 7, a polysilicon gate 8, a P type body region contact layer 9, a P + buried layer 10, an insulating dielectric layer 11, a Schottky barrier metal layer 12, an ohmic contact metal layer 13, a front metal 14 and a gate bottom P region 15.
Detailed Description
The content of the invention will now be discussed with reference to a number of exemplary embodiments. It is to be understood that these examples are discussed only to enable those of ordinary skill in the art to better understand and thus implement the teachings of the present invention, and are not meant to imply any limitations on the scope of the invention.
As used herein, the term "include" and its variants are to be read as open-ended terms meaning "including, but not limited to. The term "based on" is to be read as "based, at least in part, on". The terms "one embodiment" and "an embodiment" are to be read as "at least one embodiment". The term "another embodiment" is to be read as "at least one other embodiment".
The invention provides an enhanced silicon carbide MOSFET device and a manufacturing method thereof, aiming at the problems that in the prior art, a reverse bias diode is connected in parallel between a source electrode and a channel, the starting voltage of the device can be improved, and the current driving capability of the device can be reduced. The device is a groove type MOSFET device, as shown in figure 2, the parallel connection SiC Schottky device is arranged in the device, so that the switching speed of the device is accelerated, the switching loss is reduced, the current driving capability of the device is improved, and the overall reliability of the device is improved. An enhanced silicon carbide MOSFET device comprising, in order from bottom to top:
the back metal 1 is formed by combining metal Ti, metal Ni and metal Ag, and the back of the SiC substrate needs to be ground and thinned before the metal is deposited on the back of the SiC substrate; annealing of the device as a whole is required after the back metal 1 deposition.
As shown in fig. 3, the heavily doped N + SiC substrate 2 may be 2H SiC substrate or 4H SiC substrate, and the doping concentration of the heavily doped N + SiC substrate is about 3 × 1019-3×1020ion/CM3。
An N-epitaxial layer 3 with a doping concentration of 1X 1015-1×1016ion/CM3The thickness is 10-30 μm, and the doped impurity is nitrogen element. As shown in fig. 4, the upper surface of N-epitaxial layer 3 includes a plurality of P-type body regions arranged in parallel and at intervals in the horizontal direction, and the number of the P-type body regions is not limited and may be arranged according to the size of the device. The P type body region 4 is formed by injecting first ions downwards on the upper surface of the N-epitaxial layer 3 in a photoetching and ion injection mode, the first ions are preferably boron ions, and the depth of the P type body region 4 is 1-3 mu m.
As shown in fig. 5, the central region of the upper surfaces of at least three P type body regions 4 includes an N + source 5, the N + source 5 is formed by etching and implanting second ions, preferably phosphorus ions, into the central region of the upper surfaces of the P type body regions 4 by photolithography and ion implantation, and the depth of the N + source 5 is 0.2-0.8 μm.
As shown in fig. 6, the central region of the N + source 5 includes a trench 6, the trench 6 is formed by etching downwards in the central region of the upper surface of the N + source 5 by means of trench lithography and trench etching, the depth of the trench 6 is 1.2-1.5 times of the depth of the P-type body region, the depth is 1-4 μm, and the width is 0.4-1 μm.
As shown in fig. 7, the trench 6 includes a gate bottom P region 15, and the gate bottom P region 15 is formed by implanting third ions, preferably boron ions, downward at the bottom of the trench 6 by means of ion implantation; the groove 6 also comprises a polysilicon grid 8, the polysilicon grid 8 is filled in the whole groove in an injection mode, and the doping concentration of polysilicon is more than 1 multiplied by 1020ion/CM3(ii) a As shown in fig. 8, the trench 6 and the N-epitaxial layer further include a gate oxide layer 7, the gate oxide layer 7 is grown on the upper surface of the N-epitaxial layer 3 and the inner wall of the trench 6 in a furnace tube thermal oxidation manner, and the thickness of the gate oxide layer 7 is 0.04-0.1 μm.
As shown in fig. 11, the upper surface of the N-epitaxial layer 3 further includes a P-type body region contact layer 9, the P-type body region contact layer 9 is formed by implanting fourth ions, preferably boron ions, below the gate oxide layer 7 by means of ion implantation;
as shown in fig. 14, the P type body region 4 further includes a P + buried layer 10, the P + buried layer 10 is formed by implanting fifth ions, preferably boron ions, downward on the upper surface of the P type body region 4 by means of ion implantation, and the implantation depth of the P + buried layer 10 is 0.4-0.6 times the depth of the P type body region 4;
as shown in fig. 12, an insulating dielectric layer 11, the insulating dielectric layer 11 being composed of SiO 2; the insulating medium layer 11 comprises a Schottky barrier metal layer 12 and an ohmic contact metal layer 13; as shown in fig. 16, a schottky barrier metal layer 12 is deposited on the upper surface of the N-epitaxial layer 3 by photolithography and etching and contacts the N-epitaxial layer 3, the schottky barrier metal layer 12 is disposed between the P-type body regions 4; as shown in fig. 17, the ohmic contact metal layer 13 is disposed in the insulating dielectric layer 11 at a position where no SiO2 is present; the thickness of the insulating dielectric layer 11 isThe Schottky barrier metal layer 12 is TiMo or TiW, and the thickness of the Schottky barrier metal layer 12 isThe ohmic contact metal layer 13 is Ti with a thickness of
As shown in fig. 17, the front metal 14 is composed of Al and has a thickness of 1 to 5 μm.
The invention discloses a preparation method of an enhanced silicon carbide MOSFET device, which comprises the following steps:
step 1: selecting an N + type heavily doped SiC substrate 2, and growing an N-epitaxial layer 3 on the upper surface of the N + type heavily doped SiC substrate; the N + type heavily doped SiC substrate 2 can be a 2H SiC substrate or a 4H SiC substrate. The doping concentration of the N + type heavily doped SiC substrate 2 is about 3X 1019-3×1020ion/CM3The doping concentration of the N-epitaxial layer 3 is 1 x 1015-1×1016ion/CM3The thickness is 10-30 μm, and the doped impurity is nitrogen element. According to the doping concentration and the thickness of the N-epitaxial layer 3, the voltage resistance of about 1000-3000V can be realized.
Step 2: on the upper surface of the N-epitaxial layer 3And (3) downwards implanting first ions, preferably boron ions, by photoetching and ion implantation to form at least three P-type body regions 4 which are arranged in parallel at intervals in the horizontal direction, wherein the implantation is performed for multiple times, and the implantation depth of each time is different, so that impurities at each position in the vertical direction are uniformly distributed. Preferably, the number of injections is 3-5. The single injection dose is 2 x 1013-1×1014Ion/cm2In the meantime. The cumulative implantation dose is 1 × 1014-5×1014Ion/cm2In the meantime. The implantation energy is 50Kev-1.5Mev, and the energy gradients of all stages are consistent. The implantation depth is between 1um-2.5um from the surface to the bottom. Forming an N + source 5 by implanting second ions, which are phosphorus ions, downward in the central region of the upper surface of the P-type body region 4, preferably at a dose of 3 × 1015-2×1016ion/CM2In the meantime. The depth of the implanted junction is between 0.3 μm and 0.5 μm, and the implantation energy is between 150 and 500 kev. Then, the N + source 5 and the P-type body 4 are advanced at a high temperature, wherein the advancing temperature is 1700-1900 ℃, and the advancing time is 60-300 min. After the push-in is finished, the junction depth of the P type body region is 1-3 mu m, and the junction depth of the N type source region is 0.2-0.8 mu m.
And step 3: photoresist is coated on the other areas of the upper surface of the N-epitaxial layer 3 except the central area of the N + source electrode 5, a groove 6 is formed in the central area by means of groove photoetching and groove etching, the depth of the groove 6 is 1.2-1.5 times of the depth of the P type body area 4, and the etching gas is preferably F-based gas, such as CF4, C2F6, CHF3 and the like. And after the etching is finished, the bottom of the groove 6 is subjected to smooth treatment, so that the bottom of the groove 6 is smoother, an electric field at the bottom of the groove 6 can be weakened, and the surface states of SiC and oxide at the bottom are reduced.
And 4, step 4: injecting third ions downwards at the bottom of the groove 6 in an ion injection mode to form a grid bottom P region, wherein the third ions are preferably boron ions; the implantation dose is 1 × 1013-1×1014ion/CM2The implantation energy is 30-80 Kev. And after the injection is finished, removing the photoresist. The third ions injected in the step 4 can participate in depletion when the device is reversely biased, and the effect of weakening the electric field at the bottom of the gate oxide is achieved, so that the tolerance of the device can be improvedAnd (4) pressing and reliability.
And 5: as shown in fig. 8, a first gate oxide layer is grown on the upper surface of the N-epitaxial layer 4 and the inner wall of the trench 6 by multiple rapid thermal oxidation. The multiple rapid thermal oxidation is preferably performed 5-10 times, and the multiple rapid thermal oxidation increases the manufacturing cost of the device. Then stripping the first gate oxide layer by a wet etching mode, and then forming a second gate oxide layer 7 on the upper surface of the N-epitaxial layer and the inner wall of the groove by a furnace tube thermal oxidation mode; the time of the rapid thermal oxidation mode is usually 30s-2min, and the thickness of the single thermal oxidation isWithin. Cumulative thermal oxide thickness ofThe above. The inner walls of the grooves 6 are eventually made smoother and less interface states. And then growing a gate oxide layer 7 by adopting a furnace tube thermal oxidation method, wherein CL-based gas can be introduced for oxidation in order to further improve the gate oxide quality. The final oxide layer thickness is between 0.04-0.1 μm. During the oxidation process, the third ions at the bottom are activated.
Step 6: as shown in FIG. 9, polysilicon is deposited on the upper surface of the N-epitaxial layer 3 and in the trenches to form polysilicon gates 7, the polysilicon having an impurity concentration of 1X 1020ion/CM3Above, the thickness of the polysilicon is withinMeanwhile, as shown in fig. 10, the polysilicon on the upper surface of the N-epitaxial layer is etched by a CMP process;
and 7: as shown in fig. 11, fourth ions are implanted on the upper surface of the N-epitaxial layer 3 below the second gate oxide layer 7 to form a P-type body region contact layer 9, the fourth ions are preferably boron ions, the implantation energy is based on just penetrating through the gate oxide film, and the optimized energy is about 50-150 Kev; the implantation dose is 1 × 1013-5×1013ion/CM2In the meantime. The fourth ions can make the surface concentration of the P-type body region 4 more concentrated, and make ohmic contact easier to form in the subsequent process. In addition, theThe N + source 5 and the polysilicon gate 8 are still N-type since the N-type impurity concentration is much higher than the P-type impurity concentration.
And 8: as shown in fig. 12, an insulating dielectric layer 10 is grown on the upper surface of the gate oxide layer 7, and the insulating dielectric layer 10 is composed of SiO 2; the growth mode adopts LPCVD (low pressure chemical vapor deposition), and the thickness of the dielectric layer is withinIn the meantime.
And step 9: as shown in fig. 13, at least six channels are formed by etching the insulating dielectric layer 10 through photolithography and etching, the channels lead to the upper surface of the P-type body region 4 and the upper surface of the N + source 5, and the region formed by the six channels is the first region.
Step 10: as shown in fig. 14, implanting fifth ions on the upper surface of the P-type body region 4 to which the channel leads by ion implantation to form a P + buried layer; preferably, the fifth ions are boron ions; the implantation depth of the fifth ions is 0.4-0.6 times of the depth of the P type body region 4 and is deeper than the N + source electrode 5; the implantation energy is between 300 and 800Kev, and the implanted impurity dose is 2 x 1013-2×1014ion/CM2In the meantime. The fifth ions injected in the step can reduce the internal resistance of the base region, so that the parasitic NPN triode is prevented from being started, the EAS resistance of the device is improved, the reliability of the device is improved, and the voltage capability and the current capability of the MOSFET cannot be influenced because the P + buried layer 10 has a certain distance from the vertical conducting channel.
Step 11: as shown in fig. 15, the second region is formed by etching through the P-type body region contact layer 9, the second gate oxide layer and the insulating dielectric layer 10 above the region between the P-type body regions 4 by means of dry etching. The dry etching method comprises the following steps: the insulating medium layer 10 is etched in an EOP mode, gaseous byproducts are generated in the EOP mode when dry plasma etching is carried out, the generated byproducts are different when different materials are etched, and when one material is etched, the signal strength of the byproducts is detected through a sensor, so that the etching completion can be known. After the etching in the EOP mode is finished, etching the oxide layer 7 and the contact layer of the P type body region by adopting an ICP machine coupled by plasma9, the general etching depth is within 0.5 um. As shown in FIG. 16, a barrier metal is deposited on the second region to form a Schottky barrier metal layer 12, and after the deposition is completed, N is added2And carrying out high-temperature annealing in the atmosphere.
Step 12: as shown in fig. 17, titanium metal is deposited on the first and second regions to form an ohmic contact metal layer 13.
Step 13: as shown in fig. 17, Al is grown over the ohmic contact metal layer and the insulating dielectric layer to form a front metal.
Although embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that changes, modifications, substitutions and alterations can be made in these embodiments without departing from the principles and spirit of the invention, the scope of which is defined in the appended claims and their equivalents.
Claims (22)
1. An enhanced silicon carbide MOSFET device, comprising:
the upper surface of the N-epitaxial layer comprises a plurality of P-type body regions which are arranged in parallel at intervals in the horizontal direction, the P-type body regions are formed downwards on the upper surface of the N-epitaxial layer and comprise first ions, and the P-type body regions are connected through Schottky barrier metal layers;
a central region of the at least three P-type body region upper surfaces includes an N + source formed downward in the P-type body region upper surface central region, the N + source including second ions;
a groove is arranged below the central region of the N + source electrode, and the depth of the groove is deeper than the P-type body region but is not in contact with the N + type heavily doped SiC substrate; the groove comprises a gate bottom P region, the gate bottom P region is arranged at the bottom of the groove and comprises third ions;
the groove also comprises a polysilicon grid, and the polysilicon grid is filled in the whole groove; the N-epitaxial layer and the groove also comprise a gate oxide layer, and the gate oxide layer grows on the inner wall of the groove;
the outer side of the N + source electrode on the upper surface of the P type body region also comprises a P type body region contact layer, the P type body region contact layer is formed on the upper surface of the P type body region in a downward arrangement mode, and the P type body region contact layer comprises fourth ions;
the P-type body region further comprises a P + buried layer, the P + buried layer is arranged in the center of the P-type body region and outside the groove, and the P + buried layer comprises fifth ions; and an ohmic contact metal layer is arranged above the N + source electrode, the P-type body region contact layer and the Schottky barrier metal layer.
2. The device of claim 1, wherein the device, in order from top to bottom, is:
a back metal formed from a combination of metal Ti, metal Ni, and metal Ag; an N + type heavily doped SiC substrate; the N-epitaxial layer; an insulating medium layer made of SiO2Composition is carried out; the insulating medium layer is arranged above the polycrystalline silicon grid electrode and the P-type body region contact layer;
a front metal consisting of Al and having a thickness of 1-5 μm.
3. The device according to claim 2, wherein the silicon carbide single crystal material used for the silicon carbide substrate is one of a 2H-SiC single crystal and a 4H-SiC single crystal, and the doping concentration of the N + -type heavily doped SiC substrate is 3 x 1019-3×1020ion/CM3。
4. The device of claim 1, wherein the N-epitaxial layer has a doping concentration of 1 x 1015-1×1016ion/CM3The thickness is 10-30 μm, and the doped impurity is nitrogen element.
5. The device of claim 1, wherein the P-type body region has a depth of 1-3 μm, the first ions are boron ions, the N + source region has a depth of 0.2-0.8 μm, and the second ions are phosphorous ions.
6. The device of claim 1, wherein the third, fourth, and fifth ions are boron ions.
7. The device of claim 1 wherein said polysilicon has a doping concentration greater than 1 x 1020ion/CM3。
8. The device of claim 1 wherein said gate oxide layer has a thickness of 0.04-0.1 μm.
10. A method of fabricating an enhanced silicon carbide MOSFET device, comprising:
step 1: selecting an N + type heavily doped SiC substrate, and growing an N-epitaxial layer on the upper surface of the N + type heavily doped SiC substrate;
step 2: first ions are downwards implanted into the upper surface of the N-epitaxial layer in a photoetching and ion implantation mode to form at least three P-type body regions which are arranged in parallel at intervals in the horizontal direction, and second ions are downwards implanted into the central regions of the upper surfaces of the at least three P-type body regions in an ion implantation mode to form an N + source electrode;
and step 3: etching a groove downwards in the central area of the N + source electrode in a groove photoetching and groove etching mode, wherein the depth of the groove is deeper than the P-type body region but is not contacted with the N + type heavily doped SiC substrate;
and 4, step 4: injecting third ions downwards at the bottom of the groove in an ion injection mode to form a grid bottom P region;
and 5: growing a first gate oxide layer on the upper surface of the N-epitaxial layer and the inner wall of the groove by a rapid thermal oxidation mode for 5-10 times, stripping the first gate oxide layer by a wet etching mode, and then forming a second gate oxide layer on the upper surface of the N-epitaxial layer and the inner wall of the groove by a furnace tube thermal oxidation mode;
step 6: depositing polycrystalline silicon on the upper surface of the N-epitaxial layer and in the groove, and etching the polycrystalline silicon on the upper surface of the N-epitaxial layer through a CMP (chemical mechanical polishing) process;
and 7: injecting fourth ions into the upper surface of the N-epitaxial layer below the second gate oxide layer to form a P-type body region contact layer;
and 8: growing an insulating medium layer on the upper surface of the second gate oxide layer, wherein the insulating medium layer is made of SiO2Composition is carried out;
and step 9: etching the insulating medium layer by photoetching and etching modes to form at least six channels, wherein the channels lead to the upper surface of the P-type body region and the upper surface of the N + source electrode, and the region formed by the at least six channels is a first region;
step 10: implanting fifth ions on the upper surface of the P-type body region to which the channel leads in an ion implantation mode to form a P + buried layer, wherein the implantation depth of the fifth ions is 0.4-0.6 times of the depth of the P-type body region;
step 11: etching through the P type body region contact layer, the second gate oxide layer and the insulating medium layer above the regions among the P type body regions in a dry etching mode to form a second region, depositing barrier metal on the second region to form a Schottky barrier metal layer, and depositing N type body region contact layer, the second gate oxide layer and the insulating medium layer after the deposition is finished to form a Schottky barrier metal layer2Carrying out high-temperature annealing in the atmosphere;
step 12: depositing metal titanium on the first area and the second area to form an ohmic contact metal layer;
step 13: and growing Al on the ohmic contact metal layer and the insulating medium layer to form front metal.
11. The method of claim 10, wherein the first ions are boron ions, the number of times of implantation of the first ions is 3-5, and the single implantation dose is 2 x 1013-1×1014ion/CM2Cumulative implant dose of 1X 1014-5×1014ion/CM2The implantation energy is 50Kev-1.5Mev, and the implantation depth is 1 μm-2.5 μm.
12. The method of claim 10, wherein the second ions are phosphorus ions and the implantation dose of the second ions is 3 x 1015-2×1016ion/CM2The implantation energy is 150Kev-500Kev, and the implantation depth is 0.3 μm-0.5 μm.
13. The method as claimed in claim 10, wherein the P + source and the P-type body region are advanced at 1700-1900 ℃ for 60-300 min.
14. The method of claim 10, wherein the trench has a depth of 1-4 μm and a width of 0.4-1 μm, and wherein the bottom of the trench is rounded after the trench lithography and trench etching.
15. The method of claim 10, wherein the third ions are boron ions and the implant dose is 1 x 1013-1×1014ion/CM2The implantation energy is 30-80 Kev.
17. The method according to claim 10, wherein the furnace thermal oxidation method uses a CL-based gas, and a thickness of the second oxide layer formed by the furnace thermal oxidation method is 0.04 to 0.1 μm.
19. The method of claim 10, wherein the fourth ion is implanted at an energy of 50 to 150Kev and at an implant dose of 1 x 1013-5×1013ion/CM2。
21. The method as claimed in claim 10, wherein the implantation energy of the fifth ions is 300-800Kev, and the implantation dose is 2 x 1013-2×1014ion/CM2。
22. The method as claimed in claim 10, wherein the ohmic contact metal layer is deposited and then annealed at a high temperature of 900-1100 ℃.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201911258411.XA CN111081759B (en) | 2019-12-10 | 2019-12-10 | Enhanced silicon carbide MOSFET device and manufacturing method thereof |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201911258411.XA CN111081759B (en) | 2019-12-10 | 2019-12-10 | Enhanced silicon carbide MOSFET device and manufacturing method thereof |
Publications (2)
Publication Number | Publication Date |
---|---|
CN111081759A true CN111081759A (en) | 2020-04-28 |
CN111081759B CN111081759B (en) | 2022-07-15 |
Family
ID=70313538
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201911258411.XA Active CN111081759B (en) | 2019-12-10 | 2019-12-10 | Enhanced silicon carbide MOSFET device and manufacturing method thereof |
Country Status (1)
Country | Link |
---|---|
CN (1) | CN111081759B (en) |
Cited By (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN112417729A (en) * | 2020-11-23 | 2021-02-26 | 复旦大学 | Ant colony algorithm-based SiC MOSFET packaging structure optimization method |
CN112992895A (en) * | 2021-01-27 | 2021-06-18 | 复旦大学 | Preparation method of GaN-based switch integrated unit and GaN-based switch tube wafer structure |
CN113725077A (en) * | 2021-08-31 | 2021-11-30 | 江苏东海半导体科技有限公司 | Schottky barrier device and method of forming the same |
CN114784108A (en) * | 2022-04-21 | 2022-07-22 | 电子科技大学 | Planar gate SiC MOSFET (silicon carbide metal oxide semiconductor field effect transistor) integrated with junction barrier Schottky diode and manufacturing method thereof |
CN115132726A (en) * | 2022-09-02 | 2022-09-30 | 深圳芯能半导体技术有限公司 | Structure and manufacturing method of fast recovery power device and electronic equipment |
CN115172445A (en) * | 2022-09-02 | 2022-10-11 | 深圳芯能半导体技术有限公司 | Structure and manufacturing method of fast recovery power device and electronic equipment |
CN116825780A (en) * | 2023-08-31 | 2023-09-29 | 深圳平创半导体有限公司 | Semiconductor device and method for manufacturing the same |
Citations (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20080029812A1 (en) * | 2005-02-11 | 2008-02-07 | Alpha & Omega Semiconductor, Ltd | Planar SRFET using no additional masks and layout method |
US20110291186A1 (en) * | 2010-06-01 | 2011-12-01 | Hamza Yilmaz | Semiconductor power devices manufactured with self-aligned processes and more reliable electrical contacts |
CN102364688A (en) * | 2011-11-09 | 2012-02-29 | 电子科技大学 | Vertical double-diffusion metal oxide semiconductor field effect transistor (MOSFET) |
US20130256698A1 (en) * | 2010-08-02 | 2013-10-03 | Microsemi Corporation | Low loss sic mosfet |
CN104425246A (en) * | 2013-08-27 | 2015-03-18 | 无锡华润上华半导体有限公司 | Insulated gate bipolar transistor and preparation method thereof |
CN105047721A (en) * | 2015-08-26 | 2015-11-11 | 国网智能电网研究院 | Silicon carbide trench gate power metal-oxide-semiconductor field effect transistors (MOSFETs) device and manufacturing method thereof |
CN109065540A (en) * | 2018-08-06 | 2018-12-21 | 中国科学院半导体研究所 | A kind of structure and preparation method of the SiC UMOSFET of integrated SBD |
CN110534559A (en) * | 2019-09-03 | 2019-12-03 | 深圳第三代半导体研究院 | A kind of sic semiconductor device terminal and its manufacturing method |
-
2019
- 2019-12-10 CN CN201911258411.XA patent/CN111081759B/en active Active
Patent Citations (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20080029812A1 (en) * | 2005-02-11 | 2008-02-07 | Alpha & Omega Semiconductor, Ltd | Planar SRFET using no additional masks and layout method |
US20110291186A1 (en) * | 2010-06-01 | 2011-12-01 | Hamza Yilmaz | Semiconductor power devices manufactured with self-aligned processes and more reliable electrical contacts |
US20130256698A1 (en) * | 2010-08-02 | 2013-10-03 | Microsemi Corporation | Low loss sic mosfet |
CN102364688A (en) * | 2011-11-09 | 2012-02-29 | 电子科技大学 | Vertical double-diffusion metal oxide semiconductor field effect transistor (MOSFET) |
CN104425246A (en) * | 2013-08-27 | 2015-03-18 | 无锡华润上华半导体有限公司 | Insulated gate bipolar transistor and preparation method thereof |
CN105047721A (en) * | 2015-08-26 | 2015-11-11 | 国网智能电网研究院 | Silicon carbide trench gate power metal-oxide-semiconductor field effect transistors (MOSFETs) device and manufacturing method thereof |
CN109065540A (en) * | 2018-08-06 | 2018-12-21 | 中国科学院半导体研究所 | A kind of structure and preparation method of the SiC UMOSFET of integrated SBD |
CN110534559A (en) * | 2019-09-03 | 2019-12-03 | 深圳第三代半导体研究院 | A kind of sic semiconductor device terminal and its manufacturing method |
Non-Patent Citations (1)
Title |
---|
李晓云 等: "SiC-AlN复相陶瓷材料的无压烧结和导热性能", 《真空电子技术》 * |
Cited By (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN112417729A (en) * | 2020-11-23 | 2021-02-26 | 复旦大学 | Ant colony algorithm-based SiC MOSFET packaging structure optimization method |
CN112417729B (en) * | 2020-11-23 | 2023-04-18 | 复旦大学 | Ant colony algorithm-based SiC MOSFET packaging structure optimization method |
CN112992895B (en) * | 2021-01-27 | 2023-01-24 | 复旦大学 | Preparation method of GaN-based switch integrated unit and GaN-based switch tube wafer structure |
CN112992895A (en) * | 2021-01-27 | 2021-06-18 | 复旦大学 | Preparation method of GaN-based switch integrated unit and GaN-based switch tube wafer structure |
CN113725077A (en) * | 2021-08-31 | 2021-11-30 | 江苏东海半导体科技有限公司 | Schottky barrier device and method of forming the same |
CN113725077B (en) * | 2021-08-31 | 2022-08-05 | 江苏东海半导体股份有限公司 | Schottky barrier device and method of forming the same |
CN114784108A (en) * | 2022-04-21 | 2022-07-22 | 电子科技大学 | Planar gate SiC MOSFET (silicon carbide metal oxide semiconductor field effect transistor) integrated with junction barrier Schottky diode and manufacturing method thereof |
CN114784108B (en) * | 2022-04-21 | 2023-05-05 | 电子科技大学 | Planar gate SiC MOSFET integrated with junction barrier Schottky diode and manufacturing method thereof |
CN115132726B (en) * | 2022-09-02 | 2022-11-29 | 深圳芯能半导体技术有限公司 | Structure and manufacturing method of fast recovery power device and electronic equipment |
CN115172445B (en) * | 2022-09-02 | 2022-11-29 | 深圳芯能半导体技术有限公司 | Structure and manufacturing method of fast recovery power device and electronic equipment |
CN115172445A (en) * | 2022-09-02 | 2022-10-11 | 深圳芯能半导体技术有限公司 | Structure and manufacturing method of fast recovery power device and electronic equipment |
CN115132726A (en) * | 2022-09-02 | 2022-09-30 | 深圳芯能半导体技术有限公司 | Structure and manufacturing method of fast recovery power device and electronic equipment |
CN116825780A (en) * | 2023-08-31 | 2023-09-29 | 深圳平创半导体有限公司 | Semiconductor device and method for manufacturing the same |
CN116825780B (en) * | 2023-08-31 | 2023-10-31 | 深圳平创半导体有限公司 | Semiconductor device and method for manufacturing the same |
Also Published As
Publication number | Publication date |
---|---|
CN111081759B (en) | 2022-07-15 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN111081759B (en) | Enhanced silicon carbide MOSFET device and manufacturing method thereof | |
JP3413250B2 (en) | Semiconductor device and manufacturing method thereof | |
CN105097894A (en) | Semiconductor device | |
KR20010112238A (en) | Power mos element and method for producing the same | |
US9443926B2 (en) | Field-stop reverse conducting insulated gate bipolar transistor and manufacturing method therefor | |
KR101955055B1 (en) | Power semiconductor device and method of fabricating the same | |
US6800509B1 (en) | Process for enhancement of voltage endurance and reduction of parasitic capacitance for a trench power MOSFET | |
CN103477439A (en) | Semiconductor device and process for production thereof | |
CN114975602A (en) | High-reliability IGBT chip and manufacturing method thereof | |
CN112382655B (en) | Wide bandgap power semiconductor device and preparation method thereof | |
CN110600537A (en) | Separation gate CSTBT with PMOS current clamping and manufacturing method thereof | |
US20230261073A1 (en) | Semiconductor power devices having multiple gate trenches and methods of forming such devices | |
JP2000269487A (en) | Semiconductor device and its manufacture | |
CN111211168A (en) | RC-IGBT chip and manufacturing method thereof | |
WO2018000223A1 (en) | Insulated gate bipolar transistor structure and manufacturing method therefor | |
CN114497201A (en) | Field effect transistor of integrated body relay diode, preparation method thereof and power device | |
JP2005191241A (en) | Semiconductor device and method for manufacturing the same | |
CN115117151B (en) | IGBT chip with composite cellular structure and manufacturing method thereof | |
WO2023249847A1 (en) | Gate trench power semiconductor devices having trench shielding patterns formed during the well implant and related methods | |
CN116387154A (en) | Carrier storage groove type bipolar transistor structure and manufacturing method thereof | |
CN114068721B (en) | Double-trapezoid-groove protection trapezoid-groove silicon carbide MOSFET device and manufacturing method thereof | |
KR102217856B1 (en) | Method of forming shield under trench gate | |
CN114361242A (en) | Planar silicon carbide MOSFET (Metal-oxide-semiconductor field Effect transistor) capable of adjusting threshold voltage and preparation method thereof | |
CN113437142A (en) | Trench type IGBT structure and manufacturing method thereof | |
CN110931548A (en) | Semiconductor device structure and manufacturing method thereof |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
PB01 | Publication | ||
PB01 | Publication | ||
SE01 | Entry into force of request for substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
GR01 | Patent grant | ||
GR01 | Patent grant | ||
TR01 | Transfer of patent right | ||
TR01 | Transfer of patent right |
Effective date of registration: 20230426 Address after: No. 1088, Xueyuan Avenue, Taoyuan Street, Nanshan District, Shenzhen City, Guangdong Province Patentee after: SOUTH University OF SCIENCE AND TECHNOLOGY OF CHINA Address before: Taizhou building, No. 1088, Xueyuan Avenue, Xili University Town, Nanshan District, Shenzhen City, Guangdong Province Patentee before: SHENZHEN THIRD GENERATION SEMICONDUCTOR Research Institute |