CN110600537A - Separation gate CSTBT with PMOS current clamping and manufacturing method thereof - Google Patents
Separation gate CSTBT with PMOS current clamping and manufacturing method thereof Download PDFInfo
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- H01L29/66234—Bipolar junction transistors [BJT]
- H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
- H01L29/66333—Vertical insulated gate bipolar transistors
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- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
- H01L29/7395—Vertical transistors, e.g. vertical IGBT
- H01L29/7396—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions
- H01L29/7397—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
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- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
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- H01L29/7398—Vertical transistors, e.g. vertical IGBT with both emitter and collector contacts in the same substrate side
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Abstract
The invention belongs to the technical field of power semiconductor devices, and relates to a separation gate CSTBT with a PMOS current clamping function and a manufacturing method thereof. According to the invention, the PMOS structure is introduced on the basis of the traditional CSTBT, so that the saturation current of the device in forward conduction is effectively improved, the short-circuit safe working capacity of the device is improved, meanwhile, the influence of the N-type charge storage layer 14 on the breakdown characteristic of the device is eliminated, so that the doping concentration of the N-type charge storage layer 14 can be improved to improve the carrier distribution of the device in forward conduction, the conductivity modulation capacity of a drift region is improved, the forward conduction voltage drop of the device is reduced, in addition, the gate capacitance, especially the Miller capacitance, of the device is reduced by the L-shaped separated gate structure, the switching speed of the device is improved, and the switching loss of the device is reduced. And because the separation gate and the gate structure are integrated in the same groove, the area of the chip is saved.
Description
Technical Field
The invention belongs to the technical field of power semiconductor devices, and relates to a separation gate CSTBT with a PMOS current clamping function and a manufacturing method thereof.
Background
The Insulated Gate Bipolar Transistor (IGBT) has the advantages of a field effect transistor (MOSFET) and a bipolar crystal transistor (BJT), has the advantages of easy driving of the MOSFET, low input impedance and high switching speed, and also has the advantages of high current density of the BJT in an on state, low conduction voltage, low loss and good stability. Therefore, the high-power electronic circuit is developed into one of core electronic components in modern power electronic circuits and is widely applied to various fields of traffic, communication, household appliances and aerospace. The performance of the power electronic system is greatly improved by the application of the IGBT.
Since the eighties of the twentieth century when IGBTs were invented, IGBTs have been developed along the trends of reducing device switching losses, increasing device operating frequency, and increasing device reliability. IGBTs have been developed from the first generation of planar gate pass-through IGBTs (PT-IGBTs) to the current latest seventh generation of carrier storage IGBTs (csbt), which are made by introducing an N-type doped carrier storage layer under a P-type base region on the basis of the sixth generation of Trench field stop IGBTs (Trench FS-IGBTs). The introduction of the N-type carrier storage layer improves the carrier distribution of the drift region of the device, reduces the conduction voltage drop of the device, and optimizes the compromise relationship between the conduction voltage drop and the switching loss of the device. However, CSTBT (as shown in fig. 1) also has some problems, such as the introduction of an N-type carrier storage layer, which degrades the breakdown characteristics of the device, although the carrier distribution of the drift region is improved, and limits the application of the device in the high voltage field. Another disadvantage is that for the trench type IGBT, in order to improve the integration of the chip, the trench density is made larger, the saturation current when the conducting device is conducted in the forward direction is larger, the large saturation current deteriorates the short-circuit safe working capability, and the saturation current can be reduced by reducing the trench density, but this may cause the surface current distribution of the device to be uneven, which affects the reliability of the device.
Disclosure of Invention
In order to improve the influence of degradation of CSTBT breakdown characteristics caused by the introduction of a carrier storage layer and the defect of overlarge saturation current when the carrier storage layer is in forward conduction, the invention provides a split gate CSTBT structure with PMOS current clamping, which is shown in FIG. 2. The invention integrates a PMOS structure which takes a P-type buried layer as a source electrode, an N-type doped layer as a base region, a P-type doped layer as a drain electrode and a separation gate as a gate electrode on the basis of the CSTBT structure. The concentration of the P buried layer is adjusted to enable a drift region below the N type charge storage layer to be depleted before the N type charge storage layer is depleted, so that the N type charge storage layer is isolated, the potential of the N type charge storage layer is clamped when the device is in forward conduction, the potential on the N type charge storage layer cannot be further increased when the bias voltage of a collector of the device is further increased, and the saturation current of the device is reduced. Meanwhile, the N-type charge layer is isolated, and the N-type charge storage layer is shielded by the separation gate electrode, so that the influence of the N-type charge storage layer on the breakdown voltage of the device is eliminated, the concentration of the N-type charge storage layer can be further improved, the carrier distribution of the device in the forward conduction process is improved, the forward conduction voltage drop of the device is reduced, and the switching loss of the device is reduced. The N-type charge storage layer potential of the device is clamped, so that the conducting current of the device cannot be further increased, the purpose of reducing the saturation current of the device is achieved, the short-circuit safe working capacity of the device is improved, the Miller capacitance of the device is reduced by the L-shaped separation gate electrode, the switching speed of the device is improved, and the switching loss of the device is reduced. And because the separation gate and the gate structure are integrated in the same groove, the area of the chip is saved.
The technical scheme of the invention is as follows:
a cell structure of a split gate CSTBT structure with PMOS current clamping as shown in FIG. 2 comprises: the collector structure comprises a back collector metal 1, a P-type collector region 2, an N-type field stop layer 3 and an N-drift region 4 which are sequentially stacked from bottom to top; the upper layer of the N-drift region 4 is provided with a P-type buried layer 5 and an N-type charge storage layer 14; an N-type doped layer 6 is arranged above the P-type buried layer 5; the upper layer of the N-type doped layer 6 is provided with a P-type doped layer 7; the P-type base region 13 is arranged on the upper layer of the N-type charge storage layer 14; the upper layer of the P-type base region 13 is provided with an N + emitter region 11 and a P + emitter region 12 which are independent of each other; a groove structure is arranged above the P-type buried layer 5, on the side surface of the N-type doping layer 6, on the side surface of the P-type doping layer 7, on the side surface of the N-type charge storage layer 14, on the side surface of the P-type base region 13 and on the side surface of the N + emitter region 11, and comprises an insulating dielectric layer 105, an L-shaped separation gate electrode 91, a separation gate dielectric layer 101, a gate electrode 92, a polycrystalline silicon isolation dielectric layer 103 and a gate dielectric layer 102; a dielectric layer 104 is arranged above the polysilicon isolation dielectric layer 103, the gate electrode 92 and the gate dielectric layer 102; emitter metal 8 is arranged above the P-type doped layer 7, the separation gate dielectric layer 101, the separation gate electrode 91, the dielectric layer 104, the N + emitter region and the P + emitter region.
Further, in a split gate CSTBT with PMOS current clamping, a half cell structure is shown in fig. 3, and a schottky contact metal 15 is introduced above the P-type doped layer 7.
Further, a split gate CSTBT with PMOS current clamping has a half-cell structure as shown in FIG. 4, which is characterized in that the P-type buried layer 5 extends to the bottom of the N-type charge storage layer 14.
Further, a split gate CSTBT with PMOS current clamping structure has a half-cell structure as shown in FIG. 5, wherein the thickness of the dielectric layer 105 is larger than that of the gate dielectric layer 102
Further, a split gate CSTBT with PMOS current clamping has a half-cell structure as shown in fig. 6, and a super-junction P column 16 and a super-junction N column 17 are independent from each other above the N-type field stop layer 3 and below the P-type buried layer 5, wherein the super-junction P column 16 and the super-junction N column 17 meet the charge balance requirement.
Further, the semiconductor material of the IGBT device in the invention adopts Si, SiC, GaAs or GaN, the groove filling material adopts polycrystalline Si, SiC, GaAs or GaN, and each part can adopt the same material or different material combinations.
Furthermore, the device structure is not only suitable for IGBT devices, but also suitable for MOSFET devices, and the P-type collector region 2 on the back of the device is replaced by an N + layer.
A manufacturing method of a separation gate CSTBT with PMOS current clamping comprises the following steps:
step 1: selecting a lightly doped FZ silicon wafer with certain thickness and concentration to form an N-drift region 4;
step 2: manufacturing a terminal structure of a device on the front surface of the silicon wafer through pre-oxidation, photoetching, etching, ion implantation and high-temperature annealing processes on the surface of the silicon wafer;
and step 3: growing a field oxide layer on the surface of a silicon wafer, photoetching to obtain an active region, growing a pre-oxide layer, implanting P-type impurities by ions to obtain a P-type buried layer 5, implanting N-type impurities above the P-type buried layer 5 to obtain an N-type charge storage layer 14, and implanting P-type ions to obtain a P-type base region 13 on the N-type charge storage layer;
and 4, step 4: and depositing a protective layer on the surface of the silicon wafer, photoetching a window to perform groove silicon etching, and further etching a groove on the P-type buried layer 5. The depth of the groove is greater than that of the N-type charge storage layer 14 and less than that of the P-type buried layer 5;
and 5: growing a dielectric layer on the inner wall of the groove by oxidation, depositing polycrystalline silicon on the dielectric layer and reversely etching the redundant polycrystalline silicon on the surface;
step 6: oxidizing, photoetching and etching the polysilicon and the dielectric layer to prepare a gate groove;
and 7: oxidizing a growth medium layer in the gate trench, depositing polycrystalline silicon and reversely etching the surface polycrystalline silicon to obtain a gate electrode 92 and a separation gate electrode 91;
and 8: masking, photoetching and ion implantation of N-type impurities to obtain an N + emission region 11, and ion implantation of P-type impurities to obtain a P + emission region 12;
and step 9: depositing a dielectric layer on the front surface of the silicon wafer, etching and depositing metal to obtain emitter metal 8;
step 10: turning over the silicon wafer, reducing the thickness of the silicon wafer, injecting N-type impurities into the back of the silicon wafer, annealing to manufacture an N-type field stop layer 3 of the device, and injecting P-type impurities into the back of the N-type field stop layer 3 to form a P-type collector region;
step 11: and depositing metal on the back of the silicon wafer to obtain collector metal 1.
Further, the order of forming the trench structure and forming the N-type charge storage layer 14 and the P-type base region 13 may be exchanged;
further N-doped layers 6 and N-charge storage layers 14 may be fabricated together and P-doped layers 7 and P-base regions 13 may be fabricated together.
Further, for simplifying the description, the device structure and the manufacturing method are described by taking an N-channel IGBT device as an example, but the invention is also applicable to the manufacturing of a P-channel IGBT device.
Working principle of the invention
In the case of CSTBT, the introduction of the charge storage layer degrades the breakdown characteristics of the device, and another disadvantage is that the saturation current of the device in the forward conduction is large, which makes the short-circuit safe operation capability thereof poor, and the saturation current can be reduced by reducing the channel density of the trench NMOS, but this may cause the uneven distribution of the surface current of the device, thereby reducing the reliability of the device in operation. Therefore, the invention provides an L-shaped separation gate CSTBT with PMOS current clamping. When the device works in a blocking state, a PN junction between the P-type buried layer 5 and the N-drift region 4 bears reverse bias, the N-type charge storage layer 14 is isolated by the P-type buried layer 5, the influence of the N-type charge storage layer 14 on the breakdown characteristic of the device is shielded, and meanwhile, the influence of the N-type charge storage layer 14 on the breakdown characteristic of the device is weakened in an auxiliary mode through the L-shaped separation gate structure. When the device is conducted in the forward direction, the PMOS structure formed by the P-type buried layer 5, the N-type buried layer 6, the P-type doping 7 and the separation gate electrode 91 provides an additional path for holes, the potential of the N-type charge storage layer 14 is determined by the potential of the P-type buried layer 5, the N-type charge storage layer 14 is isolated by a drift region depletion region below the N-type charge storage layer 14 before being depleted by adjusting the concentration of the P-type buried layer 5, the potential on the N-type charge storage layer 14 is not increased along with the increase of bias voltage on the collector 1, MOS channel current of the IGBT is saturated in advance, the saturation current of the IGBT is reduced, and the short-circuit safe working capacity of the device is improved. And because the separation gate and the gate structure are integrated in the same groove, the area of the chip is saved.
The beneficial effects of the invention are as follows:
according to the invention, the PMOS structure is introduced on the basis of the traditional CSTBT, so that the saturation current of the device in forward conduction is effectively improved, the short-circuit safe working capacity of the device is improved, meanwhile, the influence of the N-type charge storage layer 14 on the breakdown characteristic of the device is eliminated, so that the doping concentration of the N-type charge storage layer 14 can be improved to improve the carrier distribution of the device in forward conduction, the conductivity modulation capacity of a drift region is improved, the forward conduction voltage drop of the device is reduced, in addition, the gate capacitance, especially the Miller capacitance, of the device is reduced by the L-shaped separated gate structure, the switching speed of the device is improved, and the switching loss of the device is reduced. And because the separation gate and the gate structure are integrated in the same groove, the area of the chip is saved.
Drawings
FIG. 1 is a diagram of a conventional CSTBT device half cell structure with a floating P region
Fig. 2 is a schematic diagram of a half-cell structure of a split gate csbt with PMOS current clamp according to embodiment 1 of the present invention;
fig. 3 is a schematic diagram of a half-cell structure of a split gate csbt with PMOS current clamp according to embodiment 2 of the present invention;
fig. 4 is a schematic diagram of a half-cell structure of a split gate csbt with PMOS current clamp according to embodiment 3 of the present invention;
fig. 5 is a schematic diagram of a half-cell structure of a split gate csbt with PMOS current clamp according to embodiment 4 of the present invention;
fig. 6 is a schematic diagram of a half-cell structure of a split gate csbt with PMOS current clamp according to embodiment 5 of the present invention;
fig. 7 is a schematic diagram of a half-cell structure of a split gate csbt with PMOS current clamp according to embodiment 6 of the present invention;
fig. 8 is a schematic diagram of a half-cell structure after forming a trench in a split gate csbt with PMOS current clamp according to embodiment 1 of the present invention;
fig. 9 is a schematic diagram of a half-cell structure after forming a trench dielectric layer by using a split gate csbt with PMOS current clamp according to embodiment 1 of the present invention;
fig. 10 is a schematic diagram of a half-cell structure after polysilicon filling of a trench of a split gate csbt with PMOS current clamping according to embodiment 1 of the present invention;
fig. 11 is a schematic diagram of a second half cell structure of a split gate csbt with PMOS current clamp formed in a gate trench according to embodiment 1 of the present invention;
fig. 12 is a schematic diagram of a half-cell structure after forming a gate dielectric layer in a gate trench of a split gate csbt with PMOS current clamp according to embodiment 1 of the present invention;
fig. 13 is a schematic diagram of a half-cell structure after polysilicon deposition in a gate trench of a split gate csbt with PMOS current clamping according to embodiment 1 of the present invention;
fig. 14 is a schematic diagram of a half-cell structure with N + and P + emitter regions formed by CSTBT ion implantation with a PMOS current clamp according to embodiment 1 of the present invention;
fig. 15 is a schematic diagram of a half-cell structure of a front side dielectric layer of a split gate csbt with PMOS current clamping according to embodiment 1 of the present invention;
fig. 16 is a schematic diagram of a half-cell structure of front side emitter metal formation of the split gate csbt with PMOS current clamping according to embodiment 1 of the present invention;
fig. 17 is a schematic diagram of a half-cell structure of a split gate csbt with PMOS current clamping on its back side to form an N-type field stop layer and a P + collector region according to embodiment 1 of the present invention;
fig. 18 is a schematic diagram of a half-cell structure of a collector metal formed on the backside of a split gate csbt with PMOS current clamping according to embodiment 1 of the present invention;
in fig. 1 to 18, 1 is a collector metal, 2 is a P + collector region, 3 is an N-type field stop layer, 4 is an N-drift region, 5 is a P-type buried layer, 6 is an N-type doped layer, 7 is a P-type doped layer, 8 is an emitter metal, 91 is a split gate electrode, 92 is a gate electrode, 101 is a split gate dielectric layer, 102 is a gate dielectric layer, 103 is a polysilicon isolation dielectric layer, 104 is a dielectric layer, 105 is a split gate dielectric layer, 11 is an N + emitter region, 12 is a P + emitter region, 13 is a P-type base region, 14 is an N-type charge storage layer, 15 is a schottky contact metal, 16 is a super-junction P column, 17 is a super-junction N column, 18 is a floating P region, and 19 is an N-type buried layer.
Detailed Description
The principle and characteristics of the present invention will be further described with reference to the accompanying drawings, and the specific embodiment of the present invention is illustrated by using an IGBT with a 1200V voltage class as an example, which is only used to explain the present invention and is not used to limit the scope of the present invention.
Example 1
A split gate CSTBT with PMOS current clamping, whose half-cell structure is shown in fig. 2, comprising: the collector structure comprises a back collector metal 1, a P-type collector region 2, an N-type field stop layer 3 and an N-drift region 4, wherein the P-type collector region 2 is positioned on and connected with the back collector metal 1; a P-type buried layer 5 located above and connected to the N-drift region 4 and an N-type charge storage layer 14 located above and connected to the N-drift region 4; the N-type doping layer 6 is positioned on the upper part of the P-type buried layer and connected with the P-type buried layer; a P-type doped layer 7 located on the upper part of the N-type doped layer 6 and connected with the N-type doped layer; a P-type base region 13 located on the upper part of the N-type charge storage layer and connected thereto; the N + emitter region 11 and the P + emitter region 12 are positioned on the upper part of the P-type base region, are independent from each other and are arranged side by side; the trench structure is positioned on the upper part of the P-type buried layer 5, the side wall of the N-type doping layer 6, the side wall of the P-type doping layer 7, the side wall of the N-type charge storage layer 14, the side wall of the P-type base region 13 and the side wall of the N + emission region 11, and comprises an L-shaped separation gate electrode 91, a separation gate dielectric layer 101, a gate electrode 92, a gate dielectric layer 102, a polycrystalline silicon isolation dielectric layer 103 and a separation gate dielectric layer 105; a dielectric layer 104 which is positioned on the upper part of the gate electrode 92, the upper part of the gate dielectric layer 102 and the upper part of the polysilicon isolation dielectric layer 103 and is connected with the gate electrode 92, the gate dielectric layer 102 and the polysilicon isolation dielectric layer 103; the emitter metal 8 is positioned on the upper part of the P-type doped region 7, the upper part of the separation gate dielectric layer 101, the upper part of the separation gate 91, the upper part of the dielectric layer 104, the N + emitting region 11 and the P + emitting region 12 and is connected with the N + emitting region 11 and the P + emitting region 12; the split gate electrode 91 is connected with the P-type doped region 7, the N-type doped region 6 and the P-type buried layer 5 through a split gate dielectric layer 101, and the split gate electrode 91 is connected with the N-type charge storage layer 14 and the N-drift region 4 through a split gate dielectric layer 105; the depth of the separation gate electrode 91 is greater than that of the N-type charge storage layer 14 and is less than or equal to that of the P-type buried layer 5; the gate electrode 92 is connected with the separation gate electrode 91 through a polysilicon isolation dielectric layer 103, the gate electrode 92 is connected with the N + emitter region 11 and the P-type base region 13 through a gate dielectric layer 102, and the depth of the gate electrode 92 is larger than that of the P-type base region 13 and smaller than that of the N-type charge storage layer 14; the P-type buried layer 5 can extend from the side edge of the groove, which is in contact with the N-type doped layer, to be flush with the interface of the groove and the N-type charge storage layer 14; the separation gate 91 is shorted to the emitter metal 1.
Example 2
A split gate CSTBT with PMOS current clamping has a half-cell structure as shown in FIG. 3. in this embodiment, a Schottky contact metal 15 is introduced above the P-type doped region 7 based on embodiment 1, and the rest of the structure is the same as that of embodiment 1.
The schottky contact metal 15 introduced in the embodiment has the same potential as the emitter metal 1, and the introduction of the schottky contact metal 15 can reduce the conduction voltage drop of the PMOS and reduce the switching loss of the device.
Example 3
A half-cell structure of a current clamping split gate CSTBT with PMOS is shown in FIG. 4. this embodiment extends a P-type buried layer 5 to the bottom of an N-type charge storage layer 14 based on embodiment 1, and the rest of the structure is the same as embodiment 1.
The purpose of extending the P-type buried layer 5 to the lower side of the N-type charge storage layer 14 in this embodiment is that when the cell mesa of the structure is enlarged, the P-type buried layer 5 can still deplete the drift region below the N-type charge storage layer 14, so that the potential of the N-type charge storage layer 14 is determined by the potential of the P-type buried layer 5, and the structure can play a role in reducing saturation current by adjusting the concentration of the P-type buried layer.
Example 4
A half-cell structure of a split gate CSTBT with PMOS current clamping is shown in FIG. 5. this embodiment increases the thickness of a split gate dielectric layer 105 based on embodiment 2, and the rest of the structure is the same as embodiment 1.
In the embodiment, the thickness of the separation gate dielectric layer 105 is increased, the phenomenon of electric field concentration at the bottom of the trench of the device in a blocking state is effectively improved, the voltage endurance of the device is improved, meanwhile, the thickness of the separation gate dielectric layer is increased, the gate capacitance of the device is reduced, the switching speed of the device is increased, and the switching loss of the device is reduced.
Example 5
Fig. 6 shows a structure diagram of a half cell of a split gate CSTBT with a PMOS current clamp, in this embodiment 1, a super junction P column 16 and a super junction N column 17 are introduced into an N-type drift region 4, the super junction P column 16 and the super junction N17 satisfy a charge balance requirement, a doping concentration of the super junction N column 17 is greater than or equal to a doping concentration of the N-drift region, and the rest of the structure is the same as that of embodiment 1.
In the embodiment, the super-junction P column 16 and the super-junction N column 17 are introduced into the drift region 4 to change one-dimensional withstand voltage in the drift region into two-dimensional withstand voltage, so that the compromise relationship between the conduction voltage drop and the breakdown voltage of the device is improved, and the performance of the device is improved.
Example 6
In the present embodiment, based on embodiment 2, by introducing the N-type buried layer 19 below the P-type buried layer 5, the doping concentration of the N-type buried layer 19 is greater than that of the N-drift 4.
In the embodiment, the N-type buried layer 19 is introduced below the P-type buried layer 5, so that an additional barrier is provided for accumulation of holes, distribution of drift and carrier concentration is improved, and conduction voltage drop of the device is reduced.
The present embodiment is illustrated by taking a 1200V voltage level split gate CSTBT with PMOS current clamp as an example, and devices with different performance parameters can be fabricated according to actual requirements based on common knowledge in the art.
Step 1: an N-type lightly doped monocrystalline silicon wafer is used as an N-drift region 4 of the device, the thickness of the selected silicon wafer is 300-600 um, and the doping concentration is 1013～1014Per cm3；
Step 2: manufacturing a terminal structure of a device on the front surface of the silicon wafer through pre-oxidation, photoetching, etching, ion implantation and high-temperature annealing processes on the surface of the silicon wafer;
and step 3: growing a field oxide layer on the surface of a silicon wafer, photoetching to obtain an active region, growing a pre-oxide layer, and implanting P-type impurities by ion implantation to obtain a P-type buried layer 5, wherein the ion implantation energy is 200-500 keV, and the implantation dosage is 1013～1014Per cm2Then, an N-type charge storage layer 14 is prepared by implanting N-type impurities above the P-type buried layer 5, the ion implantation energy is 200-400 keV, and the implantation dosage is 1013～1014Per cm2Preparing a P-type base region 13 on the N-type charge storage layer by P-type ion implantation, wherein the implantation energy of particles is 200-400 keV, and the implantation dosage is 1013～1014Per cm2；
And 4, step 4: and depositing a protective layer on the surface of the silicon wafer, photoetching a window to perform groove silicon etching, and further etching a groove on the P-type buried layer 5. The depth of the groove is greater than that of the N-type charge storage layer 14 and less than that of the P-type buried layer 5;
and 5: o at 1050-1150 deg.C2Depositing a dielectric layer on the inner wall of the groove under the atmosphere, then depositing polycrystalline silicon on the dielectric layer at 750-950 ℃, and then reversely etching the redundant polycrystalline silicon on the surface;
step 6, masking, photoetching, etching polysilicon and etching a dielectric layer to form a gate groove
And 7: o at 1050-1150 deg.C2Oxidizing a growth medium layer in the gate trench under the atmosphere, depositing polycrystalline silicon and reversely etching the surface polycrystalline silicon to obtain a gate electrode 92 and a separation gate electrode 91;
and 8: the energy of the mask, the photoetching and the ion implantation of N-type impurities is 30-60 keV, implant dose is 1015～1016Per cm2The energy of ion implantation of P-type impurity is 60-80 keV, and the implantation dosage is 1015～1016Per cm2Annealing at 900 ℃ for 20-30 minutes to obtain an N + emission region 11 and a P + emission region 12 which are in mutual contact and arranged side by side; and step 9: depositing a dielectric layer on the front surface of the silicon wafer, etching and depositing metal to obtain emitter metal 8;
step 10: turning over the silicon wafer, reducing the thickness of the silicon wafer, injecting N-type impurities into the back of the silicon wafer, annealing and manufacturing an N-type field stop layer 3 of the device, wherein the thickness of the N-type field stop layer 3 is 15-30 microns, the energy of ion injection is 1500-2000 keV, and the injection dosage is 10 keV13～1014Per cm2The annealing temperature is 1200-1250 ℃, and the time is 300-600 minutes; implanting P-type impurities into the back of the N-type field stop layer 3 to form a P-type collector region 13 with an implantation energy of 40-60 keV and an implantation dose of 1012～1013Per cm2In H2And N2Carrying out back annealing in a mixed atmosphere at the temperature of 400-450 ℃ for 20-30 minutes;
step 11: and depositing metal on the back of the silicon wafer to obtain collector metal 1.
Further, the order of forming the trench structure and forming the N-type charge storage layer 14 and the P-type base region 13 may be exchanged;
further N-doped layers 6 and N-charge storage layers 14 may be fabricated together and P-doped layers 7 and P-base regions 13 may be fabricated together.
Further, for simplifying the description, the device structure and the manufacturing method are described by taking an N-channel IGBT device as an example, but the invention is also applicable to the manufacturing of a P-channel IGBT device.
Claims (9)
1. A split gate CSTBT with PMOS current clamping, comprising: the collector structure comprises a back collector metal (1), a P-type collector region (2) positioned above the back collector metal (1), an N-type field stop layer (3) positioned above the P-type collector region (2) and an N-drift region (4) positioned above the N-type field stop layer (3); the upper layer of the N-drift region (4) is provided with a P-type buried layer (5) and an N-type charge storage layer (14), and the junction depth of the lower surface of the P-type buried layer (5) is greater than that of the lower surface of the N-type charge storage layer (14); the upper surface of the N-type charge storage layer (14) is provided with a P-type base region (13), and the upper surface of the P-type base region (13) is provided with an N + emission region (11) and a P + emission region (12) which are arranged in parallel; the buried-type-buried-layer structure is characterized in that an N-type doping layer (6) is arranged on the upper surface of the P-type buried layer (5), and a P-type doping layer (7) is arranged on; a trench gate structure is arranged among the N-type doping layer (6), the P-type doping layer (7), the N + emitter region (11), the P-type base region (13) and the N-type charge storage layer (14), and the trench gate structure also extends into the P-type buried layer (5); the P-type buried layer (5), the N-type doped layer (6) and the P-type doped layer (7) are isolated from the trench gate structure through a separation gate dielectric layer (101); a separation gate electrode (91) is surrounded in the separation gate dielectric layer (101), and the separation gate electrode (91) is isolated from the N-drift region (4) and the N-type charge storage layer (14) through a separation gate dielectric layer (105); the trench gate structure is also provided with a gate electrode (92), the gate electrode (92) is isolated from the N + emitter region (11), the P-type base region (13) and the N-type charge storage layer (14) through a gate dielectric layer (102), and the gate electrode (92) is isolated from the separation gate electrode (91) through a polysilicon isolation dielectric layer (103); emitter metal (8) covers the upper surfaces of the P-type doped layer (7), the trench gate structure, the N + emitter region (11) and the P + emitter region (12), and the gate electrode (92), the gate dielectric layer (102) and the polycrystalline silicon isolation dielectric layer (103) are isolated from the emitter metal (8) through dielectric layers (104);
the junction depth of the separation gate electrode (91) is greater than that of the N-type charge storage layer (14) and less than or equal to that of the P-type buried layer (5); the junction depth of the gate electrode (92) is larger than that of the P-type base region (13) and smaller than that of the N-type charge storage layer (14); the split gate electrode (91) is shorted to the emitter metal (8).
2. A split gate CSTBT with PMOS current clamping, comprising: the collector structure comprises a back collector metal (1), a P-type collector region (2) which is positioned on and connected with the back collector metal (1), an N-type field stop layer (3) which is positioned on and connected with the P-type collector region (2), and an N-drift region (4) which is positioned on and connected with the N-type field stop layer (3); the upper part of the N-drift region (4) is provided with a P-type buried layer (5) connected with the N-drift region and an N-type charge storage layer (14) positioned on the upper part of the N-drift region (4) and connected with the N-drift region; the upper part of the P-type buried layer is provided with an N-type doped layer (6) connected with the P-type buried layer; the upper part of the N-type doped layer (6) is provided with a P-type doped layer (7) connected with the N-type doped layer; the upper part of the N-type charge storage layer is provided with a P-type base region (13) connected with the N-type charge storage layer; the upper part of the P-type base region is provided with an N + emitter region (11) and a P + emitter region (12) which are independent and arranged side by side; the upper part of the P-type buried layer (5), the side wall of the N-type doping layer (6), the side wall of the P-type doping layer (7), the side wall of the N-type charge storage layer (14), the side wall of the P-type base region (13) and the side wall of the N + emission region (11) are provided with groove structures, and each groove structure comprises an L-shaped separation gate electrode (91), a separation gate dielectric layer (101), a gate electrode (92), a gate dielectric layer (102), a polycrystalline silicon isolation dielectric layer (103) and a separation gate dielectric layer (105); the dielectric layer (104) is positioned on the upper part of the gate electrode (92), the upper part of the gate dielectric layer (102) and the upper part of the polysilicon isolation dielectric layer (103) and is connected with the gate electrode; emitter metal 8 and Schottky contact metal 15, wherein the emitter metal is located on the upper portion of the separation gate dielectric layer 101, the upper portion of the separation gate 91, the upper portion of the dielectric layer 104, the upper portions of the N + emitting region 11 and the P + emitting region 12 and connected with the N + emitting region and the P + emitting region; the split gate electrode (91) is connected with the P-type doped region (7), the N-type doped region 6 and the P-type buried layer (5) through a split gate dielectric layer (101), and the split gate electrode (91) is connected with the N-type charge storage layer (14) and the N-drift region (4) through a split gate dielectric layer (105); the depth of the separation gate electrode (91) is larger than that of the N-type charge storage layer (14) and smaller than that of the P-type buried layer (5); the gate electrode (92) is connected with the separation gate electrode (91) through a polycrystalline silicon isolation dielectric layer (103), the gate electrode (92) is connected with the N + emitter region (11) and the P-type base region (13) through a gate dielectric layer (102), and the depth of the gate electrode (92) is larger than that of the P-type base region (13) and smaller than that of the N-type charge storage layer (14); the P-type buried layer (5) extends to be flush with the interface of the trench and the N-type charge storage layer (14); the split gate electrode (91) is equipotential with the emitter metal (8).
3. The CSTBT with PMOS current clamp of claim 1, wherein: the P-type buried layer (5) extends below the N-type charge storage layer (14).
4. The CSTBT with PMOS current clamp as claimed in claim 2, wherein: the thickness of the dielectric layer (105) can be greater than or equal to the thickness of the gate dielectric layer (102).
5. The CSTBT with PMOS current clamp of claim 1, wherein: the super-junction P column (16) and the super-junction N column (17) are independent from each other above the N-type field stop layer (3) and below the P-type buried layer (5).
6. The CSTBT with PMOS current clamp as claimed in claim 2, wherein: the super-junction P column (16) and the super-junction N column (17) are independent from each other above the N-type field stop layer (3) and below the P-type buried layer (5).
7. The CSTBT with PMOS current clamp of claim 1, wherein: an N-type buried layer (19) is introduced below the P-type buried layer (5), the doping concentration of the N-type buried layer (19) is greater than that of the N-drift region (4), and the N-type buried layer (19) is introduced below the P-type buried layer (5), so that an additional barrier is provided for accumulation of holes, the distribution of carrier concentration for drift is improved, and the conduction voltage drop of the device is reduced.
8. The CSTBT with PMOS current clamp of claim 1, wherein: the semiconductor material of the IGBT device adopts Si, SiC, GaAs or GaN, the groove filling material adopts polycrystalline Si, SiC, GaAs or GaN, and each part can adopt the same material or different material combinations.
9. A manufacturing method of a separation gate CSTBT with PMOS current clamping comprises the following steps:
step 1: an N-type lightly doped monocrystalline silicon wafer is used as an N-drift region (4) of the device, the thickness of the selected silicon wafer is 300-600 um, and the doping concentration is highDegree of 1013～1014Per cm3；
Step 2: manufacturing a terminal structure of a device on the front surface of the silicon wafer through pre-oxidation, photoetching, etching, ion implantation and high-temperature annealing processes on the surface of the silicon wafer;
and step 3: growing a field oxide layer on the surface of a silicon wafer, photoetching to obtain an active region, growing a pre-oxide layer, and implanting P-type impurities to obtain a P-type buried layer (5), wherein the energy of ion implantation is 200-500 keV, and the implantation dosage is 1013～1014Per cm2Then, an N-type charge storage layer (14) is prepared by implanting N-type impurities above the P-type buried layer (5), wherein the ion implantation energy is 200-400 keV, and the implantation dosage is 1013～1014Per cm2A P-type base region (13) is prepared on the N-type charge storage layer by P-type ion implantation, the implantation energy of the particles is 200-400 keV, and the implantation dosage is 1013～1014Per cm2；
And 4, step 4: and depositing a protective layer on the surface of the silicon wafer, photoetching a window to perform groove silicon etching, and further etching a groove on the P-type buried layer (5). The depth of the groove is greater than that of the N-type charge storage layer (14) and less than that of the P-type buried layer (5);
and 5: o at 1050-1150 deg.C2Depositing a dielectric layer on the inner wall of the groove under the atmosphere, then depositing polycrystalline silicon on the dielectric layer at 750-950 ℃, and then reversely etching the redundant polycrystalline silicon on the surface;
step 6, masking, photoetching, etching polysilicon and etching a dielectric layer to form a gate groove
And 7: o at 1050-1150 deg.C2Oxidizing a growth medium layer in the gate trench under the atmosphere, depositing polycrystalline silicon and reversely etching the surface polycrystalline silicon to obtain a gate electrode (92) and a separation gate electrode (91);
and 8: the energy of the mask, the photoetching and the ion implantation of N-type impurities is 30-60 keV, and the implantation dosage is 1015～1016Per cm2The energy of ion implantation of P-type impurity is 60-80 keV, and the implantation dosage is 1015～1016Per cm2Annealing at 900 deg.C for 20-30 min to obtain the final productAn N + emission region (11) and a P + emission region (12) arranged side by side;
and step 9: depositing a dielectric layer on the front surface of the silicon wafer, etching and depositing metal to obtain emitter metal 8;
step 10: turning over the silicon wafer, reducing the thickness of the silicon wafer, injecting N-type impurities into the back of the silicon wafer, annealing and manufacturing an N-type field stop layer (3) of the device, wherein the thickness of the N-type field stop layer (3) is 15-30 microns, the energy of ion injection is 1500-2000 keV, and the injection dosage is 1013～1014Per cm2The annealing temperature is 1200-1250 ℃, and the time is 300-600 minutes; implanting P-type impurities into the back of the N-type field stop layer (3) to form a P-type collector region (13) with an implantation energy of 40-60 keV and an implantation dose of 1012～1013Per cm2In H2And N2Carrying out back annealing in a mixed atmosphere at the temperature of 400-450 ℃ for 20-30 minutes;
step 11: depositing metal on the back of the silicon wafer to obtain collector metal (1);
thus, the preparation of the separation gate CSTBT with the PMOS current clamping is completed.
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