CN113437141A - Floating P-region CSTBT device with polysilicon diode grid structure - Google Patents

Floating P-region CSTBT device with polysilicon diode grid structure Download PDF

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Publication number
CN113437141A
CN113437141A CN202110705609.9A CN202110705609A CN113437141A CN 113437141 A CN113437141 A CN 113437141A CN 202110705609 A CN202110705609 A CN 202110705609A CN 113437141 A CN113437141 A CN 113437141A
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China
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region
type
floating
gate
heavily doped
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CN202110705609.9A
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Inventor
李泽宏
胡汶金
赵一尚
曾潇
万佳利
吴玉舟
陈建鹏
于洋
张春英
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Sichuan Guangyi Microelectronic Co ltd
University of Electronic Science and Technology of China
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Sichuan Guangyi Microelectronic Co ltd
University of Electronic Science and Technology of China
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Priority to CN202110705609.9A priority Critical patent/CN113437141A/en
Publication of CN113437141A publication Critical patent/CN113437141A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
    • H01L29/7395—Vertical transistors, e.g. vertical IGBT
    • H01L29/7396—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions
    • H01L29/7397—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66234—Bipolar junction transistors [BJT]
    • H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
    • H01L29/66333—Vertical insulated gate bipolar transistors
    • H01L29/66348—Vertical insulated gate bipolar transistors with a recessed gate

Abstract

The invention relates to a floating P region CSTBT device with a polysilicon diode grid structure, belonging to the technical field of power semiconductor devices. Based on the traditional FP-CSTBT structure, on the basis of effectively reducing the conduction voltage drop of the device by utilizing a CS layer and a floating P region, on one hand, a diode grid structure is arranged in a groove, and a grid electrode and a collector electrode are further shielded by utilizing junction capacitance of a PN junction in the groove, so that smaller Miller capacitance is realized, and the switching characteristic of the device is optimized; on the other hand, the thickness of a gate oxide layer around the P-type poly gate is increased, the Miller capacitance of the device is further reduced, and electric fields at the bottom of the groove and at the corner of the groove are optimized, so that the compromise relation between the conduction voltage drop and the turn-off loss of the power device is better realized.

Description

Floating P-region CSTBT device with polysilicon diode grid structure
Technical Field
The invention belongs to the technical field of power semiconductor devices, and particularly relates to a floating P region CSTBT device with a polysilicon diode grid structure.
Background
Insulated-Gate Bipolar Transistors (IGBTs) integrate the advantages of field control devices and Bipolar devices, have the characteristics of high input impedance of MOSFETs, easy driving of gates and the like, have the advantages of high current density, high power density and the like of Bipolar Transistors, and are widely applied to the fields of rail transit, new energy vehicles, smart grids, wind power generation and the like at present. Due to the requirements of application environments and circuit topologies, IGBTs have been developed along the trend of reducing the switching power consumption of devices, increasing the operating frequency of devices, and increasing the reliability of devices.
The IGBT as a bipolar device can generate a conductivity modulation effect when being conducted, so that the carrier concentration in a drift region is greatly improved, the forward conduction voltage drop and the on-state loss of the device are reduced, and the IGBT has more obvious advantages particularly in the middle-high voltage application field. However, while the forward on voltage drop is greatly reduced, the extraction process at the time of turn-off is lengthened due to excessive storage carriers, and the current tail is remarkably increased, thereby greatly increasing the turn-off loss of the IGBT. Therefore, it has become a hot spot of current research to improve the contradictory relationship between the on-voltage drop and the off-loss of the device. In order to reduce the conduction voltage drop of the IGBT, on one hand, a trench gate structure is used for replacing a traditional plane gate IGBT structure, so that a JFET (junction field effect transistor) area of the traditional IGBT is eliminated, the conduction resistance of a device is greatly reduced, and the static power consumption of the device is reduced; on the other hand, on the basis of adopting the groove grid, a floating P region structure is introduced between the two grooves (namely the region is not in ohmic contact with the emitter), so that the electron injection effect of the device is enhanced, and the conduction voltage drop of the device is further reduced. In order to improve the trade-off relationship between the turn-on voltage drop and the turn-off energy loss of the device, a technology with Field Stop (FS) and a Carrier Store (CS) is generally adopted so as to achieve better optimization between the turn-on voltage drop and the turn-off energy loss of the IGBT. Although the conventional FP-CSTBT (as shown in fig. 1) can effectively reduce the on-state voltage drop of the device by using the CS layer and the floating P region, the floating P region can introduce a large displacement current, which affects the EMI noise of the device, and the large amount of carriers in the drift region can also increase the off-state time of the device. Therefore, it is urgently needed to develop an IGBT device that can better realize the contradictory relationship between the on-state voltage drop and the turn-off loss of the device.
Disclosure of Invention
The invention aims to solve the technical problem in the prior art and provides a floating P region CSTBT device with a polysilicon diode grid structure so as to further improve the compromise relationship between on-state voltage drop and off-state loss.
In order to solve the above technical problem, an embodiment of the present invention provides a floating P-region CSTBT device with a polysilicon diode gate structure, wherein a cell structure of the CSTBT device includes a metal collector 1, a P + collector region 2, an N-type buffer layer 3, an N-type drift region 4, and a metal emitter 13, which are sequentially stacked from bottom to top;
the top layer of the N-type drift region 4 is provided with trench gate structures arranged at intervals, the top layer of the N-type drift region 4 on one side of each trench gate structure is provided with a floating P region 9, the top layer of the N-type drift region 4 on the other side of each trench gate structure is provided with a P-type base region 6, the top layer of the P-type base region 6 is provided with a P-type heavily doped region 7 and an N-type heavily doped region 8, the side surfaces of the P-type heavily doped region 7 and the side surfaces of the N-type heavily doped region 8 are mutually contacted, and an N-type carrier storage layer 5 is;
the trench gate structure comprises an oxide layer 12, and an N + gate 10 and a P + gate 11 which are sequentially arranged from top to bottom; the oxide layer 12 is arranged among the N + grid 10, the N-type carrier storage layer 5, the P-type base region 6, the N-type heavily doped region 8 and the floating P region 9, and the oxide layer 12 is arranged between the P + grid 11 and the N-type drift region 4;
an oxide layer 12 is arranged on the first part of the N-type heavily doped region 8, the trench gate structure and the floating P region 9, and the metal emitter 13 is positioned on the second part of the N-type heavily doped region 8, the P-type heavily doped region 7 and the oxide layer 12.
On the basis of the technical scheme, the invention can be further improved as follows.
Further, the thickness of the oxide layer 12 between the P + gate 11 and the N-type drift region 4 is thicker than the thickness of the oxide layer 12 between the N + gate 10 and the N-type carrier storage layer 5, the P-type base region 6, the N-type heavily doped region 8 and the floating P region 9.
Furthermore, the N + gate 10 and the P + gate 11 are made of polysilicon.
Furthermore, the cellular structure is symmetrical left and right.
Compared with the prior art, the invention has the beneficial effects that: the invention provides a floating P region CSTBT device with a polysilicon diode grid structure on the basis of an FP-CSTBT structure. On the basis of effectively reducing the conduction voltage drop of the device, on one hand, a polysilicon diode is introduced into the groove structure, and a grid electrode and a collector electrode are further shielded by utilizing the junction capacitance of a PN junction formed by the diode in the groove, so that smaller Miller capacitance and input capacitance are realized, and the switching characteristic of the device is optimized; on the other hand, the thickness of a gate oxide layer around the P-type poly gate is increased, the Miller capacitance of the device is further reduced, and electric fields at the bottom of the groove and at the corner of the groove are optimized, so that the compromise relation between the conduction voltage drop and the turn-off loss of the power device is better realized.
Drawings
Fig. 1 is a schematic diagram of a lateral cross-sectional structure of a conventional csbt (Floating-P Trench IGBT with CS layer, FP-csbt) with a Floating P-region.
Fig. 2 is a schematic diagram of a lateral cross-sectional structure of a floating P-region CSTBT device (APD-FP-CSTBT) having a Polysilicon diode gate structure according to an embodiment of the present invention.
In the drawings, the components represented by the respective reference numerals are listed below:
the device comprises a metal collector 1, a P + collector region 2, an N-type buffer layer 3, an N-type drift region 4, an N-type carrier storage layer 5, a P-type base region 6, a P-type heavily doped region 7, an N-type heavily doped region 8, a floating P region 9, an N + grid 10, a P + grid 11, an oxide layer 12 and a metal emitter 13.
Detailed Description
The principles and features of this invention are described below in conjunction with the following drawings, which are set forth by way of illustration only and are not intended to limit the scope of the invention.
As shown in fig. 2, a floating P-region CSTBT device with a polysilicon diode gate structure according to a first embodiment of the present invention includes a metal collector 1, a P + collector region 2, an N-type buffer layer 3, an N-type drift region 4, and a metal emitter 13, which are sequentially stacked from bottom to top;
the top layer of the N-type drift region 4 is provided with trench gate structures arranged at intervals, the top layer of the N-type drift region 4 on one side of each trench gate structure is provided with a floating P region 9, the top layer of the N-type drift region 4 on the other side of each trench gate structure is provided with a P-type base region 6, the top layer of the P-type base region 6 is provided with a P-type heavily doped region 7 and an N-type heavily doped region 8, the side surfaces of the P-type heavily doped region 7 and the side surfaces of the N-type heavily doped region 8 are mutually contacted, and an N-type carrier storage layer 5 is arranged in the N-type drift region 4 below the P-type base region 6;
the trench gate structure comprises an oxide layer 12, and an N + gate 10 and a P + gate 11 which are sequentially arranged from top to bottom; the oxide layer 12 is arranged among the N + grid 10, the N-type carrier storage layer 5, the P-type base region 6, the N-type heavily doped region 8 and the floating P region 9, and the oxide layer 12 is arranged between the P + grid 11 and the N-type drift region 4;
an oxide layer 12 is arranged on the first part of the N-type heavily doped region 8, the trench gate structure and the floating P region 9, and the metal emitter 13 is positioned on the second part of the N-type heavily doped region 8, the P-type heavily doped region 7 and the oxide layer 12.
In the above embodiment, the N-type carrier storage layer 5 is used to increase the carrier concentration of the N-type drift region 4, so as to reduce the on-state voltage drop of the device. The floating P region 9 is used to enhance the electron injection effect, thereby reducing the device turn-on voltage drop. The N + grid 10 and the P + grid 11 form a polysilicon diode grid structure and are used for reducing the Miller capacitance of the device.
Optionally, the thickness of the oxide layer 12 between the P + gate 11 and the N-type drift region 4 is thicker than the thickness of the oxide layer 12 between the N + gate 10 and the N-type carrier storage layer 5, the P-type base region 6, the N-type heavily doped region 8, and the floating P region 9.
In the above embodiment, the thick oxide layer between the P + gate (11) and the N-type drift region (4) is used to reduce the miller capacitance of the device on the one hand and to optimize the electric field at the bottom and corners of the trench gate on the other hand.
Optionally, the materials of the N + gate 10 and the P + gate 11 are polysilicon.
Optionally, the cellular structure is left-right symmetric.
The principle of the invention is as follows: the invention provides a floating P region CSTBT (anti-diode gates structure for FP-CSTBT, APD-FP-CSTBT) device with a Polysilicon diode gate structure based on a traditional FP-CSTBT structure. On the basis of effectively reducing the conduction voltage drop of the device by utilizing the CS layer and the floating P region, on one hand, a polysilicon diode is introduced into the groove structure, and the grid electrode and the collector electrode are further shielded by utilizing the junction capacitance of a PN junction formed by the diode in the groove, so that smaller Miller capacitance and input capacitance are realized, and the switching characteristic of the device is optimized; on the other hand, the thickness of a gate oxide layer around the P-type poly gate is increased, the Miller capacitance of the device is further reduced, and electric fields at the bottom of the groove and at the corner of the groove are optimized, so that the compromise relation between the conduction voltage drop and the turn-off loss of the power device is better realized.
The invention provides a floating P region CSTBT with a polysilicon diode grid structure based on a traditional FP-CSTBT structure, and compared with the traditional structure, the structure can effectively reduce the Miller capacitance of a device and realize a better compromise relation between conduction voltage drop and turn-off loss.
In the description herein, references to the description of the term "one embodiment," "some embodiments," "an example," "a specific example," or "some examples," etc., mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, the schematic representations of the terms used above are not necessarily intended to refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, various embodiments or examples and features of different embodiments or examples described in this specification can be combined and combined by one skilled in the art without contradiction.
The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents, improvements and the like that fall within the spirit and principle of the present invention are intended to be included therein.

Claims (4)

1. A floating P region CSTBT device with a polysilicon diode grid structure is characterized in that a cellular structure comprises a metal collector (1), a P + collector region (2), an N-type buffer layer (3), an N-type drift region (4) and a metal emitter (13) which are sequentially stacked from bottom to top;
the top layer of the N-type drift region (4) is provided with trench gate structures arranged at intervals, the top layer of the N-type drift region (4) on one side of each trench gate structure is provided with the floating P region (9), the top layer of the N-type drift region (4) on the other side of each trench gate structure is provided with the P-type base region (6), the top layer of the P-type base region (6) is provided with a P-type heavily doped region (7) and an N-type heavily doped region (8) of which the side surfaces are mutually contacted, and an N-type carrier storage layer (5) is arranged in the N-type drift region (4) below the P-type base region (6);
the trench gate structure comprises an oxide layer (12), and an N + gate (10) and a P + gate (11) which are sequentially arranged from top to bottom; the oxide layer (12) is arranged among the N + grid (10), the N-type carrier storage layer (5), the P-type base region (6), the N-type heavily doped region (8) and the floating P region (9), and the oxide layer (12) is arranged between the P + grid (11) and the N-type drift region (4);
an oxide layer 12 is arranged on the first part of the N-type heavily doped region (8), the groove gate structure and the floating P region (9), and the metal emitter (13) is positioned on the second part of the N-type heavily doped region (8), the P-type heavily doped region (7) and the oxide layer (12).
2. The CSTBT device with the polysilicon diode gate structure as claimed in claim 1, wherein the thickness of the oxide layer (12) between the P + gate (11) and the N-type drift region (4) is thicker than the thickness of the oxide layer (12) between the N + gate (10) and the N-type carrier storage layer (5), the P-type base region (6), the N-type heavily doped region (8) and the floating P region (9).
3. The CSTBT device with the polysilicon diode gate structure as claimed in claim 1, wherein the N + gate (10) and the P + gate (11) are made of polysilicon.
4. The CSTBT device with polysilicon diode gate structure of claim 1, wherein the cell structure is symmetric.
CN202110705609.9A 2021-06-24 2021-06-24 Floating P-region CSTBT device with polysilicon diode grid structure Pending CN113437141A (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113990924A (en) * 2021-10-26 2022-01-28 电子科技大学 IGBT structure capable of reducing turn-off loss
CN114093934A (en) * 2022-01-20 2022-02-25 深圳市威兆半导体有限公司 IGBT device and manufacturing method thereof

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113990924A (en) * 2021-10-26 2022-01-28 电子科技大学 IGBT structure capable of reducing turn-off loss
CN114093934A (en) * 2022-01-20 2022-02-25 深圳市威兆半导体有限公司 IGBT device and manufacturing method thereof

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