JP2000138370A - Mosfet - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent a MOSFET from becoming slow in operation speed. SOLUTION: A MOSFET is equipped with a semiconductor substrate 1, mounted with source electrodes S and a drain electrode D that are each formed on its one surface and the other surface, a recess 1a bored in the surface of the substrate 1, where the source electrodes S are provided and provided with an insulation film 1b formed on its inner wall surface, a polysilicon layer 2 filled into the recess 1a, a gate electrode G formed on the outer surface of the polysilicon layer 2, and a channel layer 3 which is controlled by the gate electrode G and electrically connects the source electrodes S to the drain electrode D along the insulating layer 1b. In this case, the polysilicon layer 2 is composed of a first polysilicon layer 2a, where the gate electrode G is formed on its outer surface and a second polysilicon layer 2b whose conductivity is different from that of the first polysilicon layer 2a and located closer to the other surface of the substrate 1 than the first polysilicon layer 2a.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a MOSFET in which a polysilicon layer is buried as a gate region in a recess provided on the surface of a semiconductor substrate.

[0002]

2. Description of the Related Art As this kind of MOSFET, there is one shown in FIG. It has a source electrode S on one surface and a drain electrode on the other surface.
A semiconductor substrate B which D is provided, the recess A having an insulating film A ₁ on the inner surface are Ho設from one surface of the semiconductor substrate B
A polysilicon layer P of the same conductivity type buried in the recess A, a gate electrode G provided on the outer surface of the polysilicon layer P, and a source electrode S controlled by the gate electrode G.
And a, a channel layer C to conduct along the insulating layer A ₁ between the drain electrode D and.

Next, the operation of the above device will be described. The electrons injected from the source electrode S pass through the diffusion layer E provided near the first surface, and then pass through the gate electrode G and the source electrode S.
Through the channel layer C whose conduction state is controlled along the insulating layer A ₁ by the potential difference applied between the _first electrode and the drain electrode D through the diffusion layer F provided near the second surface. become.

[0004]

SUMMARY OF THE INVENTION The conventional MOS described above
In the case of the FET, of the insulating film A _{1 on} the inner surface of the concave portion A,
Portion A ₁₁ located between polysilicon layer P and diffusion layer F
However, there is a problem in that the device has a gate-drain capacitance as shown in FIG. 3 and the capacitance acts as an input capacitance of the MOSFET, thereby lowering the operation speed.

The present invention has been made in view of the above points, and an object of the present invention is to provide a MOSFET whose operating speed does not decrease.

[0006]

In order to solve the above-mentioned problems, the present invention is directed to a semiconductor substrate having a source electrode provided on one surface and a drain electrode provided on the other surface; A concave portion dug from one surface of the semiconductor substrate and having an insulating film on an inner surface, a polysilicon layer buried in the concave portion, a gate electrode provided on an outer surface of the polysilicon layer, and controlled by the gate electrode And a channel layer that conducts between the source electrode and the drain electrode along the insulating layer, wherein the polysilicon layer is a first polysilicon layer having the gate electrode provided on an outer surface thereof. And a second polysilicon layer having a conductivity type different from that of the first polysilicon layer and provided closer to the other surface than the first polysilicon layer.

According to a second aspect of the present invention, in the first aspect of the present invention, the concave portion is dug so that the opening area decreases as the distance from the one surface increases.

[0008]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A first embodiment of the present invention will be described below with reference to FIG.

Reference numeral 1 denotes an n-type semiconductor substrate having a source electrode S provided on one surface and a drain electrode D provided on the other surface. This semiconductor substrate 1
For example, a well-shaped recess 1a is formed from one surface by RIE or the like, and an insulating film is formed on the inner surface of the recess 1a.
After the formation of 1b, the polysilicon layer 2 is buried.
The polysilicon layer 2 is formed by first diffusing a p-type impurity and then diffusing an n-type impurity only in a shallow portion, so that an upper layer near one surface has a p-type first polysilicon layer. 2a, and the lower part near the other surface is
This is an n-type second polysilicon layer 2b. This first
A gate electrode G is provided on the outer surface of the polysilicon layer 2a. The first and second polysilicon layers
In forming 2a, 2b, first, a polysilicon layer containing a p-type impurity is buried in the concave portion 1a, and then,
An n-type impurity may be diffused.

The semiconductor substrate 1 includes an n-type diffusion layer 1c, a p-type diffusion layer 1d, an n-type epitaxial layer 1e, and an n-type silicon layer 1f in this order from the first surface.
The portion of 1d along the above-described insulating layer 1b serves as a channel layer 3 controlled by the gate electrode G to conduct between the source electrode S and the drain electrode D.

Next, the operation of this device will be described. The electrons injected from the source electrode S pass through the n-type diffusion layer 1c and then pass through the channel layer 3 to form the n-type epitaxial layer 1e.
And through the n-type silicon layer 1f to escape to the drain electrode D.

In such a MOSFET, the first polysilicon layer 2a having the gate electrode G provided on the outer surface is
Since the conductivity type is different from the second polysilicon layer 2b provided closer to the other surface than the first polysilicon layer 2a,
Since the two polysilicon layers 2a and 2b are electrically separated by the PN junction surface at the interface between the first polysilicon layer 2a and the second polysilicon layer 2b, they have a gate-drain capacitance. Unlike the conventional example, the portion becomes only the portion X between the first polysilicon layer 2a and the n-type epitaxial layer 1e which is the semiconductor layer on the drain electrode side, and becomes small. Disappears.

Next, a second embodiment of the present invention will be described below with reference to FIG. Note that portions having substantially the same functions as those of the first embodiment are denoted by the same reference numerals, and only the differences from the first embodiment will be described. In the first embodiment, the concave portion
1a is formed in a well shape, whereas in the present embodiment, the anisotropic etching of the <100> plane of the silicon single crystal substrate results in a V-shaped cross section having a smaller opening area as the distance from one surface increases. Is formed.

In such a MOSFET, in addition to the effect of the first embodiment, in general, when filling the recess 1a, it is difficult to fill the corner of the recess 1a. The hole is dug so that the opening area becomes smaller as the distance increases, so that the filling does not become difficult.

In the first and second embodiments, the polysilicon layer 2 is composed of a first polysilicon layer and a second polysilicon layer. The polysilicon layer 2 has three or more layers having these polysilicon layers. However, a similar effect can be obtained.

[0016]

According to the first aspect of the present invention, the first polysilicon layer provided on the outer surface with the gate electrode is provided on the second polysilicon layer provided closer to the other surface than the first polysilicon layer. Since the conductivity type is different from that of the silicon layer, both polysilicon layers are electrically separated by the PN junction surface at the interface between the first polysilicon layer and the second polysilicon layer. Unlike the conventional example, the portion having the capacitance becomes smaller only between the first polysilicon layer and the semiconductor layer on the side of the drain electrode, so that the operation speed does not decrease.

According to the second aspect of the present invention, in addition to the effect of the first aspect of the present invention, when the concave portion is generally filled, it is difficult to fill the corner portion of the concave portion.
Since the hole is dug so that the opening area becomes smaller as the distance from the one surface increases, the filling does not become difficult.

[Brief description of the drawings]

FIG. 1 is a sectional view of a first embodiment of the present invention.

FIG. 2 is a sectional view of a second embodiment of the present invention.

FIG. 3 is a sectional view of a conventional example.

FIG. 4 is an equivalent circuit diagram of the above.

[Explanation of symbols]

 1 semiconductor substrate 1a recess 1b insulating film 2 polysilicon layer 2a first polysilicon layer 2b second polysilicon layer 3 channel layer D drain electrode G gate electrode S source electrode

Claims (2)

[Claims] 1. A semiconductor substrate having a source electrode provided on one surface and a drain electrode provided on the other surface, and a concave portion dug from one surface of the semiconductor substrate and having an insulating film on an inner surface. A polysilicon layer buried in the recess, a gate electrode provided on the outer surface of the polysilicon layer, and a channel layer controlled by the gate electrode to conduct between the source electrode and the drain electrode along the insulating layer. ,
Wherein the polysilicon layer has a conductivity type different from that of the first polysilicon layer and the first polysilicon layer in which the gate electrode is provided on the outer surface, and the polysilicon layer has a higher conductivity type than the first polysilicon layer. A MOSFET comprising a second polysilicon layer provided near the other surface. 2. The MOSFET according to claim 1, wherein the recess is dug so that the opening area decreases as the distance from the one surface increases.