CN109065619B - IGBT device with low-noise and low-switching loss characteristics - Google Patents
IGBT device with low-noise and low-switching loss characteristics Download PDFInfo
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- H01L29/7396—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions
- H01L29/7397—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
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Abstract
The invention belongs to the technical field of power semiconductor devices, and particularly relates to an IGBT device with low noise and low switching loss. According to the invention, low-noise structures of a P + type JFET source region 13, an N + type JFET gate region 14 and a P-type JFET channel region 15 are introduced into a discrete floating pbody region 8 of a traditional IGBT device, so that hole storage is realized to enhance conductance modulation when the device is in forward conduction, and the hole is quickly released when the device is switched off, so that the switching-off time is reduced; meanwhile, a half-surrounded structure is formed on the JFET gate region 14 through the dielectric layer 10, so that the Miller capacitance Cgc of the device is reduced, the influence of parasitic NPN opening in the JFET structure on effective gate voltage is inhibited, and the switching time and the switching loss are reduced under the condition of ensuring low noise.
Description
Technical Field
The invention belongs to the technical field of power semiconductor devices, and particularly relates to an IGBT device with low noise and low switching loss.
Background
With the rapid development of the fields of rail transit, smart grid, wind power generation, etc., an Insulated Gate Bipolar Transistor (IGBT) has become one of mainstream power switching devices in a medium-high power range by virtue of the advantages of simple Gate control, high input impedance, large current density, reduced saturation voltage, etc., and will continue to develop towards high voltage, large current, low power loss, high operating temperature, high reliability, etc.
The high-voltage IGBT generally adopts a planar gate structure and is used in high-speed rail, power transmission and other environments with high requirements on reliability, but because of parasitic JFET resistance, the planar gate type IGBT has large saturation voltage drop and increased on-state loss compared with a groove gate type structure; meanwhile, the cell pitch of the trench gate type IGBT (Trench IGBT) is small, the current density is large, and the structure becomes a common structure for reducing conduction loss. In the TIGBT, an electric field peak value exists at the bottom of the groove gate, so that the improvement of blocking voltage is limited, and meanwhile, the short-circuit current is large and the short-circuit resistance is weak; the peak value of the electric field can be reduced by introducing a P-floating shielding layer at the bottom of the groove gate, but additional JFET resistance is introduced, so that the conduction loss is increased; the clamp diode is introduced into the P base region between the groove gates at the same time, the Eoff-Vcesat optimization trade-off relation can be improved at the same time, and the short-circuit bearing capacity of the device can be enhanced, but the existing scheme mostly focuses on 1200V voltage level. The current density of the device can be reduced by adopting a wide slot gate spacing or an FP (Floating-Pbody) area, and the short circuit bearing capacity of the TIGBT is obviously improved, but the voltage change generated in the FP structure when the device is turned on is caused by the negative gate capacitance effect of the slot gate type IGBT (FP-TIGBT) with the FP structure, and the displacement current is generated at the gate through the miller capacitance Cgc, so that the gate control capacity of the IGBT is reduced, and meanwhile, the EMI noise problem is brought.
At the voltage level of 1200-1700V, the EMI problem can be improved through the Fin p-Body, Shield Trench and Side-gate structures, but the requirement on the manufacturing process precision is strict; for the IGBT with the voltage level higher than 2500V, foreign enterprises such as ABB and Hitachi have already proposed 3300V-TIGBT products, through the built-in junction depth exceeds the discrete Floating Pbody of the depth of the grooved gate, play and reduce the electric field peak value of the bottom of the grooved gate and strengthen the role of conductance modulation, improve Eoff-Vcesat trade-off relation, but the discrete Floating FP district will influence the withstand voltage and turn-on characteristic of the device; and the discrete FP is connected with the ground through a fixed resistor to provide a partial hole path, so that the conduction loss is easily increased.
Disclosure of Invention
In view of the above, the present invention provides an IGBT device with low noise and low switching loss, which solves the problems of reduced device withstand voltage, large switching loss, etc. caused by the potential variation of P region in the prior art of a trench gate IGBT device with discrete floating P region. Forming a groove in the discrete FP, and embedding a JFET structure in the groove to form a hole carrier control structure; the JFET is a low-noise device and is arranged in a discrete FP area, and is equivalent to a variable resistor, so that the voltage withstanding reliability of the device can be improved while the EMI problem is solved; meanwhile, the Miller capacitance is reduced, and the switching loss is reduced.
In order to achieve the above purpose, the invention provides the following technical scheme:
a low-noise low-switching-loss IGBT device comprises a cellular structure, a metal collector 7, a P + collector region 6, an N-type buffer layer 5, an N-drift region 4 and a metal emitter 11 which are sequentially stacked from bottom to top; a discrete P + floating pbody region 8 is arranged in the middle area of the top layer of the N-drift region 4, P + base regions 2 are respectively arranged on two sides of the discrete P + floating pbody region 8, and an N + emitter region 1 is arranged on the top layer of each P + base region 2; the P + base region 2 and the N + emitter region 1 are in contact with the discrete P + floating pbody region 8 through a metal emitter 11; a gate structure is arranged between the P + base region 2 and the N + emitter region 1 and the discrete P + floating body region 8, the gate structure comprises a gate electrode 9 and a gate dielectric layer 3, the gate dielectric layer 3 extends into the N-drift region 4 along the vertical direction of the device to form a groove, and the gate electrode 9 is arranged in the groove; one side of the gate dielectric layer 3 is contacted with the P + base region 2, the N + emitter region 1 and the N-drift region 4, and the method is characterized in that: the other side of the gate dielectric layer 3 is isolated from the discrete P + floating body region 8 through the N-drift region 4; the discrete P + floating body region 8 is also provided with a JFET structure formed by an N + type JFET gate region 14, a P + type JFET source region 13 and a P-type JFET channel region 15; the P + type JFET source region 13 is arranged on the top layer of the P + type JFET channel region 15, the N + type JFET gate regions 14 are symmetrically arranged on two sides of the P + type JFET source region 13 and are in contact with the gate electrode 9 through the connecting bridge 12; the N + type JFET gate region 14 is isolated from the discrete P + floating body region 8 through a dielectric layer 10; the P + type JFET source region 13 is in contact with the P + base region 2 and the N + emitter region 1 through the metal emitter 11; the metal emitter 11 and the N-drift region 4 are isolated from each other through the dielectric layer 10, the P-type JFET channel region 15 is isolated from each other, and the connecting bridge 12 and the N-drift region 4 are isolated from each other through the dielectric layer 10.
Further, the junction depth of the discrete P + floating pbody regions 8 in the present invention is greater than the depth of the gate structure.
Further, the width of the channel region 15 of the P-type JFET in the invention is smaller than the width of a depletion region generated by the JFET under the on-state condition of the device.
Further, in the invention, the dielectric layer 10 between the N + type JFET gate region 14 and the discrete P + floating pbody region 8 is wide in thickness, so that a semi-surrounding structure of the JFET gate region 14 is realized, and PN junction capacitance between the JFET gate region 14 and the discrete P + floating pbody region 8 is eliminated.
Further, the semi-surrounding structure of the dielectric layer 10 to the JFET gate region 14 in the present invention is realized by a combination of dry etching or wet etching and thermal oxidation process.
Furthermore, the doping manner of the discrete P + floating pbody region 8 in the present invention is non-uniform doping or uniform doping.
Furthermore, the semiconductor material in the invention is monocrystalline silicon, silicon carbide or gallium nitride.
The JFET structure in the discrete P + floating pbody region 8 of the invention needs to meet the following conditions:
1. the discrete P + floating body region 8 is separated from the grid structure through the N-drift region 4;
the N + type JFET gate region 14 is located in the neutral region of the discrete P + floating pbody region 8 when forward blocked;
and 3, the depletion layer width generated by the N + type JFET gate region 14 and the P-type JFET channel region 15 which are symmetrical left and right in the JFET structure can completely block the channel region.
Compared with the prior art, the invention has the beneficial effects that:
1. according to the invention, the JFET area is introduced into the discrete P + floating body area, and the JFET area is equivalent to a variable resistor; holes are stored when the device is conducted in the forward direction, so that the saturation conduction voltage drop of the device is reduced; and a quick release loop is provided for holes when the device is blocked in the forward direction, so that the turn-off time and the turn-off loss are reduced.
2. According to the invention, the discrete P + floating body region is connected with the ground when being turned off, so that the Miller capacitance Cgc is reduced, and the switching time and the switching loss are effectively reduced.
3. The semi-surrounding structure of the dielectric layer 10 to the JFET gate region 14 can effectively reduce the gate capacitance, and simultaneously reduce the JFET gate leakage current generated by a parasitic NPN triode formed by the JFET gate region, the discrete P + floating body region and the N-drift region.
4. According to the half-surrounding structure of the dielectric layer 10 to the JFET gate region 14, a shallow groove is formed in the process of an IGBT groove gate structure, a thick dielectric layer is formed in the process of a gate dielectric layer 3, and the contact between a JFET channel region 15 and a discrete P + floating body region is formed by etching the bottom region of the shallow groove; and finally, forming a JFET structure through deposition and doping processes, and being compatible with the manufacturing process of the existing high-voltage IGBT device.
Drawings
FIG. 1 is a schematic structural diagram of a conventional discrete floating body IGBT device;
FIG. 2 is a schematic structural diagram of an IGBT device with low noise and low switching loss provided by the present invention;
FIG. 3 is an equivalent circuit diagram of the IGBT device with low noise and low switching loss provided by the invention;
FIG. 4 is a waveform comparison diagram of the switching process of the IGBT structure provided by the invention and the conventional structure;
FIG. 5 is a comparison graph of Miller capacitance Cgc of the IGBT structure provided by the invention and the traditional structure;
in the figure: the semiconductor device comprises an N + emitter region 1, a P + base region 2, a gate dielectric layer 3, an N-drift region 4, an N-type buffer layer 5, a P + collector region 6, a metal collector 7, a discrete P + floating pbody region 8, a gate electrode 9, a dielectric layer 10, a metal emitter 11, a connecting bridge 12, a P + JFET source region 13, an N + JFET gate region 14 and a P-type JFET channel region 15.
Detailed Description
The technical scheme of the invention is described in detail and clearly in the following description with reference to the accompanying drawings and the specific embodiments:
example (b):
an IGBT device with low noise and low switching loss, as shown in fig. 2, a cellular structure of the IGBT device includes a metal collector 7, a P + collector region 6, an N-type buffer layer 5, an N-drift region 4, and a metal emitter 11, which are sequentially stacked from bottom to top; a discrete P + floating pbody region 8 is arranged in the middle area of the top layer of the N-drift region 4, P + base regions 2 are respectively arranged on two sides of the discrete P + floating pbody region 8, and an N + emitter region 1 is arranged on the top layer of each P + base region 2; the P + base region 2 and the N + emitter region 1 are in contact with the discrete P + floating pbody region 8 through a metal emitter 11; a gate structure is arranged between the P + base region 2 and the N + emitter region 1 and the discrete P + floating body region 8, the gate structure comprises a gate electrode 9 and a gate dielectric layer 3, the gate dielectric layer 3 extends into the N-drift region 4 along the vertical direction of the device to form a groove, and the gate electrode 9 is arranged in the groove; one side of the gate dielectric layer 3 is contacted with the P + base region 2, the N + emitter region 1 and the N-drift region 4, and the method is characterized in that: the other side of the gate dielectric layer 3 is isolated from the discrete P + floating body region 8 through the N-drift region 4; the discrete P + floating body region 8 is also provided with a JFET structure formed by an N + type JFET gate region 14, a P + type JFET source region 13 and a P-type JFET channel region 15; the P + type JFET source region 13 is arranged on the top layer of the P + type JFET channel region 15, the N + type JFET gate regions 14 are symmetrically arranged on two sides of the P + type JFET source region 13 and are in contact with the gate electrode 9 through the connecting bridge 12; the N + type JFET gate region 14 is isolated from the discrete P + floating body region 8 through a dielectric layer 10; the P + type JFET source region 13 is in contact with the P + base region 2 and the N + emitter region 1 through the metal emitter 11; the metal emitter 11 and the N-drift region 4 are isolated from each other through the dielectric layer 10, the P-type JFET channel region 15 is isolated from each other, and the connecting bridge 12 and the N-drift region 4 are isolated from each other through the dielectric layer 10.
As a preferred embodiment, in this embodiment, the junction depth of the discrete P + floating body region 8 is greater than the depth of the gate structure (i.e., the trench gate); therefore, when the device is blocked in the forward direction, the P-type floating body region 8 and the N-drift region 4 can form a depletion region, so that the electric field concentration phenomenon at the bottom of a grid structure (namely a groove grid) during the forward blocking is weakened, and the reliability of the forward withstand voltage of the groove grid type high-voltage IGBT device is ensured.
The principles of the present invention are described in detail below with reference to examples:
when the structure is blocked in the forward direction, the IGBT grid electrode is at zero potential, the JFET channel is conducted at the moment, the discrete P + floating pbody area 8 is directly connected with the ground through the JFET channel, and a floating pbody/N-drift area withstand voltage PN junction is increased; meanwhile, the junction depth of the discrete P + floating body region 8 is larger than the depth of the grid structure, so that the electric field concentration phenomenon at the bottom of the groove grid during forward blocking can be weakened, the same effect as a floating field limiting ring is realized, and the breakdown voltage is favorably improved. In contrast, in the conventional discrete floating pbody region IGBT device structure shown in fig. 1, the discrete P + floating pbody region 8 stores excessive holes when conducting in the forward direction, and the holes can only be discharged through the P + base region (i.e., P-base region) of the unit cell when turning off, so that the turn-off time and turn-off loss are increased; meanwhile, when the forward blocking is carried out, the potential of the separately floating pbody area floats, although the electric field peak value at the bottom of the groove gate can be reduced, the partial pressure effect is not as grounded as the pbody area, and the forward blocking voltage is lower than that of the structure.
When the device is in forward conduction, the IGBT gate electrode is at high potential, at the moment, the N + type JFET gate region 14 and the P-type JFET channel region 15 form a depletion layer, and the separated P + floating body region 8 cannot be connected with the ground potential. Electrons are injected into the drift region from the MOS channel, holes are injected into the N-drift region 4 from the metal collector 7 on the back, and the N-drift region 4 has a conductance modulation effect; meanwhile, holes can be stored in the discrete P + floating body region 8, and corresponding electrons can be generated in the N-drift region 4 according to the electric neutral principle, so that the carrier concentration in the N-drift region 4 is enhanced, and the saturated conduction voltage drop of the device is favorably reduced. With the increase of the number of holes in the discrete P + floating pbody region 8, the potential of the discrete P + floating pbody region 8 is approximately equal to the potential of the N-drift region 4, an NPN transistor formed by the N + type JFET gate region 14, the discrete P + floating pbody region 8 and the N-drift region 4 has an opening risk, and the medium layer 10 in the provided structure semi-surrounds the JFET gate region 14, so that the area of a parasitic NPN transistor PN junction can be reduced, parasitic NPN gain is reduced, leakage current at the JFET gate when the device is turned on is effectively reduced, and the IGBT gate control capability is improved. Because the discrete P + floating body region is connected with the ground when being turned off, the Miller capacitance Cgc is reduced, the plateau period of the gate voltage in the switching process is reduced, and the switching time and the switching loss can be effectively reduced. The semi-surrounding structure of the dielectric layer 10 to the JFET gate region 14 reduces the relative area of the JFET gate and the collector, and is beneficial to further reducing the integral gate capacitance of the device.
The structure of the device determines that the device can realize reliable forward blocking capability, effectively inhibits the parasitic NPN triode from being opened, improves the grid control capability of the device, can reduce the Miller capacitance Cgc, realizes shorter switching time and lower switching loss, and ensures the low noise characteristic of the device in the switching process because the JFET is a low-noise device.
In order to verify the beneficial effects of the invention, taking the design of 3300V high-voltage N-channel trench gate type IGBT as an example, the traditional IGBT device structure shown in fig. 1 and the IGBT device structure proposed by the invention shown in fig. 2 are compared in a simulation mode by using the piece of media software, including the static parameters of the devices: forward blocking voltage, saturated conduction voltage drop and threshold voltage, dynamic parameters: miller capacitance Cgc, turn-on loss and turn-off loss, the comparison results are shown in the following table:
it is obvious from the table that the forward blocking voltage of the structure provided by the invention is 4297V, which is improved by 13% compared with the traditional structure, the conduction voltage drop is equivalent, the turn-on loss and the turn-off loss are obviously reduced, and especially the Miller capacitance Cgc is reduced by 70% compared with the traditional structure.
The simulation result of the switching process of fig. 4 shows that the turn-off speed of the IGBT device structure proposed by the present invention is significantly increased compared to the conventional structure, and the gate voltage plateau of the proposed structure is significantly reduced due to the reduction of the miller capacitance Cgc. The capacitance simulation result of fig. 5 directly shows that the Cgc of the proposed structure is significantly reduced compared to the conventional structure in the Vce voltage range of 0-200V, and the Cgc is reduced by 70% at most under the condition that Vce is 25V.
In summary, compared with the conventional structure, the low-noise and low-switching-loss IGBT device provided by the invention introduces the low-noise JFET structure into the discrete floating pbody region, stores holes when the device is forward conducted, enhances conductivity modulation, quickly discharges the holes when the device is turned off, and reduces turn-off time; the half-surrounding structure is formed on the JFET gate region through the dielectric layer, so that the Miller capacitance of the device is reduced, meanwhile, the influence of parasitic NPN opening in the JFET structure on the gate voltage is inhibited, and the switching time and the switching loss are reduced under the condition of ensuring low noise.
It should be noted that, the low-noise and low-switching-loss IGBT device in the present invention is not only suitable for the high-voltage IGBT device of 3300V to 6500V, which is commonly used at present, but also suitable for the carrier enhancement IGBT device based on the medium-voltage range of the planar gate and the trench gate.
Claims (5)
1. An IGBT device with low noise and low switching loss characteristics comprises a unit cell structure, a metal collector (7), a P + collector region (6), an N-type buffer layer (5), an N-drift region (4) and a metal emitter (11), wherein the metal collector (7), the P + collector region, the N-type buffer layer (5), the N-drift region and the metal emitter are sequentially stacked from bottom to top; a discrete P + floating pbody region (8) is arranged in the middle area of the top layer of the N-drift region (4), P + base regions (2) are respectively arranged on two sides of the discrete P + floating pbody region (8), and an N + emitter region (1) is arranged on the top layer of the P + base region (2); the P + base region (2) and the N + emitter region (1) are in contact with the discrete P + floating body region (8) through a metal emitter (11); a grid structure is arranged between the P + base region (2) and the N + emitter region (1) and the discrete P + floating body region (8), the grid structure comprises a grid electrode (9) and a grid dielectric layer (3), the grid dielectric layer (3) extends into the N-drift region (4) along the vertical direction of the device to form a groove, and the grid electrode (9) is arranged in the groove; one side of the gate dielectric layer (3) is in contact with the P + base region (2), the N + emitter region (1) and the N-drift region (4), and the method is characterized in that: the other side of the gate dielectric layer (3) is isolated from the discrete P + floating body region (8) through the N-drift region (4); the discrete P + floating body region (8) is also provided with an N + type JFET gate region (14), a P + type JFET source region (13) and a P-type JFET channel region (15) to form a JFET structure; the P-type JFET channel region (15) is arranged in the middle area of the top layer of the discrete P + floating body region (8), the P + type JFET source region (13) is arranged on the top layer of the P-type JFET channel region (15), and the N + type JFET gate regions (14) are symmetrically arranged on two sides of the P + type JFET source region (13) and are in contact with the gate electrode (9) through the connecting bridge (12); the N + type JFET gate region (14) and the discrete P + floating body region (8) are isolated by a dielectric layer (10); the P + type JFET source region (13) is in contact with the P + base region (2) and the N + emitter region (1) through a metal emitter (11); the metal emitter (11) and the N-drift region (4) are isolated from the P-type JFET channel region (15) and the connecting bridge (12) and the N-drift region (4) through the dielectric layer (10).
2. The IGBT device with low noise and low switching loss characteristics according to claim 1, wherein: the width of the P-type JFET channel region (15) is smaller than the width of a depletion region generated by the JFET under the on-state condition of the device.
3. The IGBT device with low noise and low switching loss characteristics according to claim 2, wherein: the dielectric layer (10) forms a semi-surrounding structure to the JFET gate region (14).
4. The IGBT device with low-noise and low-switching loss characteristics according to claim 3, wherein: the junction depth of the discrete P + floating Pbody regions (8) is greater than the depth of the gate structure.
5. An IGBT device with low noise and low switching loss characteristics according to any one of claims 1 to 4, characterized in that: the semiconductor material used by the device is monocrystalline silicon, silicon carbide or gallium nitride.
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| CN110265477B (en) * | 2019-06-28 | 2020-12-29 | 电子科技大学 | IGBT device with PNP punch-through triode |
| CN113764510B (en) * | 2021-07-30 | 2022-09-09 | 西安电子科技大学 | Low-turn-off-loss IGBT device with enhanced electron injection effect |
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| KR100504190B1 (en) * | 1998-09-25 | 2005-10-26 | 매그나칩 반도체 유한회사 | Bridge forming method of heterobipolar transistor |
| US8058670B2 (en) * | 2009-06-04 | 2011-11-15 | Force—MOS Technology Corporation | Insulated gate bipolar transistor (IGBT) with monolithic deep body clamp diode to prevent latch-up |
| DE102015102136B4 (en) * | 2015-02-13 | 2021-09-30 | Infineon Technologies Austria Ag | Semiconductor components and a method for forming a semiconductor component |
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