CN110265477B - IGBT device with PNP punch-through triode - Google Patents

IGBT device with PNP punch-through triode Download PDF

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Publication number
CN110265477B
CN110265477B CN201910572446.4A CN201910572446A CN110265477B CN 110265477 B CN110265477 B CN 110265477B CN 201910572446 A CN201910572446 A CN 201910572446A CN 110265477 B CN110265477 B CN 110265477B
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discrete floating
pnp
base region
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CN110265477A (en
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李泽宏
孙肇峰
何云娇
赵一尚
莫佳宁
杨洋
贾鹏飞
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University of Electronic Science and Technology of China
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Abstract

The invention belongs to the technical field of power semiconductors, and particularly relates to an IGBT device with a PNP punch-through triode.A PNP triode structure is formed by a P-type second collector region, an N-type second base region and a discrete floating Pbody region; when the device is conducted in the forward direction, the PNP triode structure is not conducted, hole enhanced conductance modulation is stored, and leakage current is further reduced through the diode connected in series on the metal electrode; when the circuit is switched off, the PNP triode penetrates through the circuit to provide a cavity discharge channel, so that the switching-off time is reduced, and the switching-on time and the switching loss are reduced under the condition that other electrical characteristics are not influenced; under the blocking state of the device, the PNP triode penetrates through the device, and the voltage withstanding capability of the device is improved.

Description

IGBT device with PNP punch-through triode
Technical Field
The invention belongs to the technical field of power semiconductors, and particularly relates to an IGBT device with a PNP punch-through triode.
Background
An Insulated Gate Bipolar Transistor (IGBT) is a novel composite power device produced on the basis of a Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) and a Bipolar Junction Transistor (BJT). Because of its advantages of small driving current, high input impedance, good thermal stability, large working current, etc., the IGBT is widely used in the fields of switching Power supplies, rectifiers, inverters, UPSs (Uninterruptible Power supplies), etc., and is also the basis of new technological development of rail transit, solar and wind Power generation, etc.
The concept of IGBTs was developed rapidly since its first introduction by Baliga of the american general electric company in 1979. The on-state characteristic and the switching characteristic of the IGBT are improved step by adding a PT (Punch Through) type structure, an NPT (Non-Punch Through) type structure and an N + buffer layer structure. The gate structure is simultaneously changed from a planar gate to a groove gate, so that the problem of high saturation voltage drop caused by the existence of a JFET area is solved. With the development of the process and the continuous increase of the demand, the size of the IGBT unit cell is also gradually reduced, and the current density per unit area is continuously increased, so that the latch-up resistance and the short circuit resistance of the device are reduced.
In response to this problem, it has been proposed to introduce an FP (Floating-Pbody) structure between two trench gates to reduce the channel density per unit area, which essentially reduces the current density per unit area to improve the short-circuit capability. However, due to the introduction of the structure, the change of the FP potential can generate displacement current in the switching process of the IGBT, and the displacement current is coupled with the gate capacitor and then affects the gate voltage, so that the gate control capability is reduced. For this reason, it is proposed in the literature that the FP structure is changed to a discrete Floating P region (SFP) structure, so that the P-type doped region between two trenches is separated from the trenches, and a displacement current cannot act on the gate; the depth of the SFP area is deeper than that of the groove gate, so that an electric field at the bottom of the groove gate is weakened, conductivity modulation is enhanced, and turn-off loss is influenced; if the discrete floating P region is grounded, the turn-off loss can be effectively reduced, the blocking characteristic can be improved, and the forward saturation voltage drop can be increased.
Disclosure of Invention
In view of the above, the present invention provides an IGBT device with a PNP punch-through transistor, which is directed to the problems of the prior art trench gate IGBT device with a discrete floating P region that the on-state and off-state of the device are affected by the potential variation of the discrete floating P region, and the switching loss is large. Forming a hole carrier channel with a punch-through triode structure by forming a punch-through triode in the discrete floating P region; in the blocking state, the PNP triode is penetrated through, so that the potential of the discrete floating P area is reduced, and the blocking capability is effectively improved; the change of the potential in the discrete floating P area in the turn-off process enables the punch-through triode to be turned on in the turn-off process, so that the turn-off loss is reduced, and the latch-up resistance of the device is improved due to the addition of a hole shunting channel; the punch-through triode can not be started in a normal conduction state, leakage current is further reduced through the series diode, and the conduction characteristic and the anti-EMI capability of the device are guaranteed.
In order to achieve the purpose, the technical scheme of the invention is as follows:
an IGBT device having a PNP punch-through transistor, the whole cell of which is symmetrical about the cell center line; the cell structure comprises a metal electrode 7, a P + collector region 6, an N-type buffer layer 5 and an N-drift region 4 which are sequentially stacked from bottom to top; the metal emitter 9, the metal electrode 16 and the metal connecting line 17 are positioned above the N-drift region 4; a discrete floating Pbody region 8 is arranged in the middle area of the top layer of the N-drift region 4, an N-type second base region 12 is arranged in the middle area of the top layer inside the discrete floating Pbody region 8, and a P-type second collector region 13 is arranged in the middle area of the top layer inside the N-type second base region 12; the P-type second collector region 13, the N-type second base region 12 and the discrete floating Pbody region 8 form a PNP triode structure; one or more diodes formed by N + polysilicon 14 and P + polysilicon 15 are arranged between the metal emitter 9 and the metal electrode 16, and the diodes are connected through a metal connecting wire 17; the lower part of the diode formed by the N + polysilicon 14 and the P + polysilicon 15 is isolated from the N-drift region 4 through a dielectric layer 11; the P + base region 2 and the N + emitter region 1 are both contacted with a metal emitter electrode 9; a grid structure is arranged between the P + base region 2, the N + emitter region 1 and the discrete floating Pbody region 8, the grid structure comprises a grid electrode 10 and a grid dielectric layer 3, the grid dielectric layer 3 extends into the N-drift region 4 along the vertical direction of the device to form a groove, and the grid electrode 10 is arranged in the groove; one side of the gate dielectric layer 3 is in contact with the P + base region 2, the N + emitter region 1 and the N-drift region 4, and the other side of the gate dielectric layer 3 is isolated from the discrete floating Pbody region 8 through the N-drift region 4.
Preferably, the base region of the triode is not fully depleted under the on-state condition of the device by controlling the thickness and doping concentration of the triode formed by the P-type second collector region 13, the N-type second base region 12 and the discrete floating Pbody region 8.
Preferably, the junction depth of the discrete floating Pbody regions 8 is greater than the depth of the gate structure.
Preferably, the doping mode of the P-type second collector region 13 is non-uniform doping or uniform doping; and the effective base region thickness of the doped lower boundary of the N-type second base region 9 is smaller than the transverse extension length thereof.
Preferably, the junction depth difference between the doped lower boundary of the discrete floating Pbody region 8 and the N-type second base region 12 is smaller than the lateral extension length thereof.
The doping of the discrete floating Pbody regions 8 is preferably non-uniform or uniform.
Preferably, the semiconductor material used for the device is single crystal silicon, silicon carbide or gallium nitride.
The triode structure in the discrete floating Pbody area needs to meet the following conditions:
(1) the depth of the gate dielectric layer is smaller than that of the discrete floating Pbody area.
(2) The discrete floating Pbody regions are not fully depleted in either the device blocking state or the conducting state.
(3) The N-type second base region can not be completely exhausted in the conduction state, and the triode is in a complete blocking state.
Compared with the prior art, the invention has the beneficial effects that:
(1) according to the invention, the PNP triode is introduced into the discrete P + floating Pbody area and is equivalent to a hole access switch; when the device is conducted in the forward direction, the PNP triode is in a blocking state, holes can be stored, and the saturation conduction voltage drop of the device is reduced; in the switching process of the device, the PNP triode penetrates through the device to provide a discharge path for a hole, so that the turn-off time and the turn-off loss are reduced; when the device is in a blocking state, the PNP triode penetrates through the device, so that the potential of the discrete P + floating Pbody area is reduced, and the breakdown voltage is increased.
(2) The invention further reduces the leakage current of the PNP triode by connecting one or more diodes in series with the metal electrode.
Drawings
FIG. 1 is a schematic structural diagram of a conventional discrete floating Pbody area IGBT device;
fig. 2 is a schematic structural diagram of an IGBT device having a PNP punch-through transistor according to the present invention;
fig. 3 is an equivalent circuit diagram of an IGBT device with a PNP punch-through transistor according to the present invention;
in the figure: the structure comprises a substrate, a gate dielectric layer, an N-drift region, an N-type buffer layer, a P + collector region, a metal collector region, a discrete floating Pbody region, a metal emitter electrode, a gate electrode, a dielectric layer, a second base region, a P-type collector region, a polysilicon layer, a P + polysilicon layer, a P electrode, a metal electrode and a metal connecting line, wherein the substrate 1 is an N + emitter region, the substrate 2 is a P + base region, the gate dielectric layer is 3, the N-drift region is 4, the N-type buffer layer is 5, the P.
Detailed Description
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.
An IGBT device having a PNP punch-through transistor, the whole cell of which is symmetrical about the cell center line; the cell structure comprises a metal electrode 7, a P + collector region 6, an N-type buffer layer 5 and an N-drift region 4 which are sequentially stacked from bottom to top; the metal emitter 9, the metal electrode 16 and the metal connecting line 17 are positioned above the N-drift region 4; a discrete floating Pbody region 8 is arranged in the middle area of the top layer of the N-drift region 4, an N-type second base region 12 is arranged in the middle area of the top layer inside the discrete floating Pbody region 8, and a P-type second collector region 13 is arranged in the middle area of the top layer inside the N-type second base region 12; the P-type second collector region 13, the N-type second base region 12 and the discrete floating Pbody region 8 form a PNP triode structure; one or more diodes formed by N + polysilicon 14 and P + polysilicon 15 are arranged between the metal emitter 9 and the metal electrode 16, and the diodes are connected through a metal connecting wire 17; the lower part of the diode formed by the N + polysilicon 14 and the P + polysilicon 15 is isolated from the N-drift region 4 through a dielectric layer 11; the P + base region 2 and the N + emitter region 1 are both contacted with a metal emitter electrode 9; a grid structure is arranged between the P + base region 2, the N + emitter region 1 and the discrete floating Pbody region 8, the grid structure comprises a grid electrode 10 and a grid dielectric layer 3, the grid dielectric layer 3 extends into the N-drift region 4 along the vertical direction of the device to form a groove, and the grid electrode 10 is arranged in the groove; one side of the gate dielectric layer 3 is in contact with the P + base region 2, the N + emitter region 1 and the N-drift region 4, and the other side of the gate dielectric layer 3 is isolated from the discrete floating Pbody region 8 through the N-drift region 4.
Specifically, the base region of the triode cannot be completely exhausted under the on-state condition of the device by controlling the thickness and the doping concentration of the triode formed by the P-type second collector region 13, the N-type second base region 12 and the discrete floating Pbody region 8.
Specifically, the junction depth of the discrete floating Pbody regions 8 is greater than the depth of the gate structure.
Specifically, the doping mode of the P-type second collector region 13 is non-uniform doping or uniform doping; and the effective base region thickness of the doped lower boundary of the N-type second base region 9 is smaller than the transverse extension length thereof.
Specifically, the junction depth difference between the doped lower boundary of the discrete floating Pbody region 8 and the doped lower boundary of the N-type second base region 12 is smaller than the lateral extension length thereof.
Specifically, the doping mode of the discrete floating Pbody region 8 is non-uniform heavy doping or uniform heavy doping.
Specifically, the semiconductor material used by the device is monocrystalline silicon, silicon carbide or gallium nitride. The principles of the present invention are described in detail below with reference to examples:
when the structure is blocked in the forward direction, the IGBT grid electrode is zero potential, the triode is in a through state, the discrete floating Pbody area 8 is directly connected with the ground through the through triode and a forward bias diode, namely the through structure FP is grounded, and the withstand voltage of a PN junction formed by the floating Pbody/N-drift area 4 is increased; and because the junction depth of the discrete floating Pbody region 8 is greater than that of the gate dielectric layer 3, the electric field at the bottom of the trench gate can be weakened, and the breakdown voltage of the device can be improved. In contrast, in the conventional discrete floating Pbody area IGBT structure shown in fig. 1, the discrete floating Pbody area 8 stores holes when conducting in the forward direction, and the holes can only be discharged through the P + base region when being turned off, so that the length of a discharging path is increased, and the turn-off time and turn-off loss are increased; meanwhile, in a blocking state, the discrete floating Pbody area floats, the internal potential of the discrete floating Pbody area is higher than that of the structure of the invention, and the discrete floating Pbody area 8 is grounded through a diode, so that the blocking voltage of the discrete floating Pbody area is lower than that of the structure of the invention.
When the structure is conducted, the FP potential is not enough to enable the triode to be penetrated, and the IGBT device with the PNP penetrating triode and the IGBT structure with the traditional discrete floating Pbody area can accumulate enough holes in the discrete floating Pbody area 8 when the device is conducted, so that the device has lower saturation voltage drop.
When the structure is turned off, because the hole in the device body needs to be discharged, the potential of the discrete floating Pbody area 8 is raised in the discharging process, when the voltage which enables the punch-through triode to pass through is reached, the discharging path is opened, the hole flows out from the metal electrode 16, and the excess hole stored in the device can be extracted more quickly, so that the switching time and the switching loss can be effectively reduced.
The structure of the device provided by the invention determines that the device can realize sufficient and reliable forward blocking capability, improves the latch-up resistance of a P-base region, improves the gate control capability of the device, realizes shorter switching time and reduces the switching loss.
In summary, compared with the conventional structure, the IGBT device with the PNP punch-through triode according to the present invention introduces a hole path that can change with the switch; the voltage resistance can be maintained in a blocking state, and the hole path is closed in a conducting state, so that the conductance modulation effect can be enhanced; in the turn-off process, the cavity passage is opened, so that the discharge speed is increased, the turn-off time is shortened, and the turn-off loss is reduced.
It should be noted that the IGBT device with PNP punch-through transistor in the present invention is not only suitable for the currently commonly used high voltage IGBT device of 3300V-6500V, but also suitable for the IGBT device based on the medium voltage range of the planar gate and the trench gate.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.

Claims (7)

1. An IGBT device with PNP punch-through triode, its characterized in that: the whole cell is symmetrical about the cell midline; the cell structure comprises a metal electrode (7), a P + collector region (6), an N-type buffer layer (5) and an N-drift region (4) which are sequentially stacked from bottom to top; the metal emitter (9), the metal electrode (16) and the metal connecting line (17) are positioned above the N-drift region (4); a discrete floating Pbody region (8) is arranged in the middle area of the top layer of the N-drift region (4), an N-type second base region (12) is arranged in the middle area of the top layer inside the discrete floating Pbody region (8), and a P-type second collector region (13) is arranged in the middle area of the top layer inside the N-type second base region (12); the P-type second collector region (13), the N-type second base region (12) and the discrete floating Pbody region (8) form a PNP triode structure; one or more diodes formed by N + polycrystalline silicon (14) and P + polycrystalline silicon (15) are arranged between the metal emitter (9) and the metal electrode (16), and the diodes are connected through a metal connecting wire (17); the lower part of the diode formed by the N + polysilicon (14) and the P + polysilicon (15) is isolated from the N-drift region (4) through a dielectric layer (11); the P + base region (2) and the N + emitter region (1) are both contacted with the metal emitter (9); a grid structure is arranged between the P + base region (2), the N + emitter region (1) and the discrete floating Pbody region (8), the grid structure comprises a grid electrode (10) and a grid dielectric layer (3), the grid dielectric layer (3) extends into the N-drift region (4) along the vertical direction of the device to form a groove, and the grid electrode (10) is arranged in the groove; one side of the gate dielectric layer (3) is in contact with the P + base region (2), the N + emitter region (1) and the N-drift region (4), and the other side of the gate dielectric layer (3) is isolated from the discrete floating Pbody region (8) through the N-drift region (4).
2. An IGBT device with a PNP punch-through transistor according to claim 1 wherein: the base region of the triode cannot be completely exhausted under the on-state condition of the device by controlling the thickness and the doping concentration of the triode formed by the P-type second collector region (13), the N-type second base region (12) and the discrete floating Pbody region (8).
3. An IGBT device with a PNP punch-through transistor according to claim 1 wherein: the junction depth of the discrete floating Pbody region (8) is greater than the depth of the gate structure.
4. An IGBT device with a PNP punch-through transistor according to claim 1 wherein: the doping mode of the P-type second collector region (13) is non-uniform doping or uniform doping; and the effective base region thickness of the doped lower boundary of the N-type second base region (12) is smaller than the transverse extension length of the doped lower boundary of the N-type second base region.
5. An IGBT device with a PNP punch-through transistor according to claim 1 wherein: the junction depth difference between the doping lower boundaries of the discrete floating Pbody region (8) and the N-type second base region (12) is smaller than the lateral extension length of the discrete floating Pbody region.
6. An IGBT device with a PNP punch-through transistor according to claim 1 wherein: the doping mode of the discrete floating Pbody area (8) is non-uniform heavy doping or uniform heavy doping.
7. An IGBT device with a PNP punch-through transistor according to any of claims 1 to 6 wherein: the semiconductor material used by the device is monocrystalline silicon, silicon carbide or gallium nitride.
CN201910572446.4A 2019-06-28 2019-06-28 IGBT device with PNP punch-through triode Expired - Fee Related CN110265477B (en)

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