CN110277444B - Trench gate IGBT device with SCR structure - Google Patents

Trench gate IGBT device with SCR structure Download PDF

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CN110277444B
CN110277444B CN201910574377.0A CN201910574377A CN110277444B CN 110277444 B CN110277444 B CN 110277444B CN 201910574377 A CN201910574377 A CN 201910574377A CN 110277444 B CN110277444 B CN 110277444B
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scr structure
dielectric layer
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CN110277444A (en
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李泽宏
孙肇峰
莫佳宁
赵一尚
杨洋
何云娇
彭鑫
任敏
高巍
张金平
张波
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University of Electronic Science and Technology of China
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    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
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    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0259—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using bipolar transistors as protective elements
    • H01L27/0262—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using bipolar transistors as protective elements including a PNP transistor and a NPN transistor, wherein each of said transistors has its base coupled to the collector of the other transistor, e.g. silicon controlled rectifier [SCR] devices
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
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    • H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
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    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
    • H01L29/7395—Vertical transistors, e.g. vertical IGBT
    • H01L29/7396—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions
    • H01L29/7397—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT

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Abstract

The invention belongs to the technical field of power semiconductors, and particularly relates to a trench gate IGBT device with an SCR structure.A P-type region, a first N-type region, a second N-type region and a discrete floating Pbody region form an SCR structure between symmetrical trench dielectric layers in the discrete floating Pbody region; when the device is conducted in the forward direction, the SCR structure is not conducted, holes are stored to enhance conductance modulation, and a diode is connected in series with the metal electrode to further reduce leakage current; when the circuit is turned off, a cavity discharge channel is provided, the turn-off time is reduced, and the switching time and the switching loss are reduced under the condition that other electrical characteristics are not influenced; and when the device is in a blocking state, the SCR structure penetrates through the device, so that the voltage resistance of the device is improved.

Description

Trench gate IGBT device with SCR structure
Technical Field
The invention belongs to the technical field of power semiconductors, and particularly relates to a trench gate IGBT device with an SCR structure.
Background
Insulated Gate Bipolar Transistor (IGBT) is a composite voltage-controlled power device created by absorbing the advantages of BJT (Bipolar Transistor) and MOSFET (Insulated Gate field effect Transistor). The IGBT has the advantages of low driving power of the MOSFET, high input impedance, high density of BJT carriers, and low on-state voltage drop, and is widely used in inverters and frequency converters, which are also core components in micro-grids, electric vehicles, renewable energy systems, and UPSs (uninterruptible power supplies).
Since the birth of 1980 s, IGBTs have been developed toward lower power consumption, better temperature characteristics, and wider SOA (safe operating area), and have undergone technological change for many generations. A Trench gate + FS (Field Stop) structure is an IGBT structure that is mainstream at present. Compared with a Planar gate IGBT, the introduction of the Trench structure eliminates a parasitic JFET area of the Planar structure on one hand, and effectively reduces saturation voltage drop; on the other hand, the Trench structure further reduces the size of the unit cell, improves the channel density and increases the current capacity of the IGBT. But also results in a significant reduction in its short circuit resistance. For this reason, new structures are continuously proposed to solve the short-circuit problem, one of which is to introduce an FP (Floating-Pbody) structure between two trench gates, to improve the short-circuit capability by reducing the channel density, and to move the location of breakdown from the trench gate bottom to the FP edge, while improving the blocking capability. Due to the introduction of the FP structure, the potential of the FP region changes in the starting and the closing processes of the Trench-IGBT, the effective grid voltage is reduced due to the generated displacement current, and the grid control capability of the IGBT is weakened. In order to improve the situation, a Separate Floating P region (separating Pbody) is proposed to be changed into an FP structure, so that the P region is separated from the groove gate, the displacement current cannot act on the gate electrode, the effect of reducing the peak electric field at the bottom of the groove gate is achieved, the conductance modulation is enhanced, and the Eoff-Vcesat compromise relation is improved. But more carriers are stored in the on-state of the device due to the enhanced conductance modulation, resulting in increased turn-off losses and affecting the blocking characteristics. If the discrete floating P region is grounded, the turn-off loss can be effectively reduced, the blocking characteristic can be improved, and the forward saturation voltage drop can be increased.
Disclosure of Invention
In view of the above, the present invention provides an IGBT device having an SCR (Silicon Controlled Rectifier) structure, which is directed to the problems of large device on-state characteristics, large switching loss, and the like of the existing TIGBT device with a discrete floating P region. Forming a hole carrier channel in the SCR structure in the trench by forming the trench in the discrete FP; under the blocking state, the PNP triode in the SCR is penetrated through, and the discrete FP potential is pulled down, so that the blocking capability is effectively improved; the change of the inner potential of the FP in the turn-off process enables the punch-through triode to be started in the turn-off process, so that the SCR is started, a cavity leakage path is provided, and the turn-off loss is reduced; the SCR can not be started in a normal conduction state, and the conduction characteristic and the EMI resistance of the device are ensured.
In order to achieve the purpose, the technical scheme of the invention is as follows:
a trench gate IGBT device with an SCR structure is characterized in that the whole cell is symmetrical about the cell center line; the cell structure comprises a metal electrode 7, a P + collector region 6, an N-type buffer layer 5 and an N-drift region 4 which are sequentially stacked from bottom to top; the metal emitter 9, the metal connecting wire 19 and the metal electrode 18 are positioned above the N-drift region 4; a discrete floating Pbody area 8 is arranged in the middle area of the top layer of the N-drift area 4, a first N-type area 14, a P-type area 13 and a second N-type area 15 are sequentially arranged in the middle area of the top layer in the discrete floating Pbody area 8 from bottom to top, groove dielectric layers 12 are symmetrically arranged on two sides of the P-type area 13, the first N-type area 14 and the second N-type area 15, the P-type area 13 is positioned above the inner part of the first N-type area 14, the second N-type area 15 is positioned above the inner part of the P-type area 13, and the P-type area 13, the first N-type area 14, the second N-type area 15 and the discrete floating Pbody area 8 form an SCR structure; one or more diodes formed by N + polysilicon 16 and P + polysilicon 17 are arranged between the metal emitter 9 and the metal electrode 18, and the diodes are connected through a metal connecting wire 19; the lower part of the diode formed by the N + polysilicon 16, the P + polysilicon 17 and the metal connecting line 19 is isolated from the N-drift region 4 through the dielectric layer 11; the P + base region 2 and the N + emitter region 1 are both contacted with a metal emitter electrode 9; a gate structure is arranged between the P + base region 2, the N + emitter region 1 and the discrete floating Pbody region 8, the gate structure comprises a gate electrode 10 and a gate dielectric layer 3, the gate dielectric layer 3 extends into the N-drift region 4 along the vertical direction of the device to form a groove, and the gate electrode 10 is arranged in the groove; one side of the gate dielectric layer 3 is in contact with the P + base region 2, the N + emitter region 1 and the N-drift region 4, and the other side of the gate dielectric layer 3 is isolated from the discrete floating Pbody region 8 through the N-drift region 4.
Preferably, the SCR formed by the P-type region 13, the first N-type region 14, the second N-type region 15 and the discrete floating Pbody region 8 will not turn on under device on-state conditions.
Preferably, the depth of the trench dielectric layer 12 is greater than or equal to the junction depth of the first N-type region 14. The depth of the trench dielectric layer 12 is less than or equal to that of the gate dielectric layer 3.
Preferably, the distance between the trench dielectric layers 12 is greater than or equal to the width of the metal electrode 18.
Preferably, the trench dielectric layer 12 is located in the neutral region of the discrete floating Pbody region 8 in the blocking state.
Preferably, the doping of the P-type region 13 is non-uniform doping or uniform doping.
Preferably, the first N-type region 14 is doped non-uniformly or uniformly.
Preferably, the doping of the second N-type region 15 is non-uniform doping or uniform doping.
The doping of the discrete floating Pbody regions 8 is preferably non-uniform or uniform.
Preferably, the semiconductor material used for the device is single crystal silicon, silicon carbide or gallium nitride.
The triode structure in the discrete floating Pbody area 8 of the invention needs to meet the following conditions:
(1) the depth of the trench dielectric layer 12 is greater than the depth of the first N-type region 14.
(2) The discrete floating Pbody region 8 is separated from the trench dielectric layer 12 in the device blocking state or conducting state.
(3) The on-state N-type base region 11 cannot be completely depleted and the SCR is in a complete blocking state.
Compared with the prior art, the invention has the beneficial effects that:
1. according to the invention, the SCR is introduced into the discrete floating Pbody area 8 and is equivalent to a cavity access switch; when the device is in forward conduction, the SCR is in a blocking state, holes can be stored, and the saturation conduction voltage drop of the device is reduced; in the switching process of the device, the SCR penetrates through the device to provide a discharge passage for the cavity, so that the turn-off time and turn-off loss are reduced; in the blocking state of the device, the SCR is communicated, so that the potential of the discrete floating Pbody area is reduced, and the breakdown voltage is increased.
2. The invention further reduces SCR leakage current by connecting one or more diodes in series with the metal electrode.
3. The groove dielectric layers 12 on the two sides of the SCR structure provided by the invention avoid latch-up of the SCR structure formed by the P-type region 13, the first N-type region 14, the second N-type region 15 and the discrete floating Pbody region 8, and adopt the same process as a groove gate, so that the manufacturing process is compatible with the manufacturing process of the existing high-voltage IGBT device.
Drawings
FIG. 1 is a schematic structural diagram of a conventional discrete floating Pbody area IGBT device;
FIG. 2 is a schematic structural diagram of an IGBT device with an SCR structure provided by the present invention;
FIG. 3 is an equivalent circuit diagram of an IGBT device with an SCR structure provided by the invention;
in fig. 2: the structure comprises an N + emitter region 1, a P + base region 2, a gate dielectric layer 3, an N-drift region 4, an N-type buffer layer 5, a P + collector region 6, a metal collector 7, a discrete floating Pbody region 8, a metal emitter 9, a gate electrode 10, a dielectric layer 11, a trench dielectric layer 12, a P-type region 13, a first N-type region 14, a second N-type region 15, N + polycrystalline silicon 16, P + polycrystalline silicon 17, a metal electrode 18 and a metal connecting line 19.
Detailed Description
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.
A trench gate IGBT device with an SCR structure is characterized in that the whole cell is symmetrical about the cell center line; the cell structure comprises a metal electrode 7, a P + collector region 6, an N-type buffer layer 5 and an N-drift region 4 which are sequentially stacked from bottom to top; the metal emitter 9, the metal connecting wire 19 and the metal electrode 18 are positioned above the N-drift region 4; a discrete floating Pbody area 8 is arranged in the middle area of the top layer of the N-drift area 4, a first N-type area 14, a P-type area 13 and a second N-type area 15 are sequentially arranged in the middle area of the top layer in the discrete floating Pbody area 8 from bottom to top, groove dielectric layers 12 are symmetrically arranged on two sides of the P-type area 13, the first N-type area 14 and the second N-type area 15, the P-type area 13 is positioned above the inner part of the first N-type area 14, the second N-type area 15 is positioned above the inner part of the P-type area 13, and the P-type area 13, the first N-type area 14, the second N-type area 15 and the discrete floating Pbody area 8 form an SCR structure; one or more diodes formed by N + polysilicon 16 and P + polysilicon 17 are arranged between the metal emitter 9 and the metal electrode 18, and the diodes are connected through a metal connecting wire 19; the lower part of the diode formed by the N + polysilicon 16, the P + polysilicon 17 and the metal connecting line 19 is isolated from the N-drift region 4 through the dielectric layer 11; the P + base region 2 and the N + emitter region 1 are both contacted with a metal emitter electrode 9; a gate structure is arranged between the P + base region 2, the N + emitter region 1 and the discrete floating Pbody region 8, the gate structure comprises a gate electrode 10 and a gate dielectric layer 3, the gate dielectric layer 3 extends into the N-drift region 4 along the vertical direction of the device to form a groove, and the gate electrode 10 is arranged in the groove; one side of the gate dielectric layer 3 is in contact with the P + base region 2, the N + emitter region 1 and the N-drift region 4, and the other side of the gate dielectric layer 3 is isolated from the discrete floating Pbody region 8 through the N-drift region 4.
Specifically, the SCR formed by the P-type region 13, the first N-type region 14, the second N-type region 15 and the discrete floating Pbody region 8 will not turn on under the on-state condition of the device.
Specifically, the depth of the trench dielectric layer 12 is greater than or equal to the junction depth of the first N-type region 14.
Specifically, the depth of the trench dielectric layer 12 is less than or equal to the depth of the gate dielectric layer 3.
Specifically, the distance between the trench dielectric layers 12 is greater than or equal to the width of the metal electrode 18.
Specifically, the trench dielectric layer 12 is located in the neutral region of the discrete floating Pbody region 8 in the blocking state.
Specifically, the doping manner of the P-type region 13 is non-uniform doping or uniform doping.
Specifically, the doping manner of the first N-type region 14 is non-uniform doping or uniform doping.
Specifically, the doping manner of the second N-type region 15 is non-uniform doping or uniform doping.
Specifically, the doping mode of the discrete floating Pbody region 8 is non-uniform heavy doping or uniform heavy doping.
Specifically, the semiconductor material used by the device is monocrystalline silicon, silicon carbide or gallium nitride.
The principles of the present invention are described in detail below with reference to examples:
when the structure is blocked in the forward direction, the IGBT grid electrode is zero potential, the SCR is in a through state at the moment, the discrete floating Pbody area 8 is directly connected with the ground through the through SCR and a forward bias diode, namely the through structure FP is grounded, and the withstand voltage of a PN junction formed by the floating Pbody/N-drift area 4 is increased; and because the junction depth of the discrete floating Pbody region 8 is greater than that of the gate dielectric layer 3 and the trench dielectric layer 12, the electric field at the bottom of the trench gate can be weakened, and the breakdown voltage of the device can be improved. In contrast, in the conventional discrete floating Pbody area IGBT structure shown in fig. 1, the discrete floating Pbody area 8 stores holes when conducting in the forward direction, and the holes can only be discharged through the P + base region when being turned off, so that the length of a discharging path is increased, and the turn-off time and turn-off loss are increased; meanwhile, in a blocking state, the discrete floating Pbody area floats, the internal potential of the discrete floating Pbody area is higher than that of the proposed structure, and the discrete floating Pbody area 8 is grounded through a diode, so that the blocking voltage of the discrete floating Pbody area is lower than that of the proposed structure.
When the structure is conducted, the FP potential is not enough to lead a PNP triode in the SCR to pass through, and the SCR is in a blocking state. When the device is conducted, the IGBT device with the SCR structure can accumulate enough holes in the discrete floating Pbody area 8 as the traditional discrete floating Pbody area IGBT structure in a conducting state, so that the device has lower saturation voltage drop.
The structure that provides is when shutting down, owing to need the release at the internal hole of device, and the 8 electric potential lifts in the empty Pbody district of separation float in the process of releasing, when reaching the voltage that makes triode break-through in the SCR, the SCR opens, and the route of releasing is opened, and the hole flows out from metal electrode 18, and the surplus hole of the inside storage of device can be faster by the extraction, can effectual reduction on-off time and switching loss.
The structure of the device provided by the invention determines that the device can realize enough and reliable forward blocking capability, improves the grid control capability of the device, realizes shorter switching time and reduces the switching loss.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.

Claims (10)

1. The utility model provides a trench gate IGBT device with SCR structure which characterized in that: the whole cell is symmetrical about the cell midline; the cell structure comprises a metal electrode (7), a P + collector region (6), an N-type buffer layer (5) and an N-drift region (4) which are sequentially stacked from bottom to top; the metal emitter (9), the metal connecting wire (19) and the metal electrode (18) are positioned above the N-drift region (4); a discrete floating Pbody area (8) is arranged in the middle area of the top layer of the N-drift area (4), a first N-type area (14), a P-type area (13) and a second N-type area (15) are sequentially arranged in the middle area of the top layer of the discrete floating Pbody area (8) from bottom to top, groove dielectric layers (12) are symmetrically arranged on two sides of the P-type area (13), the first N-type area (14) and the second N-type area (15), the P-type area (13) is located above the inside of the first N-type area (14), the second N-type area (15) is located above the inside of the P-type area (13), and the P-type area (13), the first N-type area (14), the second N-type area (15) and the discrete floating Pbody area (8) form an SCR structure; one or more diodes formed by N + polysilicon (16) and P + polysilicon (17) are arranged between the metal emitter (9) and the metal electrode (18), and the diodes are connected through a metal connecting wire (19); the lower part of a diode formed by the N + polysilicon (16), the P + polysilicon (17) and the metal connecting line (19) is isolated from the N-drift region (4) through a dielectric layer (11); the P + base region (2) and the N + emitter region (1) are both contacted with the metal emitter (9); a grid structure is arranged between the P + base region (2), the N + emitter region (1) and the discrete floating Pbody region (8), the grid structure comprises a grid electrode (10) and a grid dielectric layer (3), the grid dielectric layer (3) extends into the N-drift region (4) along the vertical direction of the device to form a groove, and the grid electrode (10) is arranged in the groove; one side of the gate dielectric layer (3) is in contact with the P + base region (2), the N + emitter region (1) and the N-drift region (4), and the other side of the gate dielectric layer (3) is isolated from the discrete floating Pbody region (8) through the N-drift region (4).
2. The trench gate IGBT device with the SCR structure of claim 1, characterized in that: the SCR formed by the P-type region (13), the first N-type region (14), the second N-type region (15) and the discrete floating Pbody region (8) is not turned on under the on-state condition of the device.
3. The trench gate IGBT device with the SCR structure of claim 1, characterized in that: the depth of the groove dielectric layer (12) is larger than or equal to the junction depth of the first N-type region (14), and the depth of the groove dielectric layer (12) is smaller than or equal to the depth of the gate dielectric layer (3).
4. The trench gate IGBT device with the SCR structure of claim 1, characterized in that: the distance between the groove dielectric layers (12) is larger than or equal to the width of the metal electrode (18).
5. The trench gate IGBT device with the SCR structure of claim 1, characterized in that: the trench dielectric layer (12) is located in the neutral region of the discrete floating Pbody region (8) in the blocking state.
6. The trench gate IGBT device with the SCR structure of claim 1, characterized in that: the doping mode of the P-type region (13) is non-uniform doping or uniform doping.
7. The trench gate IGBT device with the SCR structure of claim 1, characterized in that: the first N-type region (14) is doped in a non-uniform manner or in a uniform manner.
8. The trench gate IGBT device with the SCR structure of claim 1, characterized in that: the doping mode of the second N-type region (15) is non-uniform doping or uniform doping.
9. The trench gate IGBT device with the SCR structure of claim 1, characterized in that: the doping mode of the discrete floating Pbody area (8) is non-uniform heavy doping or uniform heavy doping.
10. The trench gate IGBT device with an SCR structure of any one of claims 1 to 9, wherein: the semiconductor material used by the device is monocrystalline silicon, silicon carbide or gallium nitride.
CN201910574377.0A 2019-06-28 2019-06-28 Trench gate IGBT device with SCR structure Expired - Fee Related CN110277444B (en)

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