CN115528090A - Double-groove SiC MOSFET device - Google Patents

Double-groove SiC MOSFET device Download PDF

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Publication number
CN115528090A
CN115528090A CN202211123364.XA CN202211123364A CN115528090A CN 115528090 A CN115528090 A CN 115528090A CN 202211123364 A CN202211123364 A CN 202211123364A CN 115528090 A CN115528090 A CN 115528090A
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China
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region
gate
trench
oxide layer
sic mosfet
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Inventor
李明玥
刘�东
鲁啸龙
卢山
欧阳杰
廖云滔
彭莉莎
胡夏融
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Southwest Jiaotong University
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Southwest Jiaotong University
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Abstract

The invention provides a double-groove SiC MOSFET device, which belongs to the technical field of power semiconductor devices and comprises an N-type substrate, an N-type epitaxial layer, a polysilicon region, an L-shaped gate source region, a channel region, a P-type shielding region, a CSL region, an N + contact region, a thick gate oxide layer, a thin gate oxide layer and an isolation oxide layer. Through the design, the reverse conductivity of the SiC MOSFET can be improved, the reverse conductivity voltage can be reduced, and the bipolar degradation phenomenon can be avoided; the gate-drain capacitance and the gate-source capacitance of the SiC MOSFET can be reduced, and the switching speed of the SiC MOSFET is improved; the maximum electric field in the gate dielectric layer can be reduced, and the reliability of the device is improved.

Description

Double-groove SiC MOSFET device
Technical Field
The invention belongs to the technical field of power semiconductor devices, and particularly relates to a double-groove SiC MOSFET device.
Background
The SiC material represented by the third-generation semiconductor material has large forbidden band width, high critical breakdown electric field, high thermal conductivity, high carrier saturation drift rate and strong radiation resistance. By means of the physical properties of the SiC material, which are obviously superior to those of the Si material, the SiC device has a strong potential in the application fields of high voltage, high temperature, high frequency, strong radiation, etc., wherein the SiC MOSFET is more concerned and gradually occupies the market of the Si-based MOSFET.
In order to achieve the high-power and low-loss operation goal, the MOSFET device needs to be developed toward a higher channel density and a lower on-state resistance. The groove structure of the MOSFET device eliminates a JFET area, converts a horizontal channel into a vertical channel, can effectively reduce the size of a unit cell, can integrate more unit cells on a chip with a fixed area, and improves the withstand voltage of the device.
When the MOSFET device is actually used, a fast diode is usually required to be connected in an anti-parallel mode to inhibit a body diode and avoid a bipolar degradation phenomenon, and the extra diode not only increases the packaging size, but also increases parasitic inductance, so that the switching frequency of the MOSFET is limited. The anti-parallel diode is transferred from the outside of the MOSFET device to the inside of the cell structure to be a good choice, such as integrating an SBD/JBS into the MOSFET cell, but integrating a unipolar diode results in an increase in the forward leakage current of the device.
The structure of the SiC MOSFET groove gate has two corners, electric field lines are dense at the two corners, and when the structure is in a blocking state, the electric field at the corners is large, so that the critical breakdown electric field of a gate oxide layer is easily reached, gate oxide breakdown is caused, and the gate oxide reliability closely influences the withstand voltage of a device. Therefore, the reliability optimization of the SiC MOSFET device should focus on the gate oxide protection design, and a direct and effective means at present is to add a new structure below the gate oxide to modulate an electric field and reduce the maximum electric field borne by the gate oxide.
Disclosure of Invention
Aiming at the defects in the prior art, the double-groove SiC MOSFET device provided by the invention improves the reverse conductivity of the SiC MOSFET, reduces the reverse conductivity voltage and avoids the bipolar degradation phenomenon; the gate-drain capacitance and the gate-source capacitance of the SiC MOSFET are reduced, and the switching speed of the SiC MOSFET is improved; the maximum electric field in the gate dielectric layer is reduced, and the reliability of the device is improved.
In order to achieve the above purpose, the invention adopts the technical scheme that: a dual trench SiC MOSFET device comprising: the semiconductor device comprises an N-type substrate, an N-type epitaxial layer which is positioned above the N-type substrate in a convex shape and is internally provided with a groove, a CSL area positioned in the N-type epitaxial layer, a P-type shielding area which clamps the CSL area in the middle, an N + contact area positioned above the P-type shielding area, a P channel area positioned below the left N + contact area, an N channel area positioned below the right N + contact area, a thin gate oxide layer positioned on the inner wall of the groove, an L-type gate source area positioned above the thin gate oxide layer and partially filling the groove, a thick gate oxide layer positioned on the inner side of the L-type gate source area, a polycrystalline silicon area which is surrounded by the thick gate oxide layer and the thin gate oxide layer and fills the rest part of the groove, an isolation oxide layer positioned on the outer side of the polycrystalline silicon area and a metal layer positioned on the outer side of the isolation oxide layer.
The invention has the beneficial effects that: the invention provides a SiC double-channel MOSFET device integrating a low-barrier diode and an L-shaped grid source, which can effectively prevent bipolar degradation and simultaneously remarkably reduce grid-drain capacitance (C) gd ) And gate-drain charge (Q) gd ) The switching speed is greatly improved, and the switching loss is reduced. The invention embeds a low-barrier diode in the right half part of the cell, provides a current path when the device is conducted reversely, and can effectively reduceThe drift region has a hole concentration, thereby preventing bipolar degradation from occurring. An L-shaped gate source is embedded at the bottom of the trench gate, so that the overlap between the gate and the drain is reduced, and the reverse transmission capacitance (C) is reduced rss ) Lower switching losses are obtained. The invention also uses the heavily doped P-type shielding region extending to the lower part of the CSL region, expands a depletion layer in a blocking state, modulates the shape of an electric field, reduces leakage current and plays a better protection role on oxide, so that the reliability of the structure in the application in a high-voltage and high-frequency working environment is improved.
Furthermore, the N channel region adopts an N channel, and a low-barrier diode is integrated in the double-groove SiC MOSFET device.
The beneficial effects of the further scheme are as follows: a low-barrier diode is integrated in the device structure of the invention to improve the reverse conduction characteristic.
Still further, the N-channel region is thinner than the P-channel region.
The beneficial effects of the above further scheme are: the thickness of the N-channel region in the present invention is verified by simulation and is an optimal value obtained by balancing the relationship between the Blocking Voltage (BV) and the reverse conduction Voltage (VF) of the device.
And further, the L-shaped gate source region is separated to form a split gate.
The beneficial effects of the further scheme are as follows: in the invention, the source electrode extends into the groove and extends to the bottom of the grid electrode to form a split grid electrode, the overlap between the grid electrode and the drain electrode is reduced, and the grid-drain capacitance (C) gd ) And gate-drain charge (Q) gd ) The switching loss is remarkably reduced, and the switching loss is also remarkably reduced.
Still further, the P-type shielding region extends to below the CSL region.
The beneficial effects of the above further scheme are: through the design, the electric field peak is generated at the boundary of the high-doped P shielding region to redistribute the electric field of the device, thereby reducing the leakage current and the maximum oxide electric field Emax in the blocking state, protecting the oxide layer and improving the reliability of the device.
Still further, the thickness of the P-type shielding region is 0.3 μm, and the doping concentration is 2 × 10 18 cm -3 (ii) a The thickness of the P channel region is 0.5 μm, and the doping concentration is 2 × 10 17 cm -3 (ii) a The thickness of the N channel region is 0.2 μm, and the doping concentration is 3 × 10 15 cm -3 。
The beneficial effects of the further scheme are as follows: the thickness and the doping concentration of the P-type shielding region are set, so that the device is prevented from punch-through breakdown; the P channel region is arranged to separate the N + source region from the CSL region during reverse operation and prevent the N + source region and the CSL region from being conducted, and a channel is formed during forward operation to enable a device to be conducted; the N-channel region is provided to form a low barrier diode to improve reverse conduction characteristics.
And furthermore, the thickness of a thick gate oxide layer between the L-shaped gate source region and the polysilicon region is 0.1 mu m.
The beneficial effects of the further scheme are as follows: the thickness of the thick gate oxide layer between the L-shaped gate source region and the polysilicon region is set to ensure that the oxide layer is not broken down.
And furthermore, the grooves comprise a source electrode groove and a grid electrode groove, wherein the depth of the source electrode groove is 1.7 mu m, the depth of the grid electrode groove is 1.4 mu m, and the thickness of a thin grid oxide layer on the inner wall of the source electrode groove is 50nm.
The beneficial effects of the further scheme are as follows: the depth of the trench and the thickness of the oxide layer are selected to balance the Blocking Voltage (BV) and the dynamic characteristics.
Furthermore, the N-type substrate and the N-type epitaxial layer are both made of SiC materials, the gate trench is made of polysilicon, the L-type gate source region is made of metal, and the metal layer is made of A1.
The beneficial effects of the further scheme are as follows: the substrate and the epitaxial layer are made of SiC materials to improve the withstand voltage and power density of the device, and the selection of the grid groove, the L-shaped grid source region and the metal layer materials forms good ohmic contact to play a role in conducting.
Drawings
Fig. 1 is a schematic view of the device structure of the present invention.
Fig. 2 is a graph showing a logarithmic curve of blocking characteristics and an electric field distribution at a gate bias of 1200V for a conventional double channel MOSFET (DT-MOSFET) and a trench MOSFET of the present invention.
FIG. 3 is an I-V characteristic curve and reverse conduction I of a DT-MOSFET sd ＝100A/cm 2 Hole concentration of (g) is shown schematically.
FIG. 4 shows the I-V characteristic and reverse conduction I of the trench MOSFET of the present invention sd ＝100A/cm 2 Hole concentration in (g) is shown schematically.
FIG. 5 is a schematic diagram showing the C-V characteristics of a DT-MOSFET and a trench MOSFET of the present invention obtained when an AC voltage is applied to the drain electrode from 0V to 1000V at a frequency of 1 MHz.
FIG. 6 is a schematic diagram of the switching waveforms of a DT-MOSFET and a trench MOSFET of the present invention.
Fig. 7 is a graph showing the turn-on loss and turn-off loss waveforms for both the DT-MOSFET and the trench MOSFET of the present invention.
The structure comprises a 1-metal layer, a 2-N + contact region, a 3-polysilicon region, a 4-P channel region, a 5-N channel region, a 6-L type gate source region, a 7-CSL region, an 8-P type shielding region, a 9-N type epitaxial layer, a 10-N type substrate, an 11-isolation oxide layer, a 12-thick gate oxide layer and a 13-thin gate oxide layer.
Detailed Description
The following description of the embodiments of the present invention is provided to facilitate the understanding of the present invention by those skilled in the art, but it should be understood that the present invention is not limited to the scope of the embodiments, and it will be apparent to those skilled in the art that various changes may be made without departing from the spirit and scope of the invention as defined and defined by the appended claims, and all changes that can be made by the invention using the inventive concept are intended to be protected.
Examples
As shown in fig. 1, the present invention provides a double trench SiC MOSFET device comprising: the semiconductor device comprises an N-type substrate 10, an N-type epitaxial layer 9 which is positioned above the N-type substrate 10 in a convex shape and is provided with a groove, a CSL region 7 positioned inside the N-type epitaxial layer 9, a P-type shielding region 8 which clamps the CSL region 7 in the middle, an N + contact region 2 positioned above the P-type shielding region 8, a P-channel region 4 positioned below the N + contact region 2 on the left side, an N-channel region 5 positioned below the N + contact region 2 on the right side, a thin gate oxide layer 13 positioned on the inner wall of the groove, an L-type gate source region 6 positioned above the thin gate oxide layer 13 and partially filling the groove, a thick gate oxide layer 12 positioned on the inner side of the L-type gate source region 6, a polycrystalline silicon region 3 which is surrounded by the thick gate oxide layer 12 and the thin gate oxide layer 13 and fills the rest part of the groove, an isolation oxide layer 11 positioned on the outer side of the polycrystalline silicon region 3, and a metal layer 1 positioned on the outer side of the isolation oxide layer 11.
In this embodiment, an N-type epitaxial layer 9 is located above an N-type substrate 10, a trench is disposed in the N-type epitaxial layer 9, a CSL region 7 is located below the trench, P-type shielding regions 8 are located on two sides of the CSL layer 7, the trench is located between the trench and the P-type shielding regions 8, an N + contact region 2 is located above the trench and the P-type shielding regions 8, a thin gate oxide layer 13 covers an inner wall of the trench, an L-type gate source region 6 is located on a surface of the thin gate oxide layer 13 and partially fills the trench, a thick gate oxide layer 12 covers a surface of the L-type gate source region 6, a polysilicon region 3 is located on a surface of the thick gate oxide layer 12 and fills a remaining portion of the trench, an isolation oxide layer 11 covers a surface of the polysilicon region 3 and a surface of the N + contact region 2, and a metal 1 covers an outer portion of the isolation oxide layer 11. The channel region is divided into a P channel region and an N channel region, the P channel region is located on the left side, the N channel region is located on the right side, and the N channel region 5 is thinner than the P channel region 4.
In this embodiment, the N-channel region 5 is an N-channel and is integrated with a low barrier diode in a double trench SiC MOSFET device.
In this embodiment, the device uses a trench gate, and further, the gate of the present invention is a split gate formed by separating the L-shaped gate source region 6.
In this embodiment, the source extends into the trench and to the bottom of the gate to form a split gate, the overlap between the gate and the drain is reduced, and the gate-drain capacitance (C) is reduced gd ) And gate-drain charge (Q) gd ) The switching loss is remarkably reduced, and the switching loss is also remarkably reduced.
In this embodiment, the right channel is different from the conventional double-channel MOSFET, and an N channel is used, and a low barrier diode is integrated in the device structure to improve reverse conduction.
In this embodiment, the P-type shielding region 8 extends to the lower side of the CSL region 7, and an electric field peak is generated at the boundary of the highly doped P-type shielding region to redistribute the electric field of the device, thereby reducing the leakage current and the maximum oxide electric field Emax in the blocking state, protecting the oxide layer, and improving the reliability of the device.
In this embodiment, the thickness of the P-type shielding region 8 is 0.3 μm, and the doping concentration is 2 × 10 18 cm -3 And the device is ensured not to have punch-through breakdown.
In this embodiment, the thickness of the P channel region 4 is 0.5 μm, and the doping concentration is 2 × 10 17 cm -3 (ii) a The N-channel region 5 has a thickness of 0.2 μm and a doping concentration of 3 × 10 15 cm -3 。
In this embodiment, the thickness of the thick gate oxide layer 12 between the L-shaped gate source region 6 and the polysilicon region 3 is 0.1 μm;
in this embodiment, the trenches include a source trench and a gate trench, wherein the depth of the source trench is 1.7 μm, the depth of the gate trench is 1.4 μm, and the thickness of the thin gate oxide layer 13 on the inner wall of the source trench is 50nm.
In this embodiment, the N-type substrate 10 and the N-type epitaxial layer 9 are both made of SiC materials, the gate trench is made of polysilicon, the L-type gate source region 6 is made of metal, and the metal layer 1 is made of A1.
In this embodiment, as shown in fig. 2, from the blocking characteristic curve, the blocking voltage of both devices exceeds 1400V, and the leakage current of the trench MOSFET of the present invention is slightly larger than that of the DT-MOSFET because the N-type channel has a lower barrier than the P-type channel and electrons pass more easily. From the electric field distribution, the maximum electric fields of the two devices are both positioned on the gate oxide layer at the bottom of the trench, but the maximum electric field intensity of the DT-MOSFET is 3.97MV/cm, the maximum electric field intensity of the trench MOSFET is only 2.52MV/cm, only because the P-type shielding layer of the invention extends to the CSL, the gate oxide can be better protected by expanding the depletion layer, the reliability of the device is improved, and the maximum electric field intensity at the gate oxide position can be further reduced.
In this embodiment, it can be seen from fig. 3 that the trench MOSFET of the present invention has a reverse conduction voltage as small as 0.96V when the device is in the third quadrant operation state, and the reverse conduction voltage of the DT-MOSFET is 2.86V. As can be seen from fig. 4, the drift region of the DT-MOSFET obtains a high concentration of holes, while the trench MOSFET integrated low barrier diode of the present invention provides a current path for reverse conduction of the device, reducing the hole concentration in the drift region and acting to prevent bipolar degradation. Thus, the present invention improves reverse conduction of the device.
In this example, as shown in FIG. 5, the C of the DT-MOSFET at 1000V can be seen rss Is 141.68pF/cm 2 C of the trench MOSFET of the present invention rss The reduction is 99.6 percent and is only 0.43pF/cm 2 . FIG. 6 shows the switching waveforms of two devices, and it can be seen that the device provided by the present invention has a shorter Miller platform, and the gate charge required for the gate voltage to reach 15V is smaller, V gs The ascending and descending speeds are faster; FIG. 7 waveforms of turn-on loss and turn-off loss of two devices, turn-on loss of DT-MOS (E) on ) And turn-off loss (E) off ) Are respectively 0.93mJ/cm 2 And 0.49mJ/cm 2 . However, for the trench MOSFET of the present invention, E on And E off Respectively reduced to 0.59mJ/cm 2 And 0.37mJ/cm 2 36.56% and 24.49% lower than DT-MOS. As can be seen from a combination of fig. 5, 6 and 7, the device of the present invention reduces the overlap between the gate electrode and the drain electrode, reducing C rss The invention has the advantages of better switching speed and lower switching loss, and the invention improves the switching speed and reduces the switching loss.

Claims (9)

1. A dual trench SiC MOSFET device, comprising: the structure comprises an N-type substrate (10), an N-type epitaxial layer (9) which is positioned above the N-type substrate (10) in a convex shape and is provided with a groove, a CSL region (7) positioned in the N-type epitaxial layer (9), a P-type shielding region (8) which clamps the CSL region (7) in the middle, an N + contact region (2) positioned above the P-type shielding region (8), a P channel region (4) positioned below the left N + contact region (2), an N channel region (5) positioned below the right N + contact region (2), a thin gate oxide layer (13) positioned on the inner wall of the groove, an L-type gate source region (6) which is positioned above the thin gate oxide layer (13) and is partially filled with the groove, a thick gate oxide layer (12) positioned on the inner side of the L-type gate source region (6), a polycrystalline silicon region (3) which is surrounded by the thick gate oxide layer (12) and the thin gate oxide layer (13) and is filled with the rest part of the groove, an isolation oxide layer (11) positioned on the outer side of the polycrystalline silicon region (3), and a metal layer (1) positioned on the outer side of the isolation oxide layer (11).
2. The double trench SiC MOSFET device of claim 1, wherein the N-channel region (5) is an N-channel and integrates a low barrier diode in the double trench SiC MOSFET device.
3. The double trench SiC MOSFET device of claim 2, wherein the N-channel region (5) is thinner than the P-channel region (4).
4. The double trench SiC MOSFET device of claim 3, wherein the L-shaped gate source regions (6) are separated to form split gates.
5. The double trench SiC MOSFET device of claim 4, wherein the P-type shield region (8) extends below the CSL region (7).
6. Double trench SiC MOSFET device according to claim 5, wherein the P-type shielding region (8) has a thickness of 0.3 μm and a doping concentration of 2 x 10 18 cm -3 (ii) a The thickness of the P channel region (4) is 0.5 μm, and the doping concentration is 2 × 10 17 cm -3 (ii) a The thickness of the N channel region (5) is 0.2 μm, and the doping concentration is 3 × 10 15 cm -3 。
7. The double trench SiC MOSFET device of claim 6, wherein the thick gate oxide layer (12) between the L-shaped gate source region (6) and the polysilicon region (3) has a thickness of 0.1 μ ι η.
8. The double trench SiC MOSFET device of claim 7, wherein the trenches comprise a source trench and a gate trench, wherein the source trench depth is 1.7 μm, the gate trench depth is 1.4 μm, and the thin gate oxide layer (13) on the inner wall of the source trench is 50nm thick.
9. The double-trench SiC MOSFET device as claimed in claim 8, wherein the N-type substrate (10) and the N-type epitaxial layer (9) are both made of SiC, the gate trench is made of polysilicon, the L-shaped gate source region (6) is made of metal, and the metal layer (1) is made of A1.
CN202211123364.XA 2022-09-15 2022-09-15 Double-groove SiC MOSFET device Pending CN115528090A (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116190451A (en) * 2023-04-18 2023-05-30 杭州芯迈半导体技术有限公司 Gate-source structure and manufacturing method thereof, asymmetric trench MOSFET and manufacturing method thereof
CN116190451B (en) * 2023-04-18 2024-05-03 杭州芯迈半导体技术有限公司 Gate-source structure and manufacturing method thereof, asymmetric trench MOSFET and manufacturing method thereof

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116190451A (en) * 2023-04-18 2023-05-30 杭州芯迈半导体技术有限公司 Gate-source structure and manufacturing method thereof, asymmetric trench MOSFET and manufacturing method thereof
CN116190451B (en) * 2023-04-18 2024-05-03 杭州芯迈半导体技术有限公司 Gate-source structure and manufacturing method thereof, asymmetric trench MOSFET and manufacturing method thereof

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