CN111933711B - SBD integrated super-junction MOSFET - Google Patents
SBD integrated super-junction MOSFET Download PDFInfo
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- CN111933711B CN111933711B CN202010831004.XA CN202010831004A CN111933711B CN 111933711 B CN111933711 B CN 111933711B CN 202010831004 A CN202010831004 A CN 202010831004A CN 111933711 B CN111933711 B CN 111933711B
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- 239000004065 semiconductor Substances 0.000 claims abstract description 9
- 239000004020 conductor Substances 0.000 claims description 21
- 239000000758 substrate Substances 0.000 claims description 14
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 13
- 239000002184 metal Substances 0.000 claims description 12
- 239000000463 material Substances 0.000 claims description 7
- 229920005591 polysilicon Polymers 0.000 claims description 7
- 229910005191 Ga 2 O 3 Inorganic materials 0.000 claims description 3
- 230000015556 catabolic process Effects 0.000 abstract description 3
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 17
- 229910010271 silicon carbide Inorganic materials 0.000 description 17
- 230000000903 blocking effect Effects 0.000 description 11
- 238000000034 method Methods 0.000 description 3
- 229910002601 GaN Inorganic materials 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000005684 electric field Effects 0.000 description 2
- 229910003465 moissanite Inorganic materials 0.000 description 2
- 238000004088 simulation Methods 0.000 description 2
- 230000003068 static effect Effects 0.000 description 2
- 230000004888 barrier function Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000001413 cellular effect Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000006731 degradation reaction Methods 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
Abstract
The invention belongs to the technical field of power semiconductors, and particularly relates to a super junction MOSFET integrated with an SBD. Compared with the traditional structure, the invention has the following characteristics: the device adopts a double-groove structure, namely a groove gate structure and a Schottky groove type structure, Schottky contact is introduced into the groove side wall of the Schottky groove type structure, so that the layout area can be effectively saved, and the follow current capability can be increased; secondly, a transversely-extending P-type shielding layer is introduced below the double grooves to protect the double grooves, so that reverse leakage current of the integrated Schottky diode can be inhibited, Schottky contact and the bottom of a groove gate are prevented from being broken down in advance, and breakdown voltage is effectively improved; and thirdly, the drift region adopts a super junction structure, so that the problem of low current capability caused by a P-type shielding layer is effectively solved. Compared with the traditional SiC MOSFET structure integrated with SBD, the SiC MOSFET structure has the advantages that the layout area can be saved, the follow current capability is enhanced, the starting capability of a body diode is restrained, and meanwhile, the SiC MOSFET structure has lower conduction voltage drop and higher breakdown voltage.
Description
Technical Field
The invention belongs to the technical field of power semiconductors, and relates to a low-loss super-junction MOSFET (metal-oxide-semiconductor field effect transistor) integrating an SBD (Schottky Barrier Diode).
Background
The SiC MOSFET has good static and dynamic characteristics due to the excellent characteristics of the silicon carbide material, but the body diode of the SiC MOSFET has higher turn-on voltage due to the larger forbidden band width; meanwhile, the SiC MOSFET has a phenomenon of bipolar degradation, that is, conduction of the body diode increases defects in the drift region, thereby causing an increase in on-resistance. Therefore, the body diode should be prevented from turning on during freewheeling. Because the SBD has a lower conduction voltage drop than the PN junction diode, the existing methods usually use an anti-parallel SBD to prevent the SiC MOSFET body diode from turning on. However, external SiC SBDs introduce additional parasitic inductance and capacitance, which greatly affects the switching performance of SiC MOSFETs. Meanwhile, the external SiC SBD also increases the packaging cost and increases the module volume. Therefore, the MOSFET integrated SBD becomes a focus of attention, however, the integrated SBD restricts the blocking capability of the SiC MOSFET device due to its large reverse leakage current and low reverse withstand voltage, and the integrated SBD occupies the surface area of the chip, limiting the utilization rate of the chip area.
Disclosure of Invention
The invention aims to solve the problems and provides a low-loss super-junction MOSFET integrated with an SBD, which can have higher blocking voltage and stronger follow current capability while ensuring low on-state voltage drop of the MOSFET integrated with the SBD and saves layout area.
The technical scheme of the invention is as follows: a low-loss super-junction MOSFET integrated with an SBD comprises an N + substrate layer 2, a drift region positioned above the N + substrate layer 2, a trench gate structure, a source electrode structure and a Schottky trench type structure, wherein the trench gate structure, the source electrode structure and the Schottky trench type structure are positioned above the drift region; a first conductive material 1 connected with the substrate layer 2 is arranged below the substrate layer, and the first conductive material 1 is led out to be a drain electrode; the drift region is composed of N-type strip regions 3 and P-type strip regions 4 which are transversely arranged at equal intervals in an alternating mode; the groove gate structure is positioned above the P-type strip region 4 and comprises a first insulating medium layer 6 positioned at the bottom and the side wall of the groove and N + polycrystalline silicon 7 in the groove, the side surface and the bottom of the N + polycrystalline silicon 7 are surrounded by the first insulating medium layer 6, the top of the N + polycrystalline silicon 7 is provided with a second conductive material 13 connected with the N + polycrystalline silicon, and the second conductive material 13 is led out to form a gate; the source electrode structure is positioned at the top of the drift region and on two sides of the trench gate structure and comprises a P-type base region 8, a P + source contact region 9 and an N + source region 10 which are transversely arranged in parallel and positioned at the top of the P-type base region 8, the P-type base region 8 and the N + source region 10 are transversely contacted with the first insulating medium layer 6, a third conductive material 12 is arranged at the tops of the P + source contact region 9 and the N + source region 10, and the third conductive material 12 is led out to be a source electrode; the Schottky groove type structure is positioned above the P-type strip region 4 on the outer side of the source electrode structure and comprises metal 11 positioned on the side wall of the groove and a second insulating medium layer 14 in the groove, and the metal 11 and the N-type strip region 3 form Schottky contact;
p-type shielding layers 5 are arranged between the Schottky groove-type structure and the P-type strip region 4 and between the groove gate structure and the P-type strip region 4, the transverse width of each P-type shielding layer 5 is larger than that of each P-type strip region 4, and spaces are reserved between the different P-type shielding layers 5 in the transverse direction; a space is reserved between the Schottky groove type structure and the source electrode structure; the metal 11 is shorted to a third conductive material 12.
Furthermore, the P-type shielding layer 5 is in short circuit with the source electrode.
Further, a buffer layer 16 is interposed between the drift region and the substrate layer.
Furthermore, a high-concentration N-type doped region 17 is adopted above and in the gap of the P-type shielding layer 5.
Further, the N + polysilicon 7 of the trench gate structure is laterally divided into two parts by the first insulating dielectric layer 6.
Further, the semiconductor material of the structure is SiC, GaN and Ga 2 O 3 Semiconductor material with equal-width forbidden band.
The invention has the beneficial effects that: compared with the traditional SiC MOSFET with the surface integrated SBD, the invention forms Schottky contact on the side wall of the groove, can increase the Schottky contact area, enhance the follow current capability and inhibit the turn-on capability of the body diode while saving the chip area; the depletion layer between the P-type buried layers can simultaneously pinch off a reverse leakage current circulation path of the Schottky diode, reduce leakage current and power consumption, improve blocking voltage of the device, simultaneously mutually deplete the P-type buried layers and the N-type drift region in a blocking state, introduce an additional PN junction to improve the distribution of an internal electric field, and further realize improvement of withstand voltage; the drift region adopts a super junction structure, so that electric field distribution is optimized, blocking capability of the device is further improved, and higher drift region doping concentration can be adopted, so that on-resistance is obviously reduced. Compared with the traditional integrated SBD technology, the invention can save the chip area, enhance the follow current capability and inhibit the turn-on capability of the body diode, and simultaneously can reduce the on-resistance and improve the blocking voltage.
Drawings
FIG. 1 is a schematic diagram of a conventional SBD-integrated SiC MOSFET structure;
FIG. 2 is a schematic structural view of embodiment 1;
FIG. 3 is a schematic structural view of embodiment 3;
FIG. 4 is a schematic structural view of example 4;
FIG. 5 is a schematic structural view of example 5;
fig. 6 and 7 are graphs comparing the blocking voltage and the on-current of the SiC MOSFET of example 4 and the conventional integrated SBD under the same conditions of simulation, respectively.
Detailed Description
The technical scheme of the invention is described in detail in the following with reference to the accompanying drawings and embodiments:
example 1
As shown in fig. 2, the low-loss super-junction MOSFET integrated with the SBD comprises an N + substrate layer 2, a drift region located above the N + substrate layer 2, and a trench gate structure, a source structure and a schottky trench structure located above the drift region; the substrate layer 2 is connected with the first conductive material 1, and the first conductive material 1 is led out to be a drain electrode; the drift region comprises N-type strip regions 3 and P-type strip regions 4 which are transversely arranged at equal intervals in an alternating mode; the groove gate structure is positioned above the P-shaped strip region 4 in the middle of the cellular and comprises a first insulating medium layer 6 at the bottom and on the side wall of the groove and N + polycrystalline silicon 7 in the groove, the N + polycrystalline silicon 7 is connected with a second conductive material 13, and the second conductive material 13 is led out to form a gate; the source electrode structure is positioned at the top of the N-type drift region and on two sides of the trench gate structure, and comprises a P-type base region 8, a P + source contact region 9 and an N + source region 10 which are transversely arranged at the top of the P-type base region 8 in parallel, wherein the P-type base region 8 and the N + source region 10 are transversely contacted with the first insulating medium layer 6 and are connected with a third conductive material 12, and the third conductive material 12 is led out to form a source electrode; the Schottky groove type structure is positioned above the P-type strip region 4 on the outer side of the source electrode structure and comprises metal 11 on the side wall of the groove and a second insulating medium layer 14 in the groove, and the metal 11 and the N-type strip region 3 form Schottky contact;
the Schottky junction surface of the Schottky groove type structure is positioned in the longitudinal direction in the body, P type shielding layers 5 are respectively inserted between the Schottky groove type structure and the P type strip region 4 and between the groove gate structure and the P type strip region 4, the transverse width of each P type shielding layer 5 is larger than that of each P type strip region 4, and different P type shielding layers 5 are transversely spaced; a certain distance is reserved between the Schottky groove type structure and the source electrode structure; the metal 11 is shorted to a third conductive material 12.
The working principle of the embodiment is as follows:
compared with the traditional SiC MOSFET integrating the SBD, the method adopts a side-integrated Schottky contact mode, so that the layout area of the chip is effectively reduced; when the reverse conduction is carried out, the Schottky metal and the source electrode are in short circuit at high potential, and the opening of the body diode can be inhibited. In the embodiment, the super junction structure and the P-type buried layer extending out of the trench region are introduced into the drift region, and in a blocking state, due to the auxiliary depletion effect of the super junction structure and the pinch-off effect of depletion regions between the P-type buried layers, the blocking voltage of a device can be effectively improved, and the reverse leakage of the integrated Schottky diode is effectively restrained; in the reverse conducting state, the lateral longitudinal Schottky contact is formed, so that large follow current capacity can be realized, and the surface area of a chip is saved.
Example 2
The difference between this example and example 1 is that in this example the P-type shield layer 5 is shorted to the source. The P-type shield layer 5 shorted to the source can suppress deterioration of the SiC MOSFET dynamic characteristics.
Example 3
As shown in fig. 3, the present example is different from embodiment 1 in that a buffer layer 16 is inserted between the N + substrate layer 2 and the drift region, and the superjunction structure is adjusted to a semi-superjunction structure, so that the difficulty in implementing the process can be reduced while better static characteristics (such as high withstand voltage and low on-resistance) are ensured.
Example 4
As shown in fig. 4, compared with embodiment 1, the difference of this embodiment is that in this embodiment, an N-type region 17 with a higher doping concentration is introduced above the P-type shielding layer 5 and at the N-type drift region 3 at the gap thereof, which can effectively reduce the on-resistance and improve the current capability of the device.
Example 5
As shown in fig. 5, compared with embodiment 1, the difference of this embodiment is that in this embodiment, the N + polysilicon 7 is laterally divided into two parts separated by the first insulating medium layer 6, so that the overlapping area of the gate metal and the drain metal can be effectively reduced, thereby reducing the gate-drain capacitance of the device and further improving the dynamic characteristics of the device.
Example 6
The present example is different from example 1 in that the semiconductor material having the structure described in the present example may be SiC, GaN, Ga 2 O 3 Semiconductor material with equal-width forbidden band.
Fig. 6 and 7 are graphs showing the comparison of the blocking voltage and the forward conduction current of the SiC MOSFET of example 4 and the conventional integrated SBD under the same conditions in simulation, respectively. It can be seen that embodiment 4 has a significant blocking voltage advantage compared to the conventional structure, and embodiment 4 also has a relatively superior on-state performance due to the presence of the N-type region 17 with a high doping concentration.
Claims (6)
1. A super-junction MOSFET integrated with an SBD comprises an N + substrate layer (2), a drift region positioned above the N + substrate layer (2), and a trench gate structure, a source electrode structure and a Schottky trench type structure positioned above the drift region; a first conductive material (1) connected with the substrate layer (2) is arranged below the substrate layer, and the first conductive material (1) is led out to be a drain electrode; the drift region is composed of N-type strip regions (3) and P-type strip regions (4) which are transversely arranged at equal intervals in an alternating mode; the groove gate structure is positioned above the P-type strip region (4) and comprises a first insulating medium layer (6) positioned at the bottom and the side wall of the groove and N + polysilicon (7) in the groove, the side surface and the bottom of the N + polysilicon (7) are surrounded by the first insulating medium layer (6), the top of the N + polysilicon (7) is provided with a second conductive material (13) connected with the N + polysilicon (7), and the second conductive material (13) is led out to form a gate; the source electrode structure is positioned at the top of the drift region and on two sides of the trench gate structure and comprises a P-type base region (8), a P + source contact region (9) and an N + source region (10) which are transversely arranged in parallel at the top of the P-type base region (8), the P-type base region (8) and the N + source region (10) are transversely contacted with the first insulating medium layer (6), a third conductive material (12) is arranged at the tops of the P + source contact region (9) and the N + source region (10), and the third conductive material (12) is led out to form a source electrode; the Schottky groove type structure is positioned above the P-type strip region (4) on the outer side of the source electrode structure and comprises metal (11) positioned on the side wall of the groove and a second insulating medium layer (14) in the groove, and the metal (11) and the N-type strip region (3) form Schottky contact;
p-type shielding layers (5) are arranged between the Schottky groove-type structure and the P-type strip region (4) and between the groove grid structure and the P-type strip region (4), the transverse width of each P-type shielding layer (5) is larger than that of each P-type strip region (4), and spaces are reserved between the different P-type shielding layers (5) in the transverse direction; a space is reserved between the Schottky groove type structure and the source electrode structure; the metal (11) is shorted to the third conductive material (12).
2. An SBD integrated super junction MOSFET according to claim 1, wherein said P-type shielding layer (5) is shorted to the source.
3. An SBD integrated super junction MOSFET according to claim 1 or 2, wherein a buffer layer (16) is arranged between said drift region and the N + substrate layer (2).
4. An SBD integrated super junction MOSFET according to claim 3, wherein said P-type shielding layer (5) has a high concentration of N-type doped region (17) above said P-type shielding layer and in the gap between adjacent P-type shielding layers (5).
5. An SBD integrated super junction MOSFET according to claim 4, wherein said trench gate structure N + polysilicon (7) is divided into two parts in lateral direction by a first insulating dielectric layer (6).
6. The SBD integrated super-junction MOSFET of claim 5, wherein the semiconductor material used for the super-junction MOSFET is SiC, GaN, Ga 2 O 3 One kind of wide bandgap semiconductor material.
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| CN114447101B (en) * | 2022-01-24 | 2023-04-25 | 电子科技大学 | Vertical GaN MOSFET integrated with freewheeling channel diode |
| CN116435335B (en) * | 2023-03-22 | 2024-03-22 | 瑶芯微电子科技(上海)有限公司 | Groove type MOSFET electric field shielding protection structure and preparation method |
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| US20050199918A1 (en) * | 2004-03-15 | 2005-09-15 | Daniel Calafut | Optimized trench power MOSFET with integrated schottky diode |
| NZ552391A (en) * | 2004-07-08 | 2010-04-30 | Semisouth Lab Inc | Monolithic vertical junction field effect transistor and schottky barrier diode fabricated from silicon carbide and method for fabricating the same |
| JP2006269720A (en) * | 2005-03-24 | 2006-10-05 | Toshiba Corp | Semiconductor device and its fabrication process |
| JP2008066708A (en) * | 2006-08-09 | 2008-03-21 | Toshiba Corp | Semiconductor device |
| JP2008182054A (en) * | 2007-01-25 | 2008-08-07 | Toshiba Corp | Semiconductor device |
| JP5617175B2 (en) * | 2008-04-17 | 2014-11-05 | 富士電機株式会社 | Wide band gap semiconductor device and manufacturing method thereof |
| JP4670915B2 (en) * | 2008-08-08 | 2011-04-13 | ソニー株式会社 | Semiconductor device |
| JP2011233701A (en) * | 2010-04-27 | 2011-11-17 | Toshiba Corp | Power semiconductor device |
| JP2013201268A (en) * | 2012-03-23 | 2013-10-03 | Toshiba Corp | Semiconductor device |
| JP5852555B2 (en) * | 2012-12-26 | 2016-02-03 | 株式会社豊田中央研究所 | Semiconductor device |
| EP2942804B1 (en) * | 2014-05-08 | 2017-07-12 | Flosfia Inc. | Crystalline multilayer structure and semiconductor device |
| WO2018055318A1 (en) * | 2016-09-23 | 2018-03-29 | Dynex Semiconductor Limited | A Power MOSFET with an Integrated Schottky Diode |
| JP6930197B2 (en) * | 2017-04-20 | 2021-09-01 | 富士電機株式会社 | Semiconductor devices and manufacturing methods for semiconductor devices |
| JP6984347B2 (en) * | 2017-11-24 | 2021-12-17 | 富士電機株式会社 | Semiconductor device |
| CN108962977B (en) * | 2018-07-12 | 2021-08-20 | 中国科学院半导体研究所 | SBD (silicon carbide) -integrated silicon carbide trench MOSFETs (metal-oxide-semiconductor field effect transistors) and preparation method thereof |
| CN109065540A (en) * | 2018-08-06 | 2018-12-21 | 中国科学院半导体研究所 | A kind of structure and preparation method of the SiC UMOSFET of integrated SBD |
| JP7127445B2 (en) * | 2018-09-11 | 2022-08-30 | 富士電機株式会社 | semiconductor equipment |
| CN109244137A (en) * | 2018-09-19 | 2019-01-18 | 电子科技大学 | A kind of high reliability SiC MOSFET element |
| CN111403474A (en) * | 2020-03-23 | 2020-07-10 | 电子科技大学 | Double-channel silicon carbide MOSFET device integrated with Schottky diode |
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