CN111969041B - Super-junction VDMOS - Google Patents
Super-junction VDMOS Download PDFInfo
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- CN111969041B CN111969041B CN202010870477.0A CN202010870477A CN111969041B CN 111969041 B CN111969041 B CN 111969041B CN 202010870477 A CN202010870477 A CN 202010870477A CN 111969041 B CN111969041 B CN 111969041B
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- 239000004065 semiconductor Substances 0.000 claims abstract description 106
- 210000000746 body region Anatomy 0.000 claims description 15
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 10
- 229920005591 polysilicon Polymers 0.000 claims description 10
- 239000012535 impurity Substances 0.000 claims description 7
- 239000000758 substrate Substances 0.000 claims description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 3
- 229910052710 silicon Inorganic materials 0.000 claims description 3
- 239000010703 silicon Substances 0.000 claims description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 2
- 229910000464 lead oxide Inorganic materials 0.000 claims description 2
- YEXPOXQUZXUXJW-UHFFFAOYSA-N oxolead Chemical compound [Pb]=O YEXPOXQUZXUXJW-UHFFFAOYSA-N 0.000 claims description 2
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 2
- 238000004088 simulation Methods 0.000 description 6
- 230000015556 catabolic process Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- GPXJNWSHGFTCBW-UHFFFAOYSA-N Indium phosphide Chemical compound [In]#P GPXJNWSHGFTCBW-UHFFFAOYSA-N 0.000 description 1
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 230000010355 oscillation Effects 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
- 230000007480 spreading Effects 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/063—Reduced surface field [RESURF] pn-junction structures
- H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7811—Vertical DMOS transistors, i.e. VDMOS transistors with an edge termination structure
Abstract
The invention belongs to the technical field of power semiconductors, and relates to a super junction VDMOS. According to the super-junction VDMOS for improving EMI provided by the invention, the second conductive type semiconductor voltage-resisting columns with different lengths are introduced into the drift region, so that the longitudinal broadening of a depletion layer between the gate and the drain of a super-junction device is relieved, and the Cgd capacitance value is raised when Vds is smaller, so that the Cgd-Vds curve is flatter. And the voltage and current overshoot is effectively relieved. Therefore, the invention can relieve the electromagnetic interference problem of the device on the basis of ensuring the original basic electrical performance of the super-junction VDMOS.
Description
Technical Field
The invention belongs to the technical field of power semiconductors, and relates to a super junction VDMOS.
Background
The power super-junction VDMOS structure utilizes the P columns and the N columns which are mutually alternated to replace an N drift region of a traditional power device, so that the on-resistance is effectively reduced, and lower on-power consumption is obtained. Due to the characteristics of unique high input impedance, low driving power, high switching speed, excellent frequency characteristic, good thermal stability and the like, the high-frequency-stability high-frequency-power-stability switching power supply is widely applied to various fields such as switching power supplies, automobile electronics and motor driving. A conventional superjunction VDMOS structure is shown in fig. 1.
The typical application environment of the power VDMOS device is a switching power supply, in order to meet the miniaturization requirement of the switching power supply, the switching frequency and the power density of the power VDMOS device are continuously improved, and the modularization and the function integration can improve the power density of electronic components, but can also generate an increasingly complex internal electromagnetic environment. Under the condition of fast switching conversion, the voltage and the current of the power device change rapidly in a short time to generate high dv/dt and di/dt, which become a strong electromagnetic interference source. The electromagnetic interference generated by the power VDMOS has a strong amplitude and occupies a wide frequency band, and the interference can cause serious electromagnetic pollution to surrounding components or equipment through a coupling mode of conduction and radiation. Therefore, the problem of EMI generated by the VDMOS device itself is not negligible.
Disclosure of Invention
Aiming at the problems, the invention provides an EMI-resistant super-junction VDMOS, which reduces the switches dv/dt and di/dt of the super-junction VDMOS and improves the EMI noise of the device on the premise of not influencing the static electrical parameters of the device.
The technical scheme of the invention is as follows: a super junction VDMOS, as shown in fig. 2, comprises a metalized drain 1, a heavily doped first conductivity type semiconductor substrate 2 located above the metalized drain 1, a lightly doped first conductivity type semiconductor region 3 located above the first conductivity type semiconductor substrate 2; the two sides of the top of the lightly doped first conductive type semiconductor region 3 are provided with second conductive type semiconductor body regions 5; a first-conductivity-type lightly-doped JFET (junction field effect transistor) region 8 is arranged between the second-conductivity-type semiconductor body regions 5; the second conductive type semiconductor body region 5 is provided with a second conductive type semiconductor heavily-doped contact region 6 and a first conductive type semiconductor source region 7, and the second conductive type semiconductor body region 5 between the first conductive type semiconductor source region 7 and the first conductive type lightly-doped JFET region 8 is a channel region; the heavily doped polysilicon electrode 10 covers the channel region and the first conductivity type JFET region 8; the heavily doped polysilicon electrode 10 is separated from the channel region and the JFET region 8 by a gate oxide layer 9; the upper surface of the second conductive type semiconductor heavily doped contact region 6 and part of the upper surface of the first conductive type semiconductor source region 7 are in direct contact with the metalized source electrode 11; the metalized source 11 and the polysilicon electrode 10 are electrically isolated by an insulating medium layer. The bottom of the second-conductivity-type semiconductor body region 5 is further provided with a second-conductivity-type semiconductor region, the second-conductivity-type semiconductor region is composed of 3 or more than 3 second-conductivity-type semiconductor pillars 41, 42. The shorter the length of the second-conductivity-type semiconductor pillar is closer to the middle position of the second-conductivity-type semiconductor region 4.
Further, the total amount of impurities of the second-conductivity-type semiconductor pillars 41, 42.
Further, the gate oxide layer 9 is made of one of silicon oxide, silicon oxynitride, and lead oxide.
The invention has the beneficial effects that: according to the super-junction VDMOS for improving EMI provided by the invention, the drift region is introduced with the second conductive type semiconductor voltage-resistant columns with different lengths, so that the longitudinal broadening of a depletion layer between the gate and the drain of a super-junction device is relieved, and the Cgd capacitance value is raised when Vds is smaller, so that the Cgd-Vds curve is flatter. And the voltage and current overshoot is effectively relieved. Therefore, the invention effectively relieves the electromagnetic interference problem of the device on the basis of ensuring the original basic electrical performance of the super-junction VDMOS.
Drawings
Fig. 1 is a front view of the structure of a conventional super junction VDMOS;
fig. 2 is a front view of a super junction VDMOS structure of the present invention;
fig. 3 is a front view of the super junction VDMOS structure of embodiment 1;
fig. 4 is a front view of the super junction VDMOS structure of embodiment 2;
fig. 5 is a schematic diagram of Cgd of a conventional superjunction device at low drain voltage;
fig. 6 is a comparison of depletion layer simulations of a conventional superjunction VDMOS structure (a) and a superjunction VDMOS structure (b) of the present invention when Vds is 7V;
fig. 7 is a comparison of depletion layer simulations of a conventional superjunction VDMOS structure (a) and a superjunction VDMOS structure (b) of the present invention when Vds is 20V;
fig. 8 is a simulation comparison of Cgd-Vds curves for a conventional super-junction VDMOS structure (a) and a super-junction VDMOS structure (b) of the present invention;
fig. 9 is a comparison of drain turn-off voltage simulations for a conventional superjunction VDMOS structure (a) and a superjunction VDMOS structure (b) of the present invention.
Description of reference numerals: the structure of the transistor comprises a metalized drain electrode 1, a first conductive type semiconductor substrate 2, a first conductive type semiconductor lightly doped epitaxial layer 3, a second conductive type semiconductor column 41 and 42, a second conductive type semiconductor body region 5, a second conductive type semiconductor heavily doped contact region 6, a first conductive type semiconductor source region 7, a first conductive type semiconductor JFET region 8, a gate oxide layer 9, a polysilicon electrode 10 and a metalized source electrode 11.
Detailed Description
The technical scheme of the invention is described in detail in the following with reference to the accompanying drawings and embodiments:
example 1
As shown in fig. 3, this example includes a metalized drain 1, a heavily doped first conductivity type semiconductor substrate 2 located above the metalized drain 1, a lightly doped first conductivity type semiconductor region 3 located above the first conductivity type semiconductor substrate 2; the two sides of the top of the lightly doped first conductive type semiconductor region 3 are provided with second conductive type semiconductor body regions 5; a first-conductivity-type lightly-doped JFET (junction field effect transistor) region 8 is arranged between the second-conductivity-type semiconductor body regions 5; the second conductive type semiconductor body region 5 is provided with a second conductive type semiconductor heavily-doped contact region 6 and a first conductive type semiconductor source region 7, and the second conductive type semiconductor body region 5 between the first conductive type semiconductor source region 7 and the first conductive type lightly-doped JFET region 8 is a channel region; the heavily doped polysilicon electrode 10 covers the channel region and the first conductivity type JFET region 8; the heavily doped polysilicon electrode 10 is separated from the channel region and the JFET region 8 by a gate oxide layer 9; the upper surface of the second conductive type semiconductor heavily doped contact region 6 and part of the upper surface of the first conductive type semiconductor source region 7 are in direct contact with the metalized source electrode 11; the metalized source 11 and the polysilicon electrode 10 are electrically isolated by an insulating medium layer. The bottom of the second-conductivity-type semiconductor body 5 also has a second-conductivity-type semiconductor region 4, said second-conductivity-type semiconductor region 4 being composed of 3 second-conductivity- type semiconductor pillars 41, 42, 43, the tops of said second-conductivity- type semiconductor pillars 41, 42, 43 being in contact with the second-conductivity-type semiconductor body 5, the sides of adjacent second-conductivity- type semiconductor pillars 41, 42, 43 being in contact with each other. The second-conductivity-type semiconductor pillars 42 located at the middle position are shorter in length than the second-conductivity- type semiconductor pillars 41, 43 located at both sides. The total amount of impurities of the second conductivity- type semiconductor columns 41, 42, 43 and the total amount of impurities of the lightly doped first conductivity-type semiconductor region 3 satisfy the charge balance.
The working principle of the embodiment is as follows:
compared with a traditional power MOSFET, the super junction MOSFET device not only has smaller cell area and smaller capacitance, but also has the lateral depletion of adjacent voltage-resisting columns to cause the abrupt reduction of the Miller capacitance Cgd, the schematic diagram of the Miller capacitance Cgd at low drain voltage is shown in FIG. 5, and the width of a depletion layer between a grid electrode and a drain electrode determines the size of the depletion layer capacitance. As can be seen from the depletion layer simulation result, in the conventional super junction VDMOS structure, since the PN junctions formed by the lightly doped second-conductivity-type breakdown pillars and the adjacent first-conductivity-type breakdown pillars are laterally depleted from each other, when Vds is equal to 7V (fig. 6(a)) and 20V (fig. 7(a)), the lateral depletion layers rapidly merge to cause longitudinal spreading of the depletion layer, and thus the value of Cgd rapidly decreases, as shown by the Cgd-Vds curves in fig. 8 (a). According to the structure provided by the invention, the second conductive type semiconductor voltage-resistant columns with different lengths and different doping concentrations are introduced into the drift region, so that the charge balance of the second conductive type semiconductor voltage-resistant columns is maintained, and the voltage-resistant characteristic is not reduced. The length of the withstand voltage column is shorter as the relative positions of the partitioned semiconductor columns 41, 42, and 43 are closer to the inside. The vertical spread of the depletion layer between the gate and the drain of the super junction device is relieved, and when Vds is 7V (fig. 6(b)) and 20V (fig. 7(b)), the depletion layer width between the gate and the drain is shorter than that of the conventional super junction VDMOS, the Cgd capacitance value is larger, and the Cgd-Vds curve (shown in fig. 8 (b)) is flatter. The drain voltage simulation image when the device is turned off is shown in fig. 9, the selected VDD is 400V, and the super-junction VDMOS provided by the patent can effectively reduce the voltage oscillation of the device on the basis of ensuring the original electrical performance after the charge balance of the voltage-resistant column is adjusted, so that the problem of electromagnetic interference is solved.
In the implementation process, certain flexible design can be performed under the condition that the basic structure is not changed according to specific conditions. When the device is manufactured, the silicon can be replaced by semiconductor materials such as silicon carbide, gallium arsenide, indium phosphide or silicon germanium and the like.
Example 2
As shown in fig. 4, on the basis of embodiment 1, a first-conductivity-type semiconductor region 12 is added below a second-conductivity-type semiconductor pillar 42. The upper surface of the first-conductivity-type semiconductor region 12 is in direct contact with the second-conductivity-type semiconductor pillars 42, and the lower surface is flush with the second-conductivity- type semiconductor pillars 41, 43. The first-conductivity-type semiconductor region 12 is doped higher in concentration than the lightly-doped first-conductivity-type semiconductor region 3. It is also characterized in that the total amount of impurities of the second conductivity- type semiconductor pillars 41, 42, 43 and the total amount of impurities of the lightly doped first conductivity-type semiconductor region 3 and the first conductivity-type semiconductor region 12 satisfy charge balance.
Example 3
In this example, on the basis of embodiment 1, the doping concentration of second conductivity type semiconductor pillar 42 located at the middle position is lower than the doping concentrations of second conductivity type semiconductor pillars 41 and 43 located at both sides.
Claims (4)
1. A super junction VDMOS comprises a metalized drain (1), a heavily doped first conductivity type semiconductor substrate (2) located above the metalized drain (1), a lightly doped first conductivity type semiconductor region (3) located above the heavily doped first conductivity type semiconductor substrate (2); the two sides of the top of the lightly doped first conductive type semiconductor region (3) are provided with second conductive type semiconductor body regions (5); a first-conductivity-type lightly-doped JFET (8) region is arranged between the second-conductivity-type semiconductor bodies (5); the second conductive type semiconductor body region (5) is provided with a second conductive type semiconductor heavily-doped contact region (6) and a first conductive type semiconductor source region (7) which are arranged in parallel, and the second conductive type semiconductor body region (5) between the first conductive type semiconductor source region (7) and the first conductive type lightly-doped JFET region (8) is a channel region; a heavily doped polysilicon electrode (10) covers the channel region, the first conductivity type JFET region (8) and part of the upper surface of the first conductivity type semiconductor source region (7); the heavily doped polysilicon electrode (10) is isolated from the first conductivity type semiconductor source region (7), the channel region and the JFET region (8) by a gate oxide layer (9); the upper surface of the second conductive type semiconductor heavily-doped contact region (6) and part of the upper surface of the first conductive type semiconductor source region (7) are in direct contact with the metalized source electrode (11); the metalized source electrode (11) is electrically isolated from the polysilicon electrode (10) by an insulating medium layer; the semiconductor device is characterized in that the bottom of the second conductivity type semiconductor body region (5) is also provided with at least 3 second conductivity type semiconductor columns, the tops of the second conductivity type semiconductor columns are in contact with the second conductivity type semiconductor body region (5), the side faces of adjacent second conductivity type semiconductor columns are in contact, the region formed by connecting the adjacent second conductivity type semiconductor columns is defined as the second conductivity type semiconductor column region, and the length of the second conductivity type semiconductor columns is gradually shortened from two sides to the middle of the second conductivity type semiconductor column region.
2. A superjunction VDMOS according to claim 1, characterized in that the total amount of impurities of all the second conductivity type semiconductor pillars and the total amount of impurities of the lightly doped first conductivity type semiconductor region (3) satisfy charge balance.
3. The super-junction VDMOS of claim 1 or 2, wherein the gate oxide layer (9) is made of one of silicon oxide, silicon oxynitride, and lead oxide.
4. The super-junction VDMOS of claim 3, wherein the first conductivity type semiconductor is an n-type semiconductor and the second conductivity type semiconductor is a p-type semiconductor; or the first conductivity type semiconductor is a p-type semiconductor and the second conductivity type semiconductor is an n-type semiconductor.
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| CN202010870477.0A CN111969041B (en) | 2020-08-26 | 2020-08-26 | Super-junction VDMOS |
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| CN202010870477.0A CN111969041B (en) | 2020-08-26 | 2020-08-26 | Super-junction VDMOS |
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| CN111969041B true CN111969041B (en) | 2022-03-29 |
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| KR101795828B1 (en) * | 2013-09-17 | 2017-11-10 | 매그나칩 반도체 유한회사 | Super-junction semiconductor device and manufacturing method thereof |
| JP6301861B2 (en) * | 2014-07-31 | 2018-03-28 | 株式会社東芝 | Semiconductor device |
| CN105870189B (en) * | 2016-04-21 | 2019-07-19 | 西安电子科技大学 | A kind of lateral super-junction bilateral diffusion metal oxide semiconductor field-effect tube with bulk electric field mudulation effect |
| CN110447108B (en) * | 2017-05-26 | 2022-12-30 | 新电元工业株式会社 | MOSFET and power conversion circuit |
| CN107482051B (en) * | 2017-08-22 | 2020-03-17 | 电子科技大学 | Super-junction VDMOS device with variable forbidden bandwidth |
| JP7081876B2 (en) * | 2017-12-19 | 2022-06-07 | ラピスセミコンダクタ株式会社 | Semiconductor devices and methods for manufacturing semiconductor devices |
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