CN114899219A - Super junction P column and N-channel 4H-SiC-based VDMOS device with shielding effect - Google Patents

Super junction P column and N-channel 4H-SiC-based VDMOS device with shielding effect Download PDF

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CN114899219A
CN114899219A CN202210506265.3A CN202210506265A CN114899219A CN 114899219 A CN114899219 A CN 114899219A CN 202210506265 A CN202210506265 A CN 202210506265A CN 114899219 A CN114899219 A CN 114899219A
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polycrystalline silicon
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陈伟中
周铸
许峰
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Chongqing University of Post and Telecommunications
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/063—Reduced surface field [RESURF] pn-junction structures
    • H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
    • Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

Abstract

The invention relates to a super junction P column and N-channel 4H-SiC-based VDMOS device with a shielding effect, and belongs to the technical field of semiconductors. The device comprises a P + polycrystalline silicon drain electrode, an N + substrate area, a P column shielding area, an N column area, a P-electric field termination area, a silicon dioxide isolating layer, a P + polycrystalline silicon gate electrode, a P + polycrystalline silicon source electrode I, a P + polycrystalline silicon source electrode II, an N-channel area and an N + source area; the P + polycrystalline silicon drain electrode, the N + substrate area, the N column area, the P + polycrystalline silicon source electrode II, the N-channel area and the N + source area form a conductive area of the device; the N column region and the P-electric field termination region form a drift region of the device; the P-column shielding region and the N-column region form a transverse super junction of the device. On the basis of the traditional 4H-SiC-based VDMOS device, the super junction structure, the integral asymmetric structure and the N-channel region are introduced into the vertical drift region, so that the breakdown voltage of the device is improved, the Miller capacitance and the feedback capacitance are greatly reduced, the dynamic performance of the device is improved, and the channel resistance and the specific on-resistance are reduced.

Description

Super junction P column and N-channel 4H-SiC-based VDMOS device with shielding effect
Technical Field
The invention belongs to the technical field of semiconductors, and relates to a super junction P column and N-channel 4H-SiC-based VDMOS device with a shielding effect.
Background
The electric energy is one of main energy sources used by human society, and has the characteristics of cleanness, high efficiency, easy transportation and the like. In the transmission and use of electric energy, power electronics technology plays an important role, and a power semiconductor is the core of the power electronics technology. The power semiconductor mainly plays a role of rectification and switching in a circuit, and the MOSFET is a commonly used power device due to its high input impedance. With the development of technology, the requirements on the breakdown voltage and the on-resistance of the device are higher and higher. Conventional silicon materials are difficult to continue to develop on power MOSFETs, at which point silicon carbide has shown great potential in the power semiconductor market. Some basic physical properties of Si and 4H-SiC materials are listed in table 1:
TABLE 1 basic physical Properties of Si and 4H-SiC materials
Figure BDA0003636294690000011
The silicon carbide, as a representative of wide bandgap semiconductors, has the characteristics of high critical breakdown electric field, high bandgap width, high thermal conductivity and high electron saturation drift velocity, and is suitable for application in the fields of high voltage, medium frequency and high frequency. Silicon carbide has various structures, and common 4H-SiC is studied and used in the present invention. When the SiC MOFET is applied in a circuit, the switching loss is much larger than the conduction loss, so improving the switching performance is a great research hotspot of the SiC MOFET.
One is as follows: for a vertical device, increasing the vertical height of the device can increase the breakdown voltage of the device, but at the same time, the problems of increasing the on-resistance, increasing the process difficulty and aggravating the self-heating problem of the device, and being difficult to dissipate heat, thereby affecting the reliability of the device, etc. therefore, how to improve the relationship between the breakdown voltage and the on-resistance of the device without increasing the vertical height becomes the main problem of the vertical power device.
The second step is as follows: as a third generation semiconductor device at present, the SiC MOFET device is applied in a high-frequency circuit in most application scenes, so that the switching performance of the device is not negligible, and the gate leakage charge Q of the device is mainly considered when the switching performance of the MOS device is measured GD The parasitic capacitance of MOSFET can be divided into three parts, i.e. gate-to-drain parasitic capacitance C GD Parasitic capacitance C between grid and source GS Parasitic capacitance C between source and drain DS . For practical applications, the input capacitance, the output capacitance and the feedback capacitance are classified into three categories. When the input capacitor is charged with threshold voltage, the device can be turned on, and when the input capacitor is discharged to a certain value, the device can be turned off, so that the input capacitor mainly influences the switching speed and the switching loss of the device. The output capacitance mainly affects the variation of the drain-source voltage of the device and limits dv/dt in the switching process. The losses due to the output capacitance are generally negligible. Feedback capacitance C GD Also commonly called miller capacitance and feedback transmission capacitance, mainly affect the coupling relationship between the gate voltage and the drain-source voltage of the device. The invention mainly researches the influence of the Miller capacitance on the switching speed of the device.
Disclosure of Invention
In view of the above, the present invention provides a super junction P-pillar and N-channel 4H-SiC based VDMOS device with a shielding effect, which reduces miller charge and feedback capacitance of the device, reduces a peak electric field of the device, optimizes a breakdown electric field of the device, increases a breakdown voltage of the device, and simultaneously introduces an N-channel region to reduce a channel resistance and a specific on-resistance of the device.
In order to achieve the purpose, the invention provides the following technical scheme:
A4H-SiC-based VDMOS device with a super-junction P column and an N-channel with shielding effect comprises a P + polysilicon drain electrode 1, an N + substrate region 2, a P column shielding region 3, an N column region 4, a P-electric field termination region 5, a silicon dioxide isolation layer 6, a P + polysilicon gate electrode 7, a P + polysilicon source electrode I8, a P + polysilicon source electrode II 9, an N-channel region 10 and an N + source region 11;
the P + polycrystalline silicon source electrode I8 is positioned above the P column shielding region 3 and is connected with a zero potential point of the P column shielding region 3, and the part does not participate in the conduction of the device and is only used for ensuring that the area of the device is at zero potential;
the P + polycrystalline silicon source electrode II 9 is positioned above the P-electric field termination region 5 and the N + source region 11, is connected with the P-electric field termination region 5 and the N + source region 1, and is a main conducting part of the device;
the P + polycrystalline silicon gate electrode 7 is positioned between the P + polycrystalline silicon source electrode I8 and the P + polycrystalline silicon source electrode II 9 and extends into the silicon dioxide isolating layer 6;
the silicon dioxide isolating layer 6 is embedded into the upper end of the P column shielding region 3 and isolates the P + polysilicon gate electrode 7 from the P column shielding region 3, the N + source region 11 and the N-channel region 10;
the N-channel region 10 is positioned above the N column region 4 and at the left of the P-electric field termination region 5;
the N + source region 11 is positioned above the N-channel region 10 and at the left of the P-electric field termination region 5;
the N + substrate region 2 is positioned below the P column shielding region 3 and the N column region 4;
the P + polysilicon drain 1 is located below the N + substrate region 2.
Optionally, a 4H-SiC-based VDMOS device with a super junction P column and an N-channel based on another structure and shielding effect is provided: on the basis of the structure of the device in claim 1, the P + polycrystalline silicon source electrodes (9) are symmetrically arranged on two sides of the P + polycrystalline silicon gate electrode (7); the silicon dioxide isolation layer (6) and the P + polysilicon gate electrode (7) are displaced to the right in the center of the N column region (4); dividing the P column shielding region (3) into two parts and placing the two parts at two sides of the N column region (4); dividing the N + source region (11) into two parts and placing the two parts on two sides of the silicon dioxide isolation layer (6); an N-channel region (10) is added at the left of the silicon dioxide isolation layer (6); a P-field termination region (5) is added on the left side of the silicon dioxide isolation layer (6).
Optionally, the P + polysilicon drain 1, the N + substrate region 2, the N column region 4, the P + polysilicon source electrode ii 9, the N-channel region 10, and the N + source region 11 constitute a conductive region.
Optionally, the N column region 4 and the P-field stop region 5 constitute a drift region.
Optionally, the P-pillar shielding region 3 and the N-pillar region 4 form a lateral Super Junction (Super Junction). The P column shielding region 3 is used as a part of a transverse super junction, does not participate in the conduction of the device, is mainly used for assisting in depleting the N column region 4, provides charge compensation, optimizes a breakdown electric field, improves breakdown voltage, shields high electric fields from the bottom and the right side of the silicon dioxide isolation layer 6, and assists in heat dissipation of the device.
Optionally, the width of the P + polysilicon source electrode 8 is 0.4 μm, and the height thereof is 0.75 μm; the width of the P + polycrystalline silicon source electrode 9 is 0.9 μm, and the height thereof is 0.75 μm.
Optionally, the length of the part of the P + polysilicon gate electrode 7 extending into the silicon dioxide isolation layer 6 is 1.25 μm, and the length of the part not extending into the silicon dioxide isolation layer 6 is 0.75 μm; the width of the P + polysilicon gate electrode 7 is 0.4 μm;
the length of the silicon dioxide isolation layer 6 embedded into the P column shielding region 3 is 2 microns, the thickness of the side wall is 0.05 microns, and the thickness of the silicon dioxide isolation layer located at the lower portion of the P + polysilicon gate electrode 7 is 0.5 microns.
Optionally, the N-channel region 10 is 1 μm high and 0.2 μm wide; the N + source region 11 has a height of 0.25 μm and a width of 0.4 μm.
Optionally, the P-pillar shielding region 3 is 14 μm high; the height of the N column region 4 is 12.75 μm.
Optionally, the N + substrate region 2 is 3 μm high and 2 μm wide; the height of the P + polysilicon drain electrode 1 is 0.5 μm, and the width thereof is 2 μm.
Optionally, the doping concentration range of the P column shielding region (3), the N column region (4) and the P-electric field termination region (5) is 1 × 10 15 cm -3 ～5×10 16 cm -3 Adjusting according to the size of the device and the required working current;
alternatively, the N-type VDMOS device can be changed into a P-type VDMOS device;
the structure is also suitable for a transverse diode, a LIGBT and an LDMOS;
optionally, the thickness of the silicon dioxide isolation layer 6 is adjustable, and is generally required to be more than 0.01 μm, and too thick affects the gate-drain capacitance (i.e. miller capacitance) of the device, resulting in too large capacitance and reduced switching speed of the device; too thin may result in a device that is not resistant to high field strength, leading to premature breakdown of the device, and reducing breakdown voltage.
The invention has the beneficial effects that: on the basis of a traditional 4H-SiC-based VDMOS device, a super junction structure, an integral asymmetric structure and an N-channel region are introduced into a vertical drift region. When the device is turned off, the P column shielding regions and the N column regions on the two sides of the device form PN junctions, the P column shielding regions perform charge compensation on the N column regions of the conductive region of the device and assist in depletion, so that the conductive region of the N column region generates a wider space charge region on one side close to the P column region, and the breakdown voltage of the device is further improved. On one hand, in the device, a zero potential point is introduced above the P column shielding region under the traditional 4H-SiC-based VDMOS structure, and the P column shielding region and the source electrode are in short circuit, so that the N column region is more obviously depleted, the longitudinal breakdown electric field of the device is further optimized, and the breakdown voltage of the device is improved; on the other hand, the device adopts asymmetric structure, and P post shielded area wraps up gate oxide layer bottom and side, has shielded the high electric field that comes from gate oxide layer and has made the gate oxide layer electric field that is close to channel one side can not surpass silicon dioxide material safety work electric field yet through the optimization of structural parameter, has reduced miller electric charge and feedback capacitance by a wide margin, and the dynamic behavior of device obtains promoting. Meanwhile, when the device is conducted, the lightly doped N-type silicon carbide is used for the channel part, so that the channel type is changed into an accumulation type, the resistivity of the accumulation type channel is smaller compared with that of a common depletion type channel, the required driving voltage is also smaller, and the channel resistance and the specific on-resistance of the device are reduced.
Additional advantages, objects, and features of the invention will be set forth in part in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from practice of the invention. The objectives and other advantages of the invention may be realized and attained by the means of the instrumentalities and combinations particularly pointed out hereinafter.
Drawings
For purposes of promoting a better understanding of the objects, aspects and advantages of the invention, reference will now be made to the following detailed description taken in conjunction with the accompanying drawings in which:
fig. 1 is a schematic structural diagram of a VDMOS device of a new structure according to embodiment 1 of the present invention;
fig. 2 is a schematic structural diagram of a VDMOS device of a new structure according to embodiment 2 of the present invention;
FIG. 3 is a comparative graph of the distribution of the breakdown electric field in the vertical direction from the N-channel region of the VDMOS device of the new structure provided by the present invention to the N + substrate region through the interface of the P-pillar shielding region and the N-pillar region;
FIG. 4 shows the drift region with a doping concentration of 8.0 × 10 16 cm -3 OfThe doping concentration of the 4H-SiC-based VDMOS device and the N column region and the P column shielding region is 8.0 multiplied by 10 16 cm -3 The avalanche breakdown characteristic diagram of the VDMOS device with the new structure is shown;
FIG. 5 shows the drift region with a doping concentration of 8.0 × 10 16 cm -3 The doping concentration of the conventional 4H-SiC-based VDMOS device and the N column region and the P column shielding region is 8.0 multiplied by 10 16 cm -3 The potential distribution diagram of the VDMOS device with the new structure under avalanche breakdown;
FIG. 6 shows the present invention at V GS ＝15V、V DS When the voltage is 800V, the doping concentration of the N column region and the P column shielding region is 8.0 multiplied by 10 16 cm -3 The peak intensity comparison graph of the grid oxide layer of the VDMOS device with the new structure and the traditional 4H-SiC-based VDMOS device is shown;
FIG. 7 shows the doping concentrations of the N-pillar region and the P-pillar shielding region of the VDMOS device of embodiment 1 provided by the invention are from 5.0 × 10 16 cm -3 To 1.0X 10 17 cm -3 A graph of the relation between the feedback capacitance and the drain voltage of the traditional 4H-SiC-based VDMOS device during increasing;
FIG. 8 is a graph comparing the gate charge performance of a VDMOS device of example 1 provided by the present invention and a conventional 4H-SiC-based VDMOS device;
fig. 9 is a graph of the drain-source voltage and the drain-source current with time during the turn-on process and the turn-off process of the VDMOS device in accordance with the embodiment 1 provided by the present invention under the resistive load;
FIG. 10 shows the present invention at V GS When the voltage is 15V, the doping concentration of the N column region and the P column shielding region is 5.0 multiplied by 10 16 cm -3 To 1.0X 10 17 cm -3 A graph of drain current versus drain voltage for incremental increases;
FIG. 11 shows the present invention at V GS ＝15V、V DS The doping concentration of the drift region is 8.0 × 10 at 20V 16 cm -3 The doping concentration of the conventional 4H-SiC-based VDMOS device and the N column region and the P column shielding region is 8.0 multiplied by 10 16 cm -3 The output characteristic curve of the VDMOS device with the new structure is compared with a comparison graph of the specific on-resistance under the same level of breakdown voltage.
Fig. 12 is a schematic view of a main process flow of a VDMOS device according to embodiment 1 of the present invention;
reference numerals: 1. a P + polysilicon drain electrode; 2. an N + substrate region; 3. a P-pillar shield region; 4. an N column region; 5. a P-field termination region; 6. a silicon dioxide isolation layer; 7. a P + polysilicon gate electrode; 8. a P + polycrystalline silicon source electrode I; 9. a P + polycrystalline silicon source electrode II; 10. an N-channel region; 11. and an N + source region.
Detailed Description
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention. It should be noted that the drawings provided in the following embodiments are only for illustrating the basic idea of the present invention in a schematic way, and the features in the following embodiments and examples may be combined with each other without conflict.
Wherein the showings are for the purpose of illustrating the invention only and not for the purpose of limiting the same, and in which there is shown by way of illustration only and not in the drawings in which there is no intention to limit the invention thereto; for a better explanation of the embodiments of the present invention, some parts of the drawings may be omitted, enlarged or reduced, and do not represent the size of an actual product; it will be understood by those skilled in the art that certain well-known structures in the drawings and descriptions thereof may be omitted.
The same or similar reference numerals in the drawings of the embodiments of the present invention correspond to the same or similar components; in the description of the present invention, it should be understood that if there is an orientation or positional relationship indicated by terms such as "upper", "lower", "left", "right", "front", "rear", etc., based on the orientation or positional relationship shown in the drawings, it is only for convenience of description and simplification of description, but it is not an indication or suggestion that the referred device or element must have a specific orientation, be constructed in a specific orientation, and be operated, and therefore, the terms describing the positional relationship in the drawings are only used for illustrative purposes, and are not to be construed as limiting the present invention, and the specific meaning of the terms may be understood by those skilled in the art according to specific situations.
Example 1:
as shown in fig. 1, the 4H-SiC-based VDMOS device with super junction P-pillar and N-channel with shielding effect proposed by the present invention has the structural parameters and doping concentrations shown in table 2:
table 2 table of various structural parameters and doping concentration profiles of example 1
Figure BDA0003636294690000061
The device mainly comprises a P + polycrystalline silicon drain electrode 1, an N + substrate area 2, a P column shielding area 3, an N column area 4, a P-electric field termination area 5, a silicon dioxide isolating layer 6, a P + polycrystalline silicon gate electrode 7, a P + polycrystalline silicon source electrode I8, a P + polycrystalline silicon source electrode II 9, an N-channel area 10 and an N + source area 11.
The source electrode is designed and characterized in that the source electrode is separated, one part (P + polycrystalline silicon source electrode II 9) is positioned at the upper end of the P-electric field termination region 5 and is connected with the N + source region 10 and the P-electric field termination region 5, the width is 0.9 mu m, the height is 0.75 mu m, and the part is the main conductive part of the device; the other part (P + polycrystalline silicon source electrode I8) is positioned at a zero potential point (a source electrode short-circuit electrode positioned at the upper end of the P column shielding region) at the upper end of the P column shielding region, does not participate in conduction, and is only used for ensuring that the area of the device is at zero potential, 0.4 mu m in width and 0.75 mu m in height.
The P + polysilicon gate electrode 7 is positioned in the middle of the two source electrodes and extends into the groove, the width is 0.4 mu m, the height is 0.75 mu m, the length of the embedded silicon dioxide part is 1.25 mu m, the polysilicon gate electrode 7 is separated from the P column shielding region 3, the N + source region 11 and the N-channel region 10 by the silicon dioxide isolating layer 6, the thickness of the side wall of the silicon dioxide isolating layer 6 is 0.05 mu m, and the height of the bottom region of the polysilicon gate is 0.5 mu m.
The total height of the P column shielding region 3 is 14 mu m; the embedded length of the silicon dioxide isolation layer 6 is 2 mu m, and the total height of the N column region 4 is 12.75 mu m; the N-channel region 10 is 1 μm high and 0.2 μm wide; the N + source region 11 above the N-channel region 10 is 0.4 μm wide and 0.25 μm high; the N + substrate region 2 located below the P column shield region 3 and the N column region 4 has a height of 3 μm and a width of 2 μm.
The VDMOS conduction region mainly comprises a P + polysilicon drain electrode 1, an N + substrate region 2, an N column region 4, a P + polysilicon source electrode II 9, an N-channel region 9 and an N + source region 10.
The drift region of the device mainly comprises an N column region 4 and a P-electric field termination region 5, the left P column shielding region 3 is used as a part of a super junction and does not participate in electric conduction, the left P column shielding region is mainly used for assisting in depleting the N column region 4, providing charge compensation, optimizing a breakdown electric field, improving breakdown voltage, shielding high electric fields from the bottom and the right side of a silicon dioxide isolation layer 6, and assisting in heat dissipation of the device. The lateral super junction of the device is composed of a P-column shielding region 3 and an N-column region 4.
Example 2:
as shown in fig. 2, the 4H-SiC-based VDMOS device with super junction P-pillar and N-channel having shielding effect provided by the present invention mainly includes a P + polysilicon drain electrode 1, an N + substrate region 2, a P-pillar region 3, an N-pillar region 4, a P-electric field termination region 5, a silicon dioxide isolation layer 6, a P + polysilicon gate electrode 7, a P + polysilicon source electrode 8, an N-channel region 9, and an N + source region 10.
On the basis of the structure of embodiment 1, the gate oxide layer is moved to the right to locate the gate oxide layer at the center of the N column region, the P column regions are separately arranged at two sides to assist in depleting the N column region, and meanwhile, the doping concentration of 2.0 × 10 is added above the N column region 17 cm -3 The electric field termination region improves the breakdown resistance of the P column region; adding heavily doped N-type source region with doping concentration of 2.0 × 10 on the side near the gate oxide layer 19 cm -3 The device is mainly used for providing the capability of extracting electrons during conduction, and the on-resistance of the device is further reduced. However, although the static performance of the device of example 2 is improved, the device loses the electric field shielding effect of the P-pillar region on the gate silicon dioxide isolation layer under high drain voltage, and therefore, the reliability of the device of example 2 under high voltage is not as good as that of the device of example 1.
FIG. 3 is a comparative graph of the breakdown electric field distribution of the N-channel region of the VDMOS device with the new structure provided by the present invention and the conventional 4H-SiC-based VDMOS device along the vertical direction from the interface of the P-pillar region and the N-pillar region to the N + substrate region. As can be seen from the figure, the electric field distribution of the new structure of example 1 is more uniform than that of the conventional trench gate MOSFET device, which enables the new structure to accommodate a higher breakdown voltage. It is particularly noted that the electric field intensity in the case of embodiment 1 having a vertical length of 2.5 μm suddenly drops because the drift region is blocked by the silicon dioxide isolation layer and cannot contact the P-type column region, so that the drift region is not depleted.
FIG. 4 shows the drift region with a doping concentration of 8.0 × 10 16 cm -3 The doping concentration of the conventional 4H-SiC-based VDMOS device and the N column region and the P column shielding region is 8.0 multiplied by 10 16 cm -3 The avalanche breakdown characteristic diagram of the VDMOS device with the new structure. As can be seen from fig. 4, the breakdown voltage of the conventional 4H-SiC-based VDMOS device is 1666V on the same drift region scale, while the breakdown voltage of the embodiment 1 of the present invention is 2260V on the same drift region scale, which is increased by about 594V, so that the static avalanche breakdown characteristic of the embodiment 1 of the present invention is better than that of the conventional 4H-SiC-based VDMOS device, which facilitates the device to operate at a higher operating voltage.
FIG. 5 shows the drift region with a doping concentration of 8.0 × 10 16 cm -3 The doping concentration of the conventional 4H-SiC-based VDMOS device and the N column region and the P column shielding region is 8.0 multiplied by 10 16 cm -3 The potential distribution diagram of the VDMOS device with the new structure under avalanche breakdown. As can be seen from fig. 5, the potential distributions of the two are substantially the same, but the potential distribution of embodiment 1 of the present invention has a streamline shape inclined toward the upper end of the P column shielding region, because the P column shielding region of the present device does not participate in conduction, and at the same time, the isolation layer with a thicker lower end of the gate silicon dioxide isolates the high potential from the N column region, so that the potential distribution of the device is more reasonable, and the side indicates that the breakdown voltage of the device is higher.
FIG. 6 shows the present invention at V GS ＝15V、V DS When the doping concentration is 800V, the doping concentration of the N column region and the P column shielding region is 8.0 multiplied by 10 16 cm -3 The peak intensity of the grid oxide layer of the VDMOS device with the new structure is compared with that of the traditional 4H-SiC-based VDMOS device. In embodiment 1 of the present invention, the target operating voltage level is 1200V, and according to the design specification of a power electronic system, a device generally needs to operate under 800V bus voltage, so that embodiment 1 of the present invention simulates the operation of the device under 800V bus operating voltageIn this situation, it is known that the highest withstand field strength of silicon dioxide is 4MV/cm, and as can be seen from fig. 6, the peak electric field in embodiment 1 of the present invention is located at the junction between the gate polysilicon and the bottom of the oxide layer, and the peak electric field strength is 3.68MV/cm, which is less than 4MV/cm, and is within the safe qualified range. And the left P-pillar shield effectively shields the large electric field from the bottom and left side of the gate oxide.
FIG. 7 shows the doping concentrations of the N-pillar region and the P-pillar shielding region of the VDMOS device of embodiment 1 provided by the invention are from 5.0 × 10 16 cm -3 To 1.0X 10 17 cm -3 And (3) a graph of feedback capacitance and drain voltage of the incremental and traditional 4H-SiC-based VDMOS device. As can be seen from FIG. 7, the feedback capacitance of the capacitor of example 1 at 800V drain operating voltage is 0.369Nf/cm 2 Compared with 1.225Nf/cm of the conventional 4H-SiC-based VDMOS 2 Is smaller, which reflects that the VDMOS device of example 1 is superior in high-frequency response characteristics, and at the same time, the smaller feedback capacitance means that the time required for the device to turn on and off is smaller, which is equivalent to indirectly reducing the switching loss of the device, so that the switching characteristics of example 1 are superior to those of the conventional 4H-SiC-based VDMOS device. Meanwhile, the figure also reflects that the doping concentration of the N column region and the P column shielding region is 5.0 multiplied by 10 in the embodiment 1 of the invention 16 cm -3 To 1.0X 10 17 cm -3 As can be seen from fig. 7, the higher the concentration of the drift region of the device is, the lower the feedback capacitance at 800V drain operating voltage is, because the feedback capacitance is affected by the space charge region, and the value of the space charge region capacitance is affected by the external bias voltage, the space charge region in embodiment 1 of the present invention is smaller than the conventional 4H-SiC-based VDMOS, and therefore, the space charge region in embodiment 1 of the present invention is less affected by the space charge region capacitance; it can also be seen from fig. 7 that the feedback capacitance does not change much overall although the doping concentration of the drift region changes.
FIG. 8 is a graph comparing the gate charge performance of the VDMOS device of example 1 and the conventional 4H-SiC-based VDMOS device. As can be seen from fig. 8, when the devices are not turned on, the gate charges of the devices increase with the increase of the gate-source bias voltage, the C-V relationship is approximately linear, and the curves of the portions are basically overlapped. Device just turned onWhen the gate voltage is maintained to be slightly larger than the threshold voltage by the miller plateau voltage, the gate charge is increased, and the gate voltage is increased but has a very small amplitude. After the device is completely started, the total charge of the traditional 4H-SiC-based VDMOS is 1739.97nC/cm 2 While the total charge of the embodiment 1 was 1137.31nC/cm 2 In comparison, the total charge amount of embodiment 1 of the present invention is reduced by 34.6% compared to the conventional trench MOSFET; meanwhile, compared with the Miller capacitance, the Miller charge of the traditional 4H-SiC-based VDMOS is 267.11nC/cm 2 Miller charge 174.03nC/cm for example 1 2 In contrast, the Miller charge of inventive example 1 is reduced by 34.9% compared to the conventional 4H-SiC-based VDMOS. Therefore, the device of example 1 of the present invention is superior to the conventional trench MOSFET in gate charge characteristics.
Fig. 9 is a graph of the drain-source voltage and the drain-source current with time during the turn-on process and the turn-off process of the VDMOS device under the resistive load according to embodiment 1 of the present invention. In fig. 9, a is a schematic diagram of an on-off process when the parasitic inductance of the device in embodiment 1 of the present invention is 10nH, and it can be seen from a that the on-off loss of the device is substantially concentrated within 0.43 μ s as shown in the figure, and similarly, the off-off loss of the device is substantially concentrated within 0.41 μ s as shown in the figure, so that reducing this time length as much as possible is an important objective to reduce the on-off loss and the off-off loss of the device. Meanwhile, as can be seen from the graph b, the voltage change rules of the device are the same, the three curves almost coincide, and the current curves are different mainly in the magnitude of the current. The sizes of the resistive loads are 16 omega, 8 omega, 4 omega and 2 omega in sequence, the turn-off time of the device is 0.41 mu s, 0.21 mu s, 0.04 mu s and 0.05 mu s respectively, and the corresponding turn-on time is 0.43 mu s, 0.16 mu s, 0.03 mu s and 0.02 mu s respectively. In combination with the switching characteristics of the known conventional trench MOSFET device, the switching characteristics of embodiment 1 of the present invention are superior to those of the conventional trench MOSFET device.
FIG. 10 shows the present invention at V GS When the voltage is 15V, the doping concentration of the N column region and the P column shielding region is 5.0 multiplied by 10 16 cm -3 To 1.0X 10 17 cm -3 The drain current versus drain voltage is plotted as the number of increments increases. It can be seen from fig. 10 that when the super junction is used as the drift region, the lower the doping concentration of the P column and the N column is, the device is in the same stateThe smaller the drain current under the condition of equal drain voltage, the larger the breakdown voltage, but the lower the doping concentration of the drift region, the larger the on-resistance of the device, the tendency that the breakdown voltage increases first and then decreases is presented, because when the device is turned off, as the doping concentrations of the P-type column and the N-type column are continuously decreased, the P-type column is always in auxiliary depletion of the N-type column, when the doping concentration is reduced to a certain value, the situation that the device is directly broken down in the middle of the N-type column region occurs, and the breakdown voltage at this time has a tendency of abrupt decrease.
FIG. 11 shows the present invention at V GS ＝15V、V DS The doping concentration of the drift region is 8.0 × 10 at 20V 16 cm -3 The doping concentration of the conventional 4H-SiC-based VDMOS device and the N column region and the P column shielding region is 8.0 multiplied by 10 16 cm -3 The output characteristic curves of the two devices with the new structures are compared with a comparison graph of specific on-resistance under the same level of breakdown voltage. As can be seen from FIG. 11, the drain current I of embodiment 1 DS The sum specific on-resistance is much larger than that of the conventional 4H-SiC-based VDMOS, which shows that in case of forward conduction in embodiment 1, due to the addition of the N-channel region in the channel region, the channel resistance of the device is reduced during conduction, and thus the on-resistance is reduced, so that the static conduction performance is better than that of the conventional 4H-SiC-based VDMOS.
The invention provides a super junction P column and N-channel 4H-SiC-based VDMOS device with shielding effect, which takes embodiment 1 as an example, and the main process flow is shown in FIG. 12. The main process comprises the following steps: and forming a super junction trench gate region and a silicon dioxide isolation layer by processes of ion implantation, diffusion, etching, oxidation, deposition, polycrystalline filling, annealing and the like. And finally, depositing a polysilicon electrode to form a source electrode, a grid electrode and a drain electrode.
Finally, the above embodiments are only for illustrating the technical solutions of the present invention and not for limiting, although the present invention has been described in detail with reference to the preferred embodiments, it should be understood by those skilled in the art that modifications or equivalent substitutions may be made on the technical solutions of the present invention without departing from the spirit and scope of the technical solutions, and all that should be covered by the claims of the present invention.

Claims (10)

1. A super junction P column and N-channel 4H-SiC-based VDMOS device with shielding effect is characterized in that: the silicon-based field effect transistor comprises a P + polycrystalline silicon drain electrode (1), an N + substrate region (2), a P column shielding region (3), an N column region (4), a P-electric field termination region (5), a silicon dioxide isolation layer (6), a P + polycrystalline silicon gate electrode (7), a P + polycrystalline silicon source electrode I (8), a P + polycrystalline silicon source electrode II (9), an N-channel region (10) and an N + source region (11);
the P + polycrystalline silicon source electrode I (8) is positioned above the P column shielding region (3) and is connected with a zero potential point of the P column shielding region (3);
the P + polycrystalline silicon source electrode II (9) is positioned above the P-electric field termination region (5) and the N + source region (11) and is connected with the P-electric field termination region (5) and the N + source region (11);
the P + polycrystalline silicon gate electrode (7) is positioned between the P + polycrystalline silicon source electrode I (8) and the P + polycrystalline silicon source electrode II (9) and extends into the silicon dioxide isolating layer (6);
the silicon dioxide isolating layer (6) is buried in the upper end of the P column shielding region (3) and isolates the P + polysilicon gate electrode (7) from the P column shielding region (3), the N + source region (11) and the N-channel region (10);
the N-channel region (10) is positioned above the N column region (4) and at the left of the P-electric field termination region (5);
the N + source region (11) is positioned above the N-channel region (10) and to the left of the P-electric field termination region (5);
the N + substrate region (2) is positioned below the P column shielding region (3) and the N column region (4);
the P + polycrystalline silicon drain electrode (1) is positioned below the N + substrate region (2);
the P + polycrystalline silicon drain electrode (1), the N + substrate region (2), the N column region (4), the P + polycrystalline silicon source electrode II (9), the N-channel region (10) and the N + source region (11) form a conductive region of the device;
the N column region (4) and the N-channel region (10) form a drift region of the device;
and the P column shielding region (3) and the N column region (4) form a transverse super junction of the device.
2. The super junction P-pillar and N-channel 4H-SiC-based VDMOS device with shielding effect of claim 1, wherein: providing a 4H-SiC-based VDMOS device with a super junction P column and an N-channel based on another structure and having a shielding effect: on the basis of the structure of the device of claim 1, the P + polycrystalline silicon source electrodes (9) are symmetrically arranged on two sides of the P + polycrystalline silicon gate electrode (7); the silicon dioxide isolation layer (6) and the P + polysilicon gate electrode (7) are displaced to the right in the center of the N column region (4); dividing the P column shielding region (3) into two parts and placing the two parts at two sides of the N column region (4); dividing the N + source region (11) into two parts and placing the two parts on two sides of the silicon dioxide isolation layer (6); an N-channel region (10) is added at the left of the silicon dioxide isolation layer (6); a P-field termination region (5) is added on the left side of the silicon dioxide isolation layer (6).
3. The super junction P-pillar and N-channel 4H-SiC-based VDMOS device with shielding effect of claim 1, wherein: the width of the P + polycrystalline silicon source electrode (8) is 0.4 mu m, and the height of the P + polycrystalline silicon source electrode is 0.75 mu m; the width of the P + polycrystalline silicon source electrode (9) is 0.9 mu m, and the height of the P + polycrystalline silicon source electrode is 0.75 mu m.
4. The super junction P-pillar and N-channel 4H-SiC-based VDMOS device with shielding effect of claim 1, wherein: the part of the P + polysilicon gate electrode (7) extending into the silicon dioxide isolation layer (6) is 1.25 mu m, and the part of the P + polysilicon gate electrode not extending into the silicon dioxide isolation layer (6) is 0.75 mu m; the width of the P + polycrystalline silicon gate electrode (7) is 0.4 mu m;
the length of the silicon dioxide isolation layer (6) embedded into the P column shielding region (3) is 2 microns, the thickness of the side wall is 0.05 microns, and the thickness of the lower portion of the P + polysilicon gate electrode (7) is 0.5 microns.
5. The super junction P-pillar and N-channel 4H-SiC-based VDMOS device with shielding effect of claim 1, wherein: the height of the N-channel region (10) is 1 mu m, and the width of the N-channel region is 0.2 mu m; the height of the N + source region (11) is 0.25 mu m, and the width of the N + source region is 0.4 mu m.
6. The super junction P-pillar and N-channel 4H-SiC-based VDMOS device with shielding effect of claim 1, wherein: the height of the P column shielding region (3) is 14 mu m; the height of the N column region (4) is 12.75 mu m.
7. The super junction P-pillar and N-channel 4H-SiC-based VDMOS device with shielding effect of claim 1, wherein: the height of the N + substrate region (2) is 3 mu m, and the width of the N + substrate region is 2 mu m; the height of the P + polycrystalline silicon drain electrode (1) is 0.5 mu m, and the width of the P + polycrystalline silicon drain electrode is 2 mu m.
8. The super junction P-pillar and N-channel 4H-SiC-based VDMOS device with shielding effect of claim 1, wherein: the doping concentration ranges of the P column shielding region (3), the N column region (4) and the P-electric field termination region (5) are 1 multiplied by 10 15 cm -3 ～5×10 16 cm -3 And the adjustment is carried out according to the size of the device and the required working current.
9. The super junction P-pillar and N-channel 4H-SiC-based VDMOS device with shielding effect of claim 1, wherein: an N-type VDMOS device can be changed into a P-type VDMOS device.
10. The super junction P-pillar and N-channel 4H-SiC-based VDMOS device with shielding effect of claim 1, wherein: the structure is equally applicable to lateral diodes, LIGBTs and LDMOS.
CN202210506265.3A 2022-05-10 2022-05-10 Super junction P column and N-channel 4H-SiC-based VDMOS device with shielding effect Pending CN114899219A (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
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CN117012810A (en) * 2023-10-07 2023-11-07 希力微电子(深圳)股份有限公司 Super-junction groove type power semiconductor device and preparation method thereof
CN117276347A (en) * 2023-10-26 2023-12-22 南京第三代半导体技术创新中心有限公司 High-reliability double-groove silicon carbide MOSFET device and manufacturing method

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117012810A (en) * 2023-10-07 2023-11-07 希力微电子(深圳)股份有限公司 Super-junction groove type power semiconductor device and preparation method thereof
CN117012810B (en) * 2023-10-07 2024-01-12 希力微电子(深圳)股份有限公司 Super-junction groove type power semiconductor device and preparation method thereof
CN117276347A (en) * 2023-10-26 2023-12-22 南京第三代半导体技术创新中心有限公司 High-reliability double-groove silicon carbide MOSFET device and manufacturing method
CN117276347B (en) * 2023-10-26 2024-04-12 南京第三代半导体技术创新中心有限公司 High-reliability double-groove silicon carbide MOSFET device and manufacturing method

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