CN113140636B - Trench gate type stacked gate SiC MOSFET device - Google Patents
Trench gate type stacked gate SiC MOSFET device Download PDFInfo
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- 239000002184 metal Substances 0.000 claims abstract description 61
- 229910052751 metal Inorganic materials 0.000 claims abstract description 61
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- 239000012535 impurity Substances 0.000 claims description 34
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- 229910018072 Al 2 O 3 Inorganic materials 0.000 claims description 2
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
- H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
Abstract
The invention relates to a trench gate type stacked gate SiC MOSFET device, and belongs to the technical field of semiconductors. The gate type stacked gate MOSFET introduces a PN junction at a gate polysilicon, and the gate structure is formed by stacking an N-type polysilicon layer, a gate-type P-type polysilicon layer and a gate-type gate contact metal layer. The improvement of the groove gate type stacked gate structure reduces the capacitive coupling area and distance between the gate and the source of the drain, thereby reducing gate charge and switching loss and obviously improving the switching performance of the device. Compared with the traditional groove type SiC MOSFET, the improved device has the advantage that the grid-drain charge is reduced by 68%.
Description
Technical Field
The invention belongs to the technical field of semiconductors, and relates to a trench gate type stacked gate SiCMOS (silicon-on-metal oxide semiconductor field effect transistor) device.
Background
SiC (silicon carbide) is a compound semiconductor material composed of silicon (Si) and carbon (C). SiC is considered to be a material for manufacturing power devices exceeding the Si limit, because it has not only the advantages that the dielectric breakdown field strength is 10 times that of Si and the band gap is 3 times that of Si, but also that necessary P-type and N-type control can be achieved in a wide range at the time of device manufacturing. Since SiC materials can be highly pressurized in majority carrier devices (schottky barrier diodes and MOSFETs) having a fast device structure, three characteristics of "high withstand voltage", "low on-resistance", and "high frequency" can be simultaneously realized. The drift layer resistance of the SiC device is smaller than that of the Si device, and high withstand voltage and low on-resistance can be simultaneously achieved with a MOSFET having a fast device structural feature without using conductivity modulation. The power MOSFET is a voltage control type power device, has the characteristics of simple gate drive circuit, short switching time, high power density and high conversion efficiency, and is widely applied to various power electronic systems. In principle, the MOSFET does not generate a tail current, and when the MOSFET is used in place of an IGBT, a large reduction in switching loss and a reduction in size of a heat sink can be achieved.
In the internal structure of the MOS tube, the grid is actually separated from the drain and the source by an insulating layer of silicon dioxide, which is equivalent to the existence of a capacitor. When the driving circuit controls the device, a charging and discharging process of the parasitic capacitor exists, the switching speed of the device is greatly reduced in the process, meanwhile, the power loss and the driving power in the switching process are increased, and the phenomenon is more obvious under the high-frequency working condition.
Disclosure of Invention
It is therefore an object of the present invention to provide a trench gate stacked gate SiCMOS device.
In order to achieve the purpose, the invention provides the following technical scheme:
a trench gate type stacked gate SiCMOS device is divided into two parts, wherein the first part is a conductive region, the second part is a control region, the structure of the device is bilaterally symmetrical and comprises a drain electrode metal contact region 1, an N + substrate 2, an N-drift region 3, a P-body region 4, a P + source region 5, an N + source region 6, a source electrode metal contact region 7, an insulating medium layer 8, N-polycrystalline silicon 9, P + polycrystalline silicon 10 and a gate electrode metal contact region 11;
the conductive region includes: a drain metal contact region 1, an N + substrate 2, an N-drift region 3, a P-body region 4, a P + source region 5, an N + source region 6 and a source metal contact region 7;
the drain metal contact region 1 is positioned on the lower surface of the N + substrate 2;
the N + substrate 2 is respectively positioned on the lower surface of the N-drift region 3 and the upper surface of the drain metal contact region 1;
the N-drift region 3 is positioned on the lower surface of the P-body region 4, the lower surface and the outer lower surface of the insulating medium layer 8 and is positioned on the upper surface of the N + substrate 2;
the P-body region 4 is respectively positioned on the upper surface of the N-drift region 3 and the lower surfaces of the P + source region 5 and the N + source region 6, and the side surface of the P-body region 5 is also contacted with the outer side surface of the insulating medium layer 8;
the P + source region 5 is positioned on the upper surface of the P-body region 4, meanwhile, the upper surface of the P + source region 5 is in contact with the source metal contact region 7, and the side surface of the P + source region 5 is in contact with the N + source region 6;
the N + source region 6 is positioned on the upper surface of the P-body region 5, meanwhile, the upper surface of the N + source region 6 is in contact with the source metal contact region 7, and the side surface of the N + source region 6 is in contact with the P + source region 5;
the source metal contact region 7 is positioned on the upper surfaces of the P + source region 5 and the N + source region 6;
the control area includes: an insulating medium layer 8, N-polycrystalline silicon 9, P + polycrystalline silicon 10 and a grid metal contact region 11;
the insulating medium layer 8 is positioned above the concave part of the N-drift region 3 and is positioned on the lower surfaces of the P + polycrystalline silicon 10 and the N-polycrystalline silicon 9, and the outer side of the insulating medium layer 8 is in contact with the P-body region 4 and the N + source region 6;
the N-polycrystalline silicon 9 is positioned between the P + polycrystalline silicon 10 and the insulating medium layer 8;
the P + polysilicon 10 is positioned between the N-polysilicon 9 and the insulating dielectric layer 8 of the grid metal contact region 11;
the gate metal contact region 11 is located between the P + polysilicon 10 and the insulating dielectric layer 8.
Optionally, the N + substrate 2 is doped with N-type impurities with a concentration of 5 × 10 19 cm -3 The N-drift region 3 is doped with N-type impurity at a concentration of 3X 10 15 cm -3 The P-body region 4 is doped with P-type impurities at a concentration of 2X 10 17 cm -3 The P + source region 5 is doped with P-type impurity at a concentration of 5 × 10 19 cm -3 The N + source region 6 is doped with N-type impurity with a concentration of 5 × 10 19 cm -3 N-polysilicon 9 doped with N-type impurity at a concentration of 5 × 10 17 cm -3 The P + polysilicon 10 is doped with P type impurity with the concentration of 5 x 10 19 cm -3 。
Optionally, the drain metal contact region 1 is made of Al, au, or Pt.
Optionally, the material of the source metal contact region 7 is Al, au, or Pt.
Optionally, the material of the gate metal contact region 11 is Al, au, or Pt.
Optionally, the insulating dielectric layer 8 is made of SiO 2 、SiN、Al 2 O 3 、AlN、MgO、Ga 2 O 3 、AlHfO x And HfSiON, or a combination of several of them.
The invention has the beneficial effects that: the groove type SiC MOSFET device provided by the invention changes the parasitic capacitance coupling structure of the device on the premise of ensuring that the forward conduction characteristic is not changed, thereby reducing the grid charge of the device and achieving the purpose of improving the switching performance of the device.
Additional advantages, objects, and features of the invention will be set forth in part in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from practice of the invention. The objectives and other advantages of the invention may be realized and attained by the means of the instrumentalities and combinations particularly pointed out hereinafter.
Drawings
For the purposes of promoting a better understanding of the objects, aspects and advantages of the invention, reference will now be made to the following detailed description taken in conjunction with the accompanying drawings in which:
FIG. 1 is a schematic diagram of a conventional trench-gate MOSFET structure;
FIG. 2 is a schematic diagram of a transistor structure of a square-wave stacked-gate MOSFET device according to the present invention;
FIG. 3 is a schematic diagram of a gate-type stacked-gate MOSFET device transistor structure provided in the present invention;
fig. 4 is an output characteristic curve of a conventional trench gate MOSFET, a return-type stacked gate MOSFET and a gate-type stacked gate MOSFET when T =300k, vg = 15v;
fig. 5 is a transfer characteristic curve of a gate type stacked gate MOSFET with T = 300K;
fig. 6 is a blocking characteristic curve of a conventional trench gate MOSFET, a return-type stacked gate MOSFET, and a gate-type stacked gate MOSFET when T =300k, vg =0 v;
fig. 7 is a gate charge curve of conventional trench-gate MOSFET, return-type stacked-gate MOSFET and gate-type stacked-gate MOSFET with T =300K and with device gate voltage increased from 0V to 15V;
fig. 8 is a gate electrode charging curve of a conventional trench gate MOSFET, a clip-gate MOSFET and a gate-type stacked-gate MOSFET with T =300K and a device gate voltage of 0V to 15V;
fig. 9 is a gate electrode feedback capacitance curve of T =300k, vg = -0v conventional trench gate MOSFET, return type stacked gate MOSFET and gate type stacked gate MOSFET;
FIG. 10 is a graph of switching losses for different switching frequencies of a conventional trench gate MOSFET;
FIG. 11 shows switching losses for different switching frequencies of a square-wave stacked gate MOSFET;
fig. 12 shows switching losses at different switching frequencies of a gate-type stacked gate MOSFET.
Reference numerals: the transistor comprises a 1-drain electrode metal contact region, a 2-N + substrate, a 3-N-drift region, a 4-P-body region, a 5-P + source region, a 6-N + source region, a 7-source electrode metal contact region, an 8-insulating medium layer, 9-N-polycrystalline silicon, 10-P + polycrystalline silicon and an 11-grid electrode metal contact region.
Detailed Description
The following embodiments of the present invention are provided by way of specific examples, and other advantages and effects of the present invention will be readily apparent to those skilled in the art from the disclosure herein. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention. It should be noted that the drawings provided in the following embodiments are only for illustrating the basic idea of the present invention in a schematic way, and the features in the following embodiments and examples may be combined with each other without conflict.
Wherein the showings are for the purpose of illustrating the invention only and not for the purpose of limiting the same, and in which there is shown by way of illustration only and not in the drawings in which there is no intention to limit the invention thereto; to better illustrate the embodiments of the present invention, some parts of the drawings may be omitted, enlarged or reduced, and do not represent the size of an actual product; it will be understood by those skilled in the art that certain well-known structures in the drawings and descriptions thereof may be omitted.
The same or similar reference numerals in the drawings of the embodiments of the present invention correspond to the same or similar components; in the description of the present invention, it should be understood that if there is an orientation or positional relationship indicated by terms such as "upper", "lower", "left", "right", "front", "rear", etc., based on the orientation or positional relationship shown in the drawings, it is only for convenience of description and simplification of description, but it is not an indication or suggestion that the referred device or element must have a specific orientation, be constructed in a specific orientation, and be operated, and therefore, the terms describing the positional relationship in the drawings are only used for illustrative purposes, and are not to be construed as limiting the present invention, and the specific meaning of the terms may be understood by those skilled in the art according to specific situations.
Fig. 1 is a schematic structural diagram of a conventional trench gate MOSFET.
Example 1:
as shown in fig. 2, the invention relates to a transistor structure of a trench type SiC MOSFET device, which comprises a trench type SiC MOSFET device structure, wherein the device is divided into two parts, the first part is a conductive region, and the second part is a control region, and the transistor structure is characterized in that: the structure is bilaterally symmetrical and comprises a drain metal contact region 1, an N + substrate 2, an N-drift region 3, a P-body region 4, a P + source region 5, an N + source region 6, a source metal contact region 7, an insulating medium layer 8, N-polycrystalline silicon 9, P + polycrystalline silicon 10 and a grid metal contact region 11.
The N + substrate 2 is positioned on the lower surface of the N-drift region 3 and the upper surface of the drain electrode metal contact region 1; the length of the horizontal direction is 8 μm, and the length of the vertical direction is 5 μm; doping N-type impurity with concentration of 5 × 10 19 cm -3 。
The N-drift region 3 is positioned on the lower surface of the P-body region 4, the lower surface and the outer lower surface of the insulating medium layer 8 and is also positioned on the upper surface of the N + high-concentration substrate layer 2; the length of the bottom of the N-drift region 3 in the horizontal direction is 8 micrometers, the distance between the bottom of the N-drift region 3 and the insulating medium layer 8 in the vertical direction is 12 micrometers, and the distance between the bottom of the N-drift region 3 and the P-body region 4 in the vertical direction is 12.4 micrometers; doping N-type impurity with a concentration of 3X 10 15 cm -3 。
The P-body region 4 is respectively positioned on the upper surface of the N-low concentration epitaxial layer 3 and the lower surfaces of the P + source region 6 and the N + source region 7, and the side surface of the P-body region 5 is also contacted with the outer side surface of the insulating medium layer 8; the length of the P-body region 4 in the horizontal direction is 2 mu m, and the length in the vertical direction is 0.5 mu m; the P-body region 4 is doped with P-type impurity at a concentration of 2X 10 17 cm -3 。
The P + source region 5 is positioned on the upper surface of the P-body region 4, meanwhile, the upper surface of the P + source region 5 is contacted with the source metal contact region 7, and the side surface of the P + source region 5 is contacted with the N + source region 6;the length of the P + source region 5 in the horizontal direction is 1.2 mu m, and the length of the P + source region in the vertical direction is 0.3 mu m; the P + source region 5 is doped with P-type impurities with a concentration of 5 × 10 19 cm -3 。
The N + source region 6 is positioned on the upper surface of the P-body region 5, meanwhile, the upper surface of the N + source region 6 is contacted with the source metal contact region 7, and the side surface of the N + source region 6 is contacted with the P + source region 5; the length of the N + source region 5 in the horizontal direction is 0.8 mu m, and the length of the N + source region in the vertical direction is 0.3 mu m; n-body region 4 doped with N-type impurity at a concentration of 5 × 10 19 cm -3 。
The source metal contact region 7 is positioned on the upper surfaces of the P + source region 5 and the N + source region 6;
the insulating medium layer 8 is positioned above the N & lt- & gt drift region 3, is simultaneously contacted with the lower surface and the outer side surface of the P & lt + & gt polycrystalline silicon 10, and has the thickness of 0.05 mu m.
The P + polysilicon 10 is positioned between the insulating medium layers 8 and completely surrounds the N-polysilicon 9; the length of the P + polysilicon 10 in the horizontal direction is 3.7 μm, the length in the vertical direction is 1.75 μm, and the concentration of the P-type impurity doped in the P + polysilicon 10 is 5 × 10 19 cm -3 。
Example 2:
as shown in fig. 2, the invention relates to a transistor structure of a trench type SiC MOSFET device with a double-gate stack, the device comprises a trench type SiC MOSFET device structure, the device is divided into two parts, the first part is a conductive region, the second part is a control region, and the transistor structure is characterized in that: the structure is bilaterally symmetrical and comprises a drain electrode metal contact region 1, an N + substrate 2, an N-drift region 3, a P-body region 4, a P + source region 5, an N + source region 6, a source electrode metal contact region 7, an insulating medium layer 8, N-polycrystalline silicon 9, P + polycrystalline silicon 10 and a grid electrode metal contact region 11.
The N + substrate 2 is positioned on the lower surface of the N-drift region 3 and the upper surface of the drain metal contact region 1; the length of the horizontal direction is 8 μm, and the length of the vertical direction is 5 μm; doping N-type impurity with concentration of 5 × 10 19 cm -3 。
The N-drift region 3 is positioned on the lower surface of the P-body region 4, the lower surface and the outer lower surface of the insulating medium layer 8 and is also positioned on the upper surface of the N + high-concentration substrate layer 2; the length of the bottom of the N-drift region 3 in the horizontal direction is 8 mu m, the distance between the bottom of the N-drift region 3 and the insulating medium layer 8 in the vertical direction is 12 mu m, and the bottom of the N-drift region 3 and the bottom of the insulating medium layer 8 are in contact with each otherThe distance between the P-body regions 4 in the vertical direction is 12.4 mu m; doping N-type impurity with a concentration of 3X 10 15 cm -3 。
The P-body region 4 is respectively positioned on the upper surface of the N-low concentration epitaxial layer 3 and the lower surfaces of the P + source region 6 and the N + source region 7, and the side surface of the P-body region 5 is also contacted with the outer side surface of the insulating medium layer 8; the length of the P-body region 4 in the horizontal direction is 2 mu m, and the length in the vertical direction is 0.5 mu m; the P-body region 4 is doped with P-type impurity at a concentration of 2X 10 17 cm -3 。
The P + source region 5 is positioned on the upper surface of the P-body region 4, meanwhile, the upper surface of the P + source region 5 is contacted with the source metal contact region 7, and the side surface of the P + source region 5 is contacted with the N + source region 6; the length of the P + source region 5 in the horizontal direction is 1.2 mu m, and the length of the P + source region in the vertical direction is 0.3 mu m; the P + source region 5 is doped with P type impurity with a concentration of 5 × 10 19 cm -3 。
The N + source region 6 is positioned on the upper surface of the P-body region 5, meanwhile, the upper surface of the N + source region 6 is contacted with the source metal contact region 7, and the side surface of the N + source region 6 is contacted with the P + source region 5; the length of the N + source region 5 in the horizontal direction is 0.8 mu m, and the length of the N + source region in the vertical direction is 0.3 mu m; the N-body region 4 is doped with N-type impurity at a concentration of 5X 10 19 cm -3 。
The source metal contact region 7 is positioned on the upper surfaces of the P + source region 5 and the N + source region 6;
the insulating medium layer 8 is positioned above the N & lt- & gt drift region 3, is simultaneously contacted with the lower surface and the outer side surface of the P & lt + & gt polycrystalline silicon 10, and has the thickness of 0.05 mu m.
The N-polysilicon 9 is completely surrounded by the P + polysilicon 10; the length of the N-polycrystalline silicon 9 in the horizontal direction is 3.1 mu m, and the length of the N-polycrystalline silicon in the vertical direction is 0.95 mu m; n-polysilicon 9 doped with N-type impurity at a concentration of 5 × 10 17 cm -3 。
The P + polysilicon 10 is positioned between the N-polysilicon 9 insulating medium layers 8 and completely surrounds the N-polysilicon 9; the length of the P + polysilicon 10 in the horizontal direction is 3.9 μm, the length in the vertical direction is 1.75 μm, and the concentration of the P-type impurity doped in the P + polysilicon 10 is 5 × 10 19 cm -3 。
Example 3:
the invention relates to a gate type stacked gate groove type SiC MOSFET device transistor structure, which comprises a groove type SiC MOSFET device structure, wherein the device is divided into two parts and is characterized in that: the structure is bilaterally symmetrical and comprises a drain metal contact region 1, an N + substrate 2, an N-drift region 3, a P-body region 4, a P + source region 5, an N + source region 6, a source metal contact region 7, an insulating medium layer 8, N-polycrystalline silicon 9, P + polycrystalline silicon 10 and a grid metal contact region 11.
The N + substrate 2 is positioned on the lower surface of the N-drift region 3 and the upper surface of the drain electrode metal contact region 1; the length of the horizontal direction is 8 μm, and the length of the vertical direction is 5 μm; doping N-type impurity with concentration of 5 × 10 19 cm -3 。
The N-drift region 3 is positioned on the lower surface of the P-body region 4, the lower surface and the outer side lower surface of the insulating medium layer 8 and is also positioned on the upper surface of the N + high-concentration substrate layer 2; the length of the bottom of the N-drift region 3 in the horizontal direction is 8 micrometers, the distance between the bottom of the N-drift region 3 and the insulating medium layer 8 in the vertical direction is 12 micrometers, and the distance between the bottom of the N-drift region 3 and the P-body region 4 in the vertical direction is 12.4 micrometers; doping N-type impurity with a concentration of 3X 10 15 cm -3 。
The P-body region 4 is respectively positioned on the upper surface of the N-low concentration epitaxial layer 3 and the lower surfaces of the P + source region 6 and the N + source region 7, and the side surface of the P-body region 5 is also contacted with the outer side surface of the insulating medium layer 8; the length of the P-body region 4 in the horizontal direction is 2 mu m, and the length in the vertical direction is 0.5 mu m; the P-body region 4 is doped with P-type impurity at a concentration of 2X 10 17 cm -3 。
The P + source region 5 is positioned on the upper surface of the P-body region 4, meanwhile, the upper surface of the P + source region 5 is contacted with the source metal contact region 7, and the side surface of the P + source region 5 is contacted with the N + source region 6; the length of the P + source region 5 in the horizontal direction is 1.2 mu m, and the length of the P + source region in the vertical direction is 0.3 mu m; the P + source region 5 is doped with P type impurity with a concentration of 5 × 10 19 cm -3 。
The N + source region 6 is positioned on the upper surface of the P-body region 5, meanwhile, the upper surface of the N + source region 6 is contacted with the source metal contact region 7, and the side surface of the N + source region 6 is contacted with the P + source region 5; the length of the N + source region 5 in the horizontal direction is 0.8 mu m, and the length of the N + source region in the vertical direction is 0.3 mu m; n-body region 4 doped with N-type impurity at a concentration of 5 × 10 19 cm -3 。
The source metal contact region 7 is positioned on the upper surfaces of the P + source region 5 and the N + source region 6; the vertical length of the upper end of the source metal contact region 7 is 0.1 μm, and the horizontal length of the two parts of the lower end of the source metal contact region 7 is 0.2 μm.
The insulating medium layer 8 is positioned above the N-drift region 3 and is also positioned on the lower surfaces of the P + polycrystalline silicon 10 and the N-polycrystalline silicon 9; the thickness was 0.05. Mu.m.
The N-polycrystalline silicon 9 is positioned between the P + polycrystalline silicon 10 and the insulating medium layer 8; the length of the N-polycrystalline silicon 9 in the horizontal direction is 3.1 mu m, and the length of the N-polycrystalline silicon in the vertical direction is 0.95 mu m; n-polysilicon 9 doped with N-type impurity with concentration of 5 × 10 17 cm -3 。
The P + polysilicon 10 is positioned between the N-polysilicon 9 and the insulating dielectric layer 8 of the grid metal contact region 11; p + polysilicon 10 doped with P-type impurity with concentration of 5 × 10 19 cm- 3 (ii) a The vertical length of the upper end of the P + polycrystalline silicon 10 is 0.1 mu m; the horizontal length of the two lower parts of the P + polysilicon 10 is 0.2 mu m.
Fig. 4 is an output characteristic curve of a conventional trench gate MOSFET, a return-type stacked gate MOSFET and a gate-type stacked gate MOSFET when T =300k, vg =15v, the operating drain current of the device increases linearly with the increase of the drain voltage under a voltage of 0-20V, and the three values are substantially the same.
Fig. 5 is a graph of output characteristics of T =300K, for different gate voltages of a gate-type stacked-gate MOSFET, and the drain current of the device increases with the gate voltage under the same drain voltage.
Fig. 6 is a blocking characteristic curve of the conventional trench gate MOSFET, the conventional clip gate MOSFET, and the conventional gate stack MOSFET when T =300k, vg =0v, the drain current of the device does not change significantly with the increase of the drain voltage before avalanche breakdown occurs, and the breakdown voltages of the three devices do not differ greatly.
Fig. 7 shows the gate charge curves of T =300K for conventional trench-gate MOSFETs, return-type stacked-gate MOSFETs and gate-type stacked-gate MOSFETs, with the device gate voltage being increased from 0V to 15V. The total amount of gate charges and the total amount of gate drain charges of the conventional trench gate MOSFET, the conventional square-wave gate MOSFET and the conventional gate-type stacked gate MOSFET are reduced in sequence.
Fig. 8 shows the gate electrode charging curves of T =300K for conventional trench gate MOSFETs, clip-type stacked gate MOSFETs and gate-type stacked gate MOSFETs, with the device gate voltage being increased from 0V to 15V. Compared with the traditional trench gate MOSFET, the traditional return type stacked gate MOSFET and the traditional gate type stacked gate MOSFET, the charging time of the traditional trench gate MOSFET, the traditional return type stacked gate MOSFET and the traditional gate type stacked gate MOSFET is reduced.
Fig. 9 is a gate electrode feedback capacitance curve of T =300k, vg =0v conventional trench gate MOSFET, return-type stacked gate MOSFET, and gate-type stacked gate MOSFET. The feedback capacitances of the three devices are not greatly different under high voltage.
FIG. 10 shows switching losses of a conventional trench-gate MOSFET at different switching frequencies, a device operating voltage of 800V, and a current density of 200A/cm flowing through the device 2 . Device turn-on loss E on Device turn-off loss E for the loss generated during the gate voltage from 0V to 15V off Is the loss generated during the gate voltage is increased from 0V to 15V. The turn-off loss of the device accounts for most of the total switching loss, and the total power consumption of the device is obviously larger than that of the other two devices under the switching frequency of 1MHz and 10 MHz.
FIG. 11 shows the switching losses of the square-wave stacked-gate MOSFET at different switching frequencies, the device operating voltage is 800V, and the current density flowing through the device is 200A/cm 2 . Device turn-on loss E on Device turn-off loss E for the loss generated during the gate voltage from 0V to 15V off Is the loss generated during the gate voltage is increased from 0V to 15V. The turn-on loss of the device does not change obviously with the increase of the frequency, and the turn-off loss of the device is obviously reduced with the increase of the frequency. Under the switching frequency of 1MHz and 10MHz, the power consumption of the switch of the square-wave stacked gate MOSFET is obviously smaller than that of the traditional trench gate MOSFET. The improvement of the structure reduces the parasitic capacitance, and the loss caused by charging and discharging the parasitic capacitance in the switching process is reduced.
FIG. 12 shows the switching losses at different switching frequencies of a gate-type stacked-gate MOSFET, the device operating voltage is 800V, and the current density flowing through the device is 200A/cm 2 . Device turn-on loss E on Device turn-off loss E for the loss generated during the gate voltage from 0V to 15V off Is the loss generated during the gate voltage is increased from 0V to 15V. The turn-on loss of the device does not change obviously with the increase of the frequency, and the turn-off loss of the device is obviously reduced with the increase of the frequency. Under the switching frequency of 1MHz and 10MHz, the power consumption of the gate-type stacked gate MOSFET switch is obviously smaller than that of the traditional trench gate MOSFET. The improvement of the structure reduces the parasitic capacitance, and the loss caused by charging and discharging the parasitic capacitance in the switching processAnd thus is reduced.
Table 1 shows the comparison of key performance indexes of the conventional trench gate MOSFET, the conventional clip gate MOSFET, and the conventional gate type clip gate MOSFET, and the table includes on resistance, breakdown voltage gate-drain charge, and feedback capacitance. It can be seen that the on-resistance of the three MOSFETs are the same; the breakdown voltage has little influence; the optimal gate type stack gate for gate-drain charge performance is 229.05nC/cm 2 Compared with 735.56nC/cm of the traditional trench gate 2 The reduction is reduced by 68%, and the performance is extremely excellent.
TABLE 1 comparison of key performance indicators for different MOSFETs
Table 2 shows the switching losses of conventional trench-gate MOSFET, clip-type stacked-gate MOSFET and gate-type stacked-gate MOSFET at 100KHz, 1MHz and 1MHz switching frequencies. When the three devices work under the switching frequency of 100KHz, the turn-on loss of the three devices is not greatly different; the turn-off loss of the gate type stacked gate MOSFET is reduced by 88.9 percent compared with that of the traditional trench gate MOSFET; the total switching loss of the gate-type stacked gate MOSFET is reduced by 78% compared with that of the conventional trench gate MOSFET. When the three devices work under the switching frequency of 1MHz, the turn-on loss of the three devices is not greatly different; the turn-off loss of the gate type stacked gate MOSFET is reduced by 94.9 percent compared with that of the traditional trench gate MOSFET; the total switching loss of the gate-type stacked gate MOSFET is reduced by 90.4% compared with that of the conventional trench gate MOSFET. When the three devices work under the switching frequency of 10MHz, the opening loss has no great difference; the turn-off loss gate type stacked gate MOSFET is reduced by 95.3% compared with the traditional trench gate MOSFET; the total switching loss of the gate-type stacked gate MOSFET is the lowest, and is reduced by 90.74% compared with the conventional trench gate MOSFET. The data in the table show that the turn-off loss and the total switching power consumption of the gate type stacked gate MOSFET are excellent, and the switching loss of the gate type stacked gate MOSFET is gradually reduced along with the increase of the switching frequency, so that the excellent high-frequency performance is shown.
TABLE 2 comparison of switching losses for different MOSFETs
Finally, the above embodiments are only intended to illustrate the technical solutions of the present invention and not to limit the present invention, and although the present invention has been described in detail with reference to the preferred embodiments, it will be understood by those skilled in the art that modifications or equivalent substitutions may be made on the technical solutions of the present invention without departing from the spirit and scope of the technical solutions, and all of them should be covered by the claims of the present invention.
Claims (6)
1. A trench gate type stacked gate SiC MOSFET device is divided into two parts, wherein the first part is a conductive region, and the second part is a control region, and is characterized in that: the structure of the device is bilaterally symmetrical and comprises a drain electrode metal contact region (1), an N + substrate (2), an N-drift region (3), a P-body region (4), a P + source region (5), an N + source region (6), a source electrode metal contact region (7), an insulating medium layer (8), N-polycrystalline silicon (9), P + polycrystalline silicon (10) and a grid electrode metal contact region (11);
the conductive region includes: the transistor comprises a drain electrode metal contact region (1), an N + substrate (2), an N-drift region (3), a P-body region (4), a P + source region (5), an N + source region (6) and a source electrode metal contact region (7);
the drain electrode metal contact region (1) is positioned on the lower surface of the N + substrate (2);
the N + substrate (2) is respectively positioned on the lower surface of the N-drift region (3) and the upper surface of the drain electrode metal contact region (1);
the N-drift region (3) is positioned on the lower surface of the P-body region (4), the lower surface and the outer lower surface of the insulating medium layer (8) and is positioned on the upper surface of the N + substrate (2) at the same time;
the P-body region (4) is respectively positioned on the upper surface of the N-drift region (3) and the lower surfaces of the P + source region (5) and the N + source region (6), and meanwhile, the side surface of the P-body region (4) is also contacted with the outer side surface of the insulating medium layer (8);
the P + source region (5) is located on the upper surface of the P-body region (4), meanwhile, the upper surface of the P + source region (5) is in contact with the source metal contact region (7), and the side surface of the P + source region (5) is in contact with the N + source region (6);
the N + source region (6) is positioned on the upper surface of the P-body region (4), the upper surface of the N + source region (6) is in contact with the source metal contact region (7), and the side surface of the N + source region (6) is in contact with the P + source region (5);
the source metal contact region (7) is positioned on the upper surfaces of the P + source region (5) and the N + source region (6);
the control area includes: the silicon-based gate structure comprises an insulating medium layer (8), N-polycrystalline silicon (9), P + polycrystalline silicon (10) and a gate metal contact region (11);
the insulating medium layer (8) is positioned above the concave part of the N-drift region (3) and is positioned on the lower surfaces of the P + polysilicon (10) and the N-polysilicon (9), and the outer side of the insulating medium layer (8) is in contact with the P-body region (4) and the N + source region (6);
the bottom surface of the N-polycrystalline silicon (9) is in contact with the insulating medium layer (8);
the P + polysilicon (10) is positioned between the N-polysilicon (9) and the grid metal contact region (11), and two gate-shaped bottom surfaces of the P + polysilicon are contacted with the insulating medium layer (8);
the grid metal contact region (11) is positioned between the P + polysilicon (10) and the insulating medium layer (8);
the P + polysilicon (10) is in a gate shape and covers the left side surface, the right side surface and the top surface of the N-polysilicon (9); the gate metal contact region (11) is gate-shaped and covers the left side surface, the right side surface and the top surface of the P + polysilicon (10).
2. The trench-gated, stacked-gate SiC MOSFET device of claim 1, wherein: the N + substrate (2) is doped with N-type impurities with the concentration of 5 multiplied by 10 19 cm -3 The N-drift region (3) is doped with N-type impurities at a concentration of 3X 10 15 cm -3 The P-body region (4) is doped with a P-type impurity at a concentration of 2X 10 17 cm -3 The P + source region (5) is doped with P-type impurities at a concentration of 5 × 10 19 cm -3 The N + source region (6) is doped with N type impurity at a concentration of 5X 10 19 cm -3 N-polysilicon (9) doped with N-type impurity at a concentration of 5X 10 17 cm -3 P + polysilicon (10) doped with P-type impurity at a concentration of 5 × 10 19 cm -3 。
3. The trench-gated, stacked-gate SiC MOSFET device of claim 1, wherein: the drain electrode metal contact region (1) is made of Al, au or Pt.
4. The trench-gated, stacked-gate SiC MOSFET device of claim 1, wherein: the source electrode metal contact region (7) is made of Al, au or Pt.
5. The trench-gate stacked-gate SiC MOSFET device of claim 1, wherein: the material of the grid metal contact region (11) is Al, au or Pt.
6. The trench-gated, stacked-gate SiC MOSFET device of claim 1, wherein: the insulating medium layer (8) adopts SiO 2 、SiN、Al 2 O 3 、AlN、MgO、Ga 2 O 3 、AlHfO x And HfSiON, or a combination of several of them.
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| CN103545356A (en) * | 2012-07-10 | 2014-01-29 | 台湾积体电路制造股份有限公司 | Novel metal/polysilicon gate trench power MOSFET |
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| JP4917246B2 (en) * | 2003-11-17 | 2012-04-18 | ローム株式会社 | Semiconductor device and manufacturing method thereof |
| JP5700027B2 (en) * | 2012-12-07 | 2015-04-15 | トヨタ自動車株式会社 | Semiconductor device |
| WO2019169361A1 (en) * | 2018-03-01 | 2019-09-06 | Hamza Yilmaz | Self-aligned trench mosfet structures and methods |
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| JP2003124468A (en) * | 1993-09-17 | 2003-04-25 | Toshiba Corp | Insulated gate type semiconductor element |
| CN103545356A (en) * | 2012-07-10 | 2014-01-29 | 台湾积体电路制造股份有限公司 | Novel metal/polysilicon gate trench power MOSFET |
| CN104810390A (en) * | 2014-01-29 | 2015-07-29 | 爱思开海力士有限公司 | Transistor having dual work function buried gate electrode and method for fabricating the same |
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