CN114203821A - SiC groove type MOSFET structure with built-in heterojunction diode - Google Patents

SiC groove type MOSFET structure with built-in heterojunction diode Download PDF

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CN114203821A
CN114203821A CN202111402859.1A CN202111402859A CN114203821A CN 114203821 A CN114203821 A CN 114203821A CN 202111402859 A CN202111402859 A CN 202111402859A CN 114203821 A CN114203821 A CN 114203821A
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source
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base
current spreading
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周新田
张仕达
贾云鹏
胡冬青
吴郁
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Beijing University of Technology
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Abstract

The invention provides a SiC groove type MOSFET structure with a built-in heterojunction diode, which sequentially comprises a drain electrode metal layer, an N + drain region and an N-drift region from bottom to top; the current spreading layer CSL is positioned on the upper surface of the N-drift region; the P-base region is positioned on the upper surface of the current spreading layer CSL; the P-plus area and the N-source area are all positioned on the upper surface of the P-base area and are mutually arranged in parallel; the P-shielding region is positioned on the upper surface of the N-drift region, the gate oxide is positioned on the upper surface of the left P-shielding region, the polycrystalline silicon source is positioned on the upper surface of the right P-shielding region, and the polycrystalline silicon gate is positioned on the upper surface of the gate oxide; the isolation oxygen is positioned on the upper surfaces of the N-source area and the polysilicon gate; and the source metal area is positioned on the upper surfaces of the P-plus area, the partial N-source area and the polycrystalline silicon source. The invention has the characteristics of high switching speed, low power loss and good reverse recovery characteristic.

Description

SiC groove type MOSFET structure with built-in heterojunction diode
Technical Field
The invention relates to the technical field of semiconductors, in particular to a SiC groove type MOSFET structure with a built-in heterojunction diode.
Background
In power electronic system applications, SiC power semiconductor devices are often required to withstand large voltages, which can concentrate the electric field at the trench corners, leading to premature device breakdown. J.Tan et al propose SiC trench power MOSFET with P-type shielding region in 1998, the electric field peak value when the device is broken down is transferred from the gate oxide layer to the PN junction formed by the P-type shielding region and the N-type drift region, the reliability of the gate oxide is improved, and meanwhile, the current spreading layer is introduced to further reduce the characteristic on-resistance and improve the conductivity. However, when the diode is operated in the reverse direction, current needs to pass through the parasitic body diode, which not only results in higher conduction voltage drop, but also has poor reverse recovery capability.
Disclosure of Invention
In order to solve the problems of the groove type SiC power MOSFET, the invention provides a SiC groove type MOSFET structure with a built-in heterojunction diode. The technical problem to be solved by the invention is realized by the following technical scheme:
one embodiment of the present invention provides a SiC trench MOSFET structure with a built-in heterojunction diode, comprising:
an N-drift region (3);
an N + drain region (2) located at a lower surface of the N-drift region (3);
the drain electrode metal layer (1) is positioned on the lower surface of the N + drain electrode region (2);
the current spreading layer CSL is divided into a left part, a middle part and a right part, and the left current spreading layer CSL (7-1), the middle current spreading layer CSL (7-2) and the right current spreading layer CSL (7-3) are all positioned on the upper surface of the N-drift region (3);
the P-base area is divided into a left part, a middle part and a right part, the left side P-base area (5-1), the middle part P-base area (5-2) and the right side P-base area (5-3) are arranged, the left side P-base area (5-1) is positioned on the upper surface of the left side current spreading layer CSL (7-1), the middle part P-base area (5-2) is positioned on the upper surface of the middle part current spreading layer CSL (7-2), and the right side P-base area (5-3) is positioned on the upper surface of the left side current spreading layer CSL (7-3).
The N-source area is divided into four parts, namely a leftmost N-source area (9-1), a middle left N-source area (9-2), a middle right N-source area (9-3) and a rightmost N-source area (9-4), wherein the leftmost N-source area (9-1) is positioned on the upper surface of the left P-base area (5-1), the middle left N-source area (9-2) and the middle right N-source area (9-3) are both positioned on the upper surface of the middle P-base area (5-2), and the rightmost N-source area (9-4) is positioned on the upper surface of the right P-base area (5-3);
the P-plus area is divided into three parts, a left P-plus area (8-1), a middle P-plus area (8-2) and a right P-plus area (8-3), the left P-plus area (8-1) is positioned on the upper surface of the left P-base area (5-1), the left side of the leftmost N-source area (9-1), a middle P-plus area (8-2) is positioned on the upper surface of the middle P-base area (5-2), the middle of the middle left side N-source area (9-2) and the middle right side N-source area (9-3), the right side P-plus area (8-3) is positioned on the upper surface of the right side P-base area (5-3), and the right side of the rightmost N-source area (9-4);
a polysilicon gate (6);
a polycrystalline silicon source (13) positioned on the right side of the middle P-base region (5-2) and the middle current spreading layer CSL (7-2), and on the left side of the right P-base region (5-3) and the right current spreading layer CSL (7-3);
gate oxides (11) positioned on the left side, the right side and the lower surface of the polysilicon gate (6);
the P-shielding area is divided into two parts, namely a left side P-shielding area (4-1) and a right side P-shielding area (4-2), the left side P-shielding area (4-1) is located on the upper surface of the N-drift area (3), the lower surface of the gate oxide (11), the right side P-shielding area (4-1) is located on the lower surface of the polycrystalline silicon source (13), the upper surface of the N-drift area (3) is arranged, and all the P-shielding areas are grounded;
the isolation oxygen (10) is arranged on the upper surfaces of the leftmost N-source area (9-1), the polysilicon gate (6) and the left N-source area (9-2) in the part;
the source metal layer (12) is positioned on the upper surfaces of the left P-plus area (8-1), the partial leftmost N-source area (9-1), the isolated oxygen (10), the partial middle left N-source area (9-2), the middle P-plus area (8-2), the middle right N-source area (9-3), the polycrystalline silicon source (13), the rightmost N-source area (9-4) and the right P-plus area (8-3);
a polycrystalline silicon source (13) is in contact with the N-drift region (3) to form a heterojunction, the polycrystalline silicon source is a heterojunction anode, and the N-drift region is a heterojunction cathode;
preferably, the thickness of the gate oxide is 40nm to 150 nm.
Preferably, the polysilicon gate is made of polysilicon, the polysilicon is doped in an N-type manner, the doping element is phosphorus, and the doping concentration is 1 × 1019～1×1020cm-3。
Preferably, the polycrystalline silicon source material is polycrystalline silicon, the polycrystalline silicon source material is in contact with the N-drift region to form a heterojunction, the heterojunction is used as an anode of the heterojunction, the polycrystalline silicon is doped in an N type, a doping element is a P element, and the doping concentration is 1 multiplied by 1019～1×1020cm-3；
Preferably, the N-drift region is SiC, the doping type is N-type epitaxial doping, the doping element is nitrogen element or phosphorus element, and the doping concentration is 1 x 1013～5×1016cm-3The thickness is 5 to 30 μm.
Preferably, the current spreading layer CSL is SiC, the doping type is N-type epitaxial doping, the doping element is nitrogen or phosphorus, and the doping concentration is 1 × 1016～1×1018cm-3The thickness is 1 to 5 μm.
Preferably, the P-shielding region is SiC, the doping type is P-type ion implantation, the doping element is aluminum element or boron element, and the doping concentration is 1 × 1018～1×1020cm-3The thickness is 1 to 5 μm.
Preferably, the N + drain region is doped in an N type, the doping element is nitrogen element or phosphorus element, and the doping concentration is 1 × 1018～1×1020cm-3。
Preferably, the N-source region is doped in an N type, the doping element is nitrogen element or phosphorus element, and the doping concentration is 1 x 1018～1×1020cm-3The thickness is 0.5 to 1.5 μm.
Preferably, the P-base region is doped in a P type, the doping element is aluminum element or boron element, and the doping concentration is 1 × 1017～8×1017cm-3The thickness is 0.5 to 1.5 μm.
Preferably, the P-plus region is doped in a P type, the doping element is aluminum element or boron element, and the doping concentration is 1 × 1018～1×1020cm-3The thickness is 0.5 to 1.5 μm.
Advantageous effects
The invention provides a SiC groove type MOSFET structure with a built-in heterojunction diode, when the structure works in a first quadrant, a P-shielding region can effectively protect a gate oxide and a polycrystalline silicon source, and the breakdown capability is not obviously reduced while the electric field concentration at the corner of a groove is avoided; the addition of the current expansion layer CSL widens a current channel, and although the channel density is reduced by half, the conduction capability of the current expansion layer CSL is not degraded; in addition, the gate-drain capacitance C is reduced due to the reduced coupling area between the gate and the drainGDAnd gate charge QGGreatly reduced and obviously increased switching speed. When the MOSFET works in the third quadrant, the current does not pass through the parasitic body diode any more, but passes through a heterojunction diode formed by a polycrystalline silicon source and an N-drift region, the conduction voltage drop is reduced to 0.5V from the original 2.7V, and in addition, the heterojunction is a unipolar device, so that the device is always in a unipolar conduction mode, and the bipolar conduction mode conducted by the parasitic body diode is avoided, therefore, the power loss can be greatly reduced, and the reverse recovery characteristic of the device is improved.
Drawings
FIG. 1 is a diagram of a structure of a SiC trench MOSFET with a built-in heterojunction diode according to the present invention;
fig. 2 is a structural view of a conventional SiC trench MOSFET.
Detailed Description
The principles and features of this invention are described in connection with the drawings, which are set forth as examples only and not intended to limit the scope of the invention.
Example one
In this embodiment, an SiC trench MOSFET structure with a built-in heterojunction diode includes:
an N-drift region (3);
an N + drain region (2) located at a lower surface of the N-drift region (3);
the drain electrode metal layer (1) is positioned on the lower surface of the N + drain electrode region (2);
the current spreading layer CSL is divided into a left part, a middle part and a right part, and the left current spreading layer CSL (7-1), the middle current spreading layer CSL (7-2) and the right current spreading layer CSL (7-3) are all positioned on the upper surface of the N-drift region (3);
the P-base area is divided into a left part, a middle part and a right part, the left side P-base area (5-1), the middle part P-base area (5-2) and the right side P-base area (5-3) are arranged, the left side P-base area (5-1) is positioned on the upper surface of the left side current spreading layer CSL (7-1), the middle part P-base area (5-2) is positioned on the upper surface of the middle part current spreading layer CSL (7-2), and the right side P-base area (5-3) is positioned on the upper surface of the left side current spreading layer CSL (7-3).
The N-source area is divided into four parts, namely a leftmost N-source area (9-1), a middle left N-source area (9-2), a middle right N-source area (9-3) and a rightmost N-source area (9-4), wherein the leftmost N-source area (9-1) is positioned on the upper surface of the left P-base area (5-1), the middle left N-source area (9-2) and the middle right N-source area (9-3) are both positioned on the upper surface of the middle P-base area (5-2), and the rightmost N-source area (9-4) is positioned on the upper surface of the right P-base area (5-3);
the P-plus area is divided into three parts, a left P-plus area (8-1), a middle P-plus area (8-2) and a right P-plus area (8-3), the left P-plus area (8-1) is positioned on the upper surface of the left P-base area (5-1), the left side of the leftmost N-source area (9-1), a middle P-plus area (8-2) is positioned on the upper surface of the middle P-base area (5-2), the middle of the middle left side N-source area (9-2) and the middle right side N-source area (9-3), the right side P-plus area (8-3) is positioned on the upper surface of the right side P-base area (5-3), and the right side of the rightmost N-source area (9-4);
a polysilicon gate (6);
a polycrystalline silicon source (13) positioned on the right side of the middle P-base region (5-2) and the middle current spreading layer CSL (7-2), and on the left side of the right P-base region (5-3) and the right current spreading layer CSL (7-3);
gate oxides (11) positioned on the left side, the right side and the lower surface of the polysilicon gate (6);
the P-shielding area is divided into two parts, namely a left side P-shielding area (4-1) and a right side P-shielding area (4-2), the left side P-shielding area (4-1) is located on the upper surface of the N-drift area (3), the lower surface of the gate oxide (11), the right side P-shielding area (4-1) is located on the lower surface of the polycrystalline silicon source (13), the upper surface of the N-drift area (3) is arranged, and all the P-shielding areas are grounded;
the isolation oxygen (10) is arranged on the upper surfaces of the leftmost N-source area (9-1), the polysilicon gate (6) and the left N-source area (9-2) in the part;
the source metal layer (12) is positioned on the upper surfaces of the left P-plus area (8-1), the partial leftmost N-source area (9-1), the isolated oxygen (10), the partial middle left N-source area (9-2), the middle P-plus area (8-2), the middle right N-source area (9-3), the polycrystalline silicon source (13), the rightmost N-source area (9-4) and the right P-plus area (8-3);
a polycrystalline silicon source (13) is in contact with the N-drift region (3) to form a heterojunction, the polycrystalline silicon source is a heterojunction anode, and the N-drift region is a heterojunction cathode;
furthermore, the materials of the gate oxide (11) and the isolation oxygen (10) are both SiO2。
Furthermore, the material of the polysilicon gate (6) is polysilicon, the polysilicon is doped in an N type, the doping element is P element, and the doping concentration is 1 multiplied by 1019～1×1020cm-3。
Furthermore, the polycrystalline silicon source (13) is made of polycrystalline silicon, the polycrystalline silicon is doped in an N type, the doping element is P element, and the doping concentration is 1 multiplied by 1019～1×1020cm-3And forming a heterojunction in contact with the N-drift region.
Furthermore, the N + drain region (2) is doped in an N type, the doping element is nitrogen element or phosphorus element, and the doping concentration is 1 multiplied by 1018～1×1020cm-3。
Further, the N-drift region (3) is SiC, the doping type is N-type epitaxial doping, the doping element is nitrogen element or phosphorus element, and the doping concentration is 1 multiplied by 1013～5×1016cm-3The thickness is 5 to 30 μm.
Furthermore, the P-base region is doped in a P type, the doping element is aluminum element or boron element, and the doping concentration is 1 multiplied by 1017～8×1017cm-3The thickness is 0.5 to 1.5 μm.
Furthermore, the N-source region is doped in N type, the doping element is nitrogen element or phosphorus element, and the doping concentration is 1 × 1018～1×1020cm-3The thickness is 0.5 to 1.5 μm.
Furthermore, the P-plus area is doped in P type, the doping element is aluminum element or boron element, and the doping concentration is 1 multiplied by 1018～1×1020cm-3The thickness is 0.5 to 1.5 μm.
Further, the current spreading layer CSL is doped in an N type, the doping element is nitrogen element or phosphorus element, and the doping concentration is 1 × 1016～1×1018cm-3The thickness is 1 to 5 μm.
Furthermore, the P-shielding region is doped in a P type, the doping element is aluminum element or boron element, and the doping concentration is 1 multiplied by 1018～1×1020cm-3The thickness is 1 to 5 μm.
Further, the thickness of the gate oxide (11) is 40nm to 150 nm.
In the description of the present invention, the terms "first" and "second" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implying any number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature.
The foregoing is a more detailed description of the invention in connection with specific preferred embodiments and it is not intended that the invention be limited to these specific details. For those skilled in the art to which the invention pertains, several simple deductions or substitutions can be made without departing from the spirit of the invention, and all shall be considered as belonging to the protection scope of the invention.

Claims (6)

1. A SiC trench MOSFET structure with a built-in heterojunction diode, comprising:
an N-drift region (3);
an N + drain region (2) located at a lower surface of the N-drift region (3);
the drain electrode metal layer (1) is positioned on the lower surface of the N + drain electrode region (2);
the current spreading layer CSL is divided into a left part, a middle part and a right part, and the left current spreading layer CSL (7-1), the middle current spreading layer CSL (7-2) and the right current spreading layer CSL (7-3) are all positioned on the upper surface of the N-drift region (3);
the P-base area is divided into a left part, a middle part and a right part, the left side P-base area (5-1), the middle part P-base area (5-2) and the right side P-base area (5-3) are arranged, the left side P-base area (5-1) is positioned on the upper surface of the left side current spreading layer CSL (7-1), the middle part P-base area (5-2) is positioned on the upper surface of the middle part current spreading layer CSL (7-2), and the right side P-base area (5-3) is positioned on the upper surface of the left side current spreading layer CSL (7-3).
The N-source area is divided into four parts, namely a leftmost N-source area (9-1), a middle left N-source area (9-2), a middle right N-source area (9-3) and a rightmost N-source area (9-4), wherein the leftmost N-source area (9-1) is positioned on the upper surface of the left P-base area (5-1), the middle left N-source area (9-2) and the middle right N-source area (9-3) are both positioned on the upper surface of the middle P-base area (5-2), and the rightmost N-source area (9-4) is positioned on the upper surface of the right P-base area (5-3);
the P-plus area is divided into three parts, a left P-plus area (8-1), a middle P-plus area (8-2) and a right P-plus area (8-3), the left P-plus area (8-1) is positioned on the upper surface of the left P-base area (5-1), the left side of the leftmost N-source area (9-1), a middle P-plus area (8-2) is positioned on the upper surface of the middle P-base area (5-2), the middle of the middle left side N-source area (9-2) and the middle right side N-source area (9-3), the right side P-plus area (8-3) is positioned on the upper surface of the right side P-base area (5-3), and the right side of the rightmost N-source area (9-4);
a polysilicon gate (6);
a polycrystalline silicon source (13) positioned on the right side of the middle P-base region (5-2) and the middle current spreading layer CSL (7-2), and on the left side of the right P-base region (5-3) and the right current spreading layer CSL (7-3);
gate oxides (11) positioned on the left side, the right side and the lower surface of the polysilicon gate (6);
the P-shielding area is divided into two parts, namely a left side P-shielding area (4-1) and a right side P-shielding area (4-2), the left side P-shielding area (4-1) is located on the upper surface of the N-drift area (3), the lower surface of the gate oxide (11), the right side P-shielding area (4-1) is located on the lower surface of the polycrystalline silicon source (13), the upper surface of the N-drift area (3) is arranged, and all the P-shielding areas are grounded;
the isolation oxygen (10) is arranged on the upper surfaces of the leftmost N-source area (9-1), the polysilicon gate (6) and the left N-source area (9-2) in the part;
the source metal layer (12) is positioned on the upper surfaces of the left P-plus area (8-1), the partial leftmost N-source area (9-1), the isolated oxygen (10), the partial middle left N-source area (9-2), the middle P-plus area (8-2), the right P-plus area (8-3), the middle right N-source area (9-3), the polycrystalline silicon source (13) and the rightmost N-source area (9-4);
the polycrystalline silicon source (13) is in contact with the N-drift region (3) to form a heterojunction, the polycrystalline silicon source is a heterojunction anode, and the N-drift region is a heterojunction cathode.
2. The SiC trench MOSFET structure of claim 1 in which the gate oxide thickness is from 40nm to 150 nm.
3. The SiC trench MOSFET structure of claim 1, wherein the polysilicon gate and the polysilicon source are both polysilicon, the polysilicon is doped N-type, the dopant element is phosphorus, and the dopant concentration is 1 x 1019～1×1020cm-3。
4. The structure of claim 1, wherein the current spreading layer CSL is SiC, the doping type is N-type epitaxial doping, the doping element is N or P, and the doping concentration is 1 x 1016～1×1018cm-3The thickness is 1 to 5 μm.
5. The SiC trench MOSFET structure of claim 1, wherein the P-shielding region is SiC, the doping type is P-type ion implantation, the doping element is Al or B, and the doping concentration is 1 x 1018～1×1020cm-3The thickness is 1 to 5 μm.
6. The structure of claim 1, wherein the N-drift region is SiC, the doping type is N-type epitaxial doping, the doping element is nitrogen or phosphorus, and the doping concentration is 1 x 1013～5×1016cm-3The thickness is 5 to 30 μm.
CN202111402859.1A 2021-11-24 2021-11-24 SiC groove type MOSFET structure with built-in heterojunction diode Pending CN114203821A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116230549A (en) * 2023-04-27 2023-06-06 浙江大学 Trench type insulated gate field effect transistor integrated with low barrier diode and manufacturing method thereof

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116230549A (en) * 2023-04-27 2023-06-06 浙江大学 Trench type insulated gate field effect transistor integrated with low barrier diode and manufacturing method thereof
CN116230549B (en) * 2023-04-27 2023-08-29 浙江大学 Trench type insulated gate field effect transistor integrated with low barrier diode and manufacturing method thereof

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