CN116230549B

CN116230549B - Trench type insulated gate field effect transistor integrated with low barrier diode and manufacturing method thereof

Info

Publication number: CN116230549B
Application number: CN202310492983.4A
Authority: CN
Inventors: 徐弘毅; 盛况; 任娜
Original assignee: Zhejiang University ZJU
Current assignee: Zhejiang University ZJU
Priority date: 2023-04-27
Filing date: 2023-04-27
Publication date: 2023-08-29
Anticipated expiration: 2043-04-27
Also published as: CN116230549A

Abstract

The present disclosure relates to trench insulated gate field effect transistors integrated with low barrier diodes and methods of making the same. The method comprises the following steps: forming a first trench in the prefabricated semiconductor structure, the prefabricated semiconductor structure comprising a stacked structure and a second source contact region, the first trench and the second source contact region being separated by the first source contact region, the first trench extending through the first source contact region and the channel layer and into the first diffusion region; forming a second diffusion region with the first doping type, wherein the second diffusion region penetrates through the protection layer from at least the bottom surface of the first groove along the stacking direction and extends into the composite substrate; forming a second groove in the prefabricated semiconductor structure, wherein the second groove penetrates through the first source contact region and the channel layer, and the second groove exposes the first diffusion region; forming a gate oxide structure in the first groove; and forming a source extension in the second trench, wherein the source extension is in electrical contact with the first diffusion region. The method can manufacture the trench type insulated gate field effect transistor integrated with the low barrier diode with low degradation risk.

Description

Trench type insulated gate field effect transistor integrated with low barrier diode and manufacturing method thereof

Technical Field

The present disclosure relates to the field of semiconductor technology, and in particular, to a trench type insulated gate field effect transistor integrated with a low barrier diode and a method of manufacturing the same.

Background

Metal-oxide semiconductor field effect transistors (MOSFETs) may act as switches in a circuit. The MOSFET device has low switching loss and easy driving, so that the MOSFET device plays an important role in a plurality of fields such as power grids, new energy automobiles, national defense and military industry and the like.

To further improve the static performance of MOSFETs, technological routes are gradually transitioning from planar gate MOSFETs to trench gate MOSFETs, which reduce on-resistance by removing Junction Field Effect Transistor (JFET) region resistance, improving channel mobility, and reducing cell width.

The hierarchical nature of trench-gate MOSFETs poses challenges in their overall reliability when applied in high-field environments.

Disclosure of Invention

Based on the above, a trench type insulated gate field effect transistor integrated with a low barrier diode is provided to help reduce the body diode freewheel loss, and improve the reliability problem caused by bipolar degradation of the MOSFET body diode.

In a first aspect, embodiments of the present disclosure provide a method for fabricating a trench insulated gate field effect transistor integrated with a low barrier diode, the method comprising: forming a first groove in the prefabricated semiconductor structure, wherein the prefabricated semiconductor structure comprises a laminated structure and a second source contact region, the laminated structure comprises a composite substrate, a protective layer, a first diffusion region, a channel layer and a first source contact region which are sequentially stacked, the composite substrate, the first diffusion region and the first source contact region are provided with a first doping type, the channel layer, the second source contact region and the protective layer are provided with a second doping type, the second source contact region is electrically connected with the channel layer, the first groove and the second source contact region are separated by the first source contact region, and the first groove penetrates through the first source contact region and the channel layer and extends into the first diffusion region; forming a second diffusion region with a first doping type, wherein the second diffusion region penetrates through the protective layer from the bottom surface of the first groove along the stacking direction and extends into the composite substrate, and the second diffusion region is electrically connected with the first diffusion region; forming a second groove in the prefabricated semiconductor structure, wherein the second groove is positioned on one side of the second source contact region, which is away from the first groove, and penetrates through the first source contact region and the channel layer, and the second groove exposes the first diffusion region; forming a gate oxide structure in the first groove; and forming a source extension in the second trench, wherein the source extension is in electrical contact with the first diffusion region.

According to the method provided by the embodiment of the disclosure, the first diffusion region can be exposed by forming the second groove, and then the source extension part is formed, so that the first diffusion region is electrically contacted by the source extension part in the trench type insulated gate field effect transistor of the integrated low barrier diode manufactured by the method, the channel layer and the protection layer form pinch-off in the stacking direction, and the degradation risk of the structure formed by the source extension part and the first diffusion region is low. In the method provided by the embodiment of the disclosure, the low potential barrier diode is integrated as the freewheeling diode in the process of forming the trench type insulated gate field effect transistor, so that the loss of the body diode is reduced, the bipolar degradation is avoided, and the reliability of the trench type insulated gate field effect transistor is improved. In addition, by forming the first diffusion region, the current of the trench type insulated gate field effect transistor can be diffused, and the gate oxide structure formed in the first trench can be protected by matching with the protection layer.

In some embodiments, the source extension makes ohmic contact with the first diffusion region. Illustratively, the method includes the step of forming a first diffusion region. Illustratively, the first diffusion region may be formed to a thickness in the range of 0.2 μm to 1 μm.

By this arrangement, the channel layer and the protective layer can form a pinch-off barrier diode. The barrier height of the diode is controlled by the thickness of the first diffusion region and is continuously adjustable.

In some embodiments, the step of forming the source extension includes: forming a first metal layer, wherein the first metal layer and the first diffusion region realize Schottky contact; and forming a second metal layer, wherein the second metal layer is electrically connected with the first metal layer.

According to the method provided by the embodiment of the disclosure, the Schottky contact is performed on the first diffusion region by forming the first metal layer, so that the Schottky diode is formed in the trench type insulated gate field effect transistor integrated with the low barrier diode, which is formed by the method, and the pinch-off of the channel layer and the protective layer can be formed, and the Schottky barrier is not directly exposed in the vertical electric field direction. The trench type insulated gate field effect transistor integrated with the low barrier diode formed by the method has the advantages of reliable high voltage and short circuit process.

In some embodiments, the second trench extends through the first diffusion region in the stacking direction.

The source electrode extension region is contacted with the first diffusion region in different directions, and the electric field state in the first diffusion region can be controlled according to requirements under the condition of protecting the gate oxide structure.

In a second aspect, embodiments of the present disclosure provide a trench insulated gate field effect transistor integrated with a low barrier diode, the trench insulated gate field effect transistor integrated with a low barrier diode comprising: the laminated structure comprises a composite substrate, a protective layer, a first diffusion region, a channel layer and a first source contact region which are sequentially stacked, wherein the composite substrate, the first diffusion region and the first source contact region are provided with a first doping type, and the channel layer and the protective layer are provided with a second doping type; the second source contact region is provided with a second doping type and is electrically connected with the channel layer; the second diffusion region is provided with a first doping type, penetrates through the protective layer along the stacking direction and extends into the composite substrate, and is electrically connected with the first diffusion region; a gate oxide structure penetrating the first source contact region and the channel layer and extending into the second diffusion region, the gate oxide structure being separated from the second source contact region by the first source contact region; and the source electrode extension part is positioned at one side of the second source contact region, which is away from the gate oxide structure, penetrates through the first source contact region and the channel layer, and is in electrical contact with the first diffusion region.

By arranging the source electrode extension part to be in electrical contact with the first diffusion region, the trench type insulated gate field effect transistor integrated with the low barrier diode can well eliminate the degradation risk of the freewheel diode in the structure of the trench type insulated gate field effect transistor and can be widely applied. In addition, the first diffusion region of the trench type insulated gate field effect transistor of the integrated low barrier diode is used for diffusing device current and can be matched with a protective layer to protect a gate oxide structure.

In some embodiments, the source extension makes ohmic contact with the first diffusion region.

This arrangement helps to pinch off the channel layer from the protective layer. The barrier height of the diode can be well controlled, and the adaptability of the trench type insulated gate field effect transistor integrated with the low barrier diode is improved.

In some embodiments, the source extension includes a first metal layer in schottky contact with the first diffusion region and a second metal layer electrically connected to the first metal layer.

In the trench type insulated gate field effect transistor integrated with the low barrier diode, the first metal layer and the first diffusion region realize schottky contact, the schottky diode in the vertical direction of the stacking direction is formed, and the channel layer and the protection layer form pinch-off in the stacking direction. In the high-voltage state, the Schottky barrier is not directly exposed in the vertical electric field direction, so that the reduction of the height of the surface barrier can be restrained; in the short circuit process, the trench type insulated gate field effect transistor integrated with the low barrier diode has the advantage, so that the problem of early failure of the Schottky junction position caused by the reduction of the barrier height can be avoided.

In some embodiments, the source extension extends through the first diffusion region in the stacking direction.

With this arrangement, the position of the schottky contact or ohmic contact can be adjusted, and then the positional relationship of the potential barrier and the electric field can be adjusted to suppress the decrease in the surface potential barrier height. Different embodiments may be provided according to actual requirements.

In some embodiments, the trench isolation gate field effect transistor integrated with the low barrier diode has a first cell location and a second cell location, the direction of the first cell location opposite the second cell location being perpendicular to the stacking direction and perpendicular to the direction of the second source contact region opposite the gate oxide structure; the part of the second source contact region located at the first cell position penetrates through the channel layer along the stacking direction; the part of the second source contact region at the second cell position penetrates through the channel layer and the first diffusion region along the stacking direction, and the part of the source extension part at the second cell position extends into the second source contact region and is electrically contacted with the second source contact region.

So configured, at the second cell location, the source extension is in electrical contact with the second source contact region and the second source contact region is connectable with the protective layer, which helps to inhibit charge accumulation of the protective layer during dynamic processes.

In a third aspect, embodiments of the present disclosure provide an electronic component comprising: a circuit; and the trench type insulated gate field effect transistor integrated with the low barrier diode is electrically connected with the circuit.

By arranging the trench type insulated gate field effect transistor integrated with the low barrier diode, the controllability of the electronic element is higher, the application range is wider, the trench type insulated gate field effect transistor integrated with the low barrier diode can provide the function of a freewheel diode for a circuit, and the electronic element has longer service life.

Drawings

Fig. 1 is a flow diagram of a method of fabricating a trench insulated gate field effect transistor integrated with a low barrier diode provided by embodiments of the present disclosure;

FIG. 2 is a schematic structural view of a composite substrate in an embodiment of the present disclosure;

fig. 3 is a schematic structural view of a semiconductor structure after forming a pre-formed channel layer in an embodiment of the present disclosure;

fig. 4 is a schematic structural view of a semiconductor structure after forming a first source contact region in an embodiment of the present disclosure;

fig. 5 is a schematic structural view of a semiconductor structure after forming a second source contact region in an embodiment of the present disclosure;

fig. 6 is a schematic structural view of a semiconductor structure after forming a first trench in an embodiment of the present disclosure;

fig. 7 is a schematic structural view of a semiconductor structure after forming a second diffusion region in an embodiment of the present disclosure;

fig. 8 is a schematic structural view of a semiconductor structure after forming a second trench in an embodiment of the present disclosure;

Fig. 9 is a schematic structural view of a semiconductor structure after an insulating layer is formed in an embodiment of the present disclosure;

fig. 10 is a schematic structural diagram of a semiconductor structure after forming a gate in an embodiment of the disclosure;

FIG. 11 is a schematic diagram of a trench isolation gate field effect transistor with integrated low barrier diode after source formation in an embodiment of the disclosure;

fig. 12 is a schematic structural diagram of a trench type insulated gate field effect transistor integrated with a low barrier diode according to an embodiment of the present disclosure;

fig. 13 is a schematic structural diagram of a trench type insulated gate field effect transistor integrated with a low barrier diode according to an embodiment of the present disclosure;

fig. 14 is a schematic structural diagram of a trench type insulated gate field effect transistor integrated with a low barrier diode according to an embodiment of the present disclosure;

fig. 15 is a schematic structural diagram of a trench type insulated gate field effect transistor integrated with a low barrier diode according to an embodiment of the present disclosure;

FIG. 16 is a schematic diagram of a structure of a metal oxide semiconductor structure after forming a first metal layer in an embodiment of the disclosure;

FIG. 17 is a schematic cross-sectional view at A-A of FIG. 16;

FIG. 18 is a schematic cross-sectional view at B-B in FIG. 16;

FIG. 19 is a schematic cross-sectional view at C-C of FIG. 16;

fig. 20 is a schematic structural diagram of a trench type insulated gate field effect transistor integrated with a low barrier diode according to an embodiment of the present disclosure;

FIG. 21 is a schematic cross-sectional view at D-D of FIG. 20;

FIG. 22 is a schematic diagram of another semiconductor structure in a second cell position according to an embodiment of the present disclosure;

fig. 23 is a schematic structural diagram of a trench type insulated gate field effect transistor integrated with a low barrier diode according to an embodiment of the present disclosure;

fig. 24 is a schematic structural diagram of a trench-type insulated gate field effect transistor integrated with a low barrier diode according to an embodiment of the present disclosure;

fig. 25 is a schematic structural diagram of a trench type insulated gate field effect transistor integrated with a low barrier diode according to an embodiment of the present disclosure;

fig. 26 is a schematic structural diagram of a trench type insulated gate field effect transistor integrated with a low barrier diode according to an embodiment of the present disclosure;

fig. 27 is a schematic structural diagram of a trench-type insulated gate field effect transistor integrated with a low barrier diode according to an embodiment of the present disclosure;

fig. 28 is a schematic structural diagram of a trench type insulated gate field effect transistor integrated with a low barrier diode according to an embodiment of the present disclosure;

fig. 29 is a schematic structural diagram of a trench-type insulated gate field effect transistor integrated with a low barrier diode according to an embodiment of the present disclosure;

fig. 30 is a schematic structural diagram of a trench-type insulated gate field effect transistor integrated with a low barrier diode according to an embodiment of the present disclosure;

Fig. 31 is a schematic structural diagram of a trench type insulated gate field effect transistor integrated with a low barrier diode according to an embodiment of the present disclosure;

fig. 32 is a block diagram of an electronic component provided in an embodiment of the present disclosure.

Reference numerals illustrate: 100. prefabricating a laminated structure; 101. a composite substrate; 102. a substrate; 103. an epitaxial layer; 104. a protective layer; 105. a first diffusion region; 106. prefabricating a channel layer; 107. a channel layer; 108. a first source contact region; 109. a second source contact region; 110. a first groove; 111. a second diffusion region; 112. a second groove; 113. an insulating layer; 114. a gate; 115. a gate oxide structure; 116. a source electrode structure; 117. a source extension; 118. a source electrode covering part; 119. a first metal layer; 120. a second metal layer; 20. an electronic component; 200. prefabricating a semiconductor structure; 300. a trench insulated gate field effect transistor; 400. a circuit.

Detailed Description

In order to make the above objects, features and advantages of the embodiments of the present disclosure more comprehensible, a detailed description of specific embodiments of the present disclosure is provided below with reference to the accompanying drawings. In the following description, numerous specific details are set forth in order to provide a thorough understanding of embodiments of the present disclosure. The disclosed embodiments may be embodied in many other forms other than described herein and similar modifications may be made by those skilled in the art without departing from the spirit of the disclosed embodiments, so that the disclosed embodiments are not limited to the specific examples of embodiments described below.

In the description of the embodiments of the present disclosure, it should be understood that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," "axial," "radial," "circumferential," etc. indicate or are based on the orientation or positional relationship shown in the drawings, merely for convenience of describing the embodiments of the present disclosure and to simplify the description, and do not indicate or imply that the devices or elements referred to must have a particular orientation, be configured and operated in a particular orientation, and thus should not be construed as limiting the embodiments of the present disclosure.

Furthermore, the terms "first," "second," "third," and the like are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include at least one such feature. For example, a first cell may also be referred to as a second cell, which may also be referred to as a first cell. In the description of the embodiments of the present disclosure, the meaning of "a plurality" is at least two, such as two, three, etc., unless explicitly specified otherwise.

In the presently disclosed embodiments, the terms "connected," "connected," and the like are to be construed broadly and, unless otherwise specifically indicated and defined, as being either fixedly connected, detachably connected, or integrally formed, for example; can be flexible connection or rigid connection along at least one direction; can be mechanically or electrically connected; either directly or indirectly, through intermediaries, or both, may be in communication with each other or in interaction with each other, unless expressly defined otherwise. The terms "mounted," "disposed," "secured," and the like may be construed broadly as connected. The specific meaning of the above terms in the embodiments of the present disclosure may be understood by those of ordinary skill in the art according to specific circumstances.

In the presently disclosed embodiments, unless expressly stated and limited otherwise, a first feature "up" or "down" on a second feature may be that the first and second features are in direct contact, or that the first and second features are in indirect contact via an intermediary. Moreover, a first feature being "above," "over" and "on" a second feature may be a first feature being directly above or obliquely above the second feature, or simply indicating that the first feature is level higher than the second feature. The first feature being "under", "below" and "beneath" the second feature may be the first feature being directly under or obliquely below the second feature, or simply indicating that the first feature is less level than the second feature.

It will be understood that when an element is referred to as being "fixed" or "disposed" on another element, it can be directly on the other element or intervening elements may also be present. When an element is referred to as being "connected" to another element, it can be directly connected to the other element or intervening elements may also be present. The terms "vertical," "horizontal," "upper," "lower," "left," "right," and the like are used herein for illustrative purposes only and are not meant to be the only embodiment.

Referring to fig. 1, fig. 1 shows a schematic flow chart of a method for manufacturing a trench insulated gate field effect transistor integrated with a low barrier diode in an embodiment of the present disclosure, and a method 10 for manufacturing a trench insulated gate field effect transistor integrated with a low barrier diode in an embodiment of the present disclosure includes the following steps.

Step S101, forming a first groove. The first trench is located in the prefabricated semiconductor structure. Illustratively, the prefabricated semiconductor structure includes a stacked structure and a second source contact region. The laminated structure comprises a composite substrate, a protective layer, a first diffusion region, a channel layer and a first source contact region which are stacked in sequence. The composite substrate, the first diffusion region and the first source contact region have a first doping type, and the channel layer, the second source contact region and the protective layer have the second doping type. The second source contact region is electrically connected with the channel layer. The first trench is separated from the second source contact region by the first source contact region, and extends through the first source contact region and the channel layer and into the first diffusion region.

In step S102, a second diffusion region is formed. Illustratively, the second diffusion region has a first doping type. The second diffusion region is positioned at the bottom of the first groove, penetrates through the protection layer along the stacking direction and extends into the composite substrate, and is electrically connected with the first diffusion region.

Step S103, forming a second groove. The second trench is located in the prefabricated semiconductor structure. Illustratively, the second trench is located on a side of the second source contact region facing away from the first trench, in other words, the first trench is located on a side of the second source contact region facing away from the second trench. The second groove penetrates through the first source contact region and the channel layer, and the second groove exposes the first diffusion region.

Step S104, forming a gate oxide structure. The gate oxide structure is located in the first trench. Illustratively, the gate oxide structure includes a gate electrode and an insulating layer between the gate electrode and the prefabricated semiconductor structure, and the insulating layer may include an oxide.

In step S105, a source extension is formed. The source extension is located in the second trench. The source extension is in electrical contact with the first diffusion region. Illustratively, the material of the source extension includes a metal, and the source extension and the first diffusion region achieve a metal-to-semiconductor contact.

Illustratively, the method 10 further includes the step of forming a prefabricated semiconductor structure. In some aspects, the method 10 may further include the step of forming a drain structure.

According to the method for manufacturing the trench type insulated gate field effect transistor of the integrated low barrier diode, the first diffusion region can be exposed through the formation of the second groove, and then the source extension part is formed, so that the first diffusion region is electrically contacted by the source extension part in the trench type insulated gate field effect transistor of the integrated low barrier diode manufactured by the method, the channel layer and the protection layer form pinch-off in the stacking direction, and the degradation risk of a structure formed by the source extension part and the first diffusion region is low.

Fig. 2 to 11 are process diagrams showing a method for manufacturing a trench type insulated gate field effect transistor integrated with a low barrier diode, and the method provided by the embodiments of the present disclosure is described in detail with reference to fig. 2 to 11.

Referring to fig. 2, fig. 2 shows a schematic structural diagram of a composite substrate. Illustratively, the step of forming the prefabricated semiconductor structure includes: an epitaxial layer 103 is formed on one side of the substrate 102.

The substrate 102 and the epitaxial layer 103 may both have a first doping type, both of which may be used to construct the composite substrate 101. The composite substrate 101 may also include other structures. The material of the composite substrate 101 may include silicon carbide, and may also include at least one of silicon, germanium, silicon germanium, gallium arsenide, and gallium nitride. The substrate 102 may have N-type doping and the epitaxial layer 103 may also have N-type doping. The doping concentration of the substrate 102 may be greater than the doping concentration of the epitaxial layer 103.

Referring to fig. 3, fig. 3 shows a schematic structural diagram of a semiconductor structure after forming a pre-formed channel layer. Illustratively, the step of forming the prefabricated semiconductor structure includes: a protective layer 104, a first diffusion region 105 and a pre-fabricated channel layer 106 are formed on a side of the epitaxial layer 103 facing away from the substrate 102, which are stacked in order. The protection layer 104 and the pre-formed channel layer 106 may have a second doping type, specifically, P-type doping. The first diffusion region 105 may have N-type doping.

Illustratively, the protective layer 104 may be formed by an epitaxial process, and the first diffusion region 105 may be formed by an epitaxial process. In-situ doping may be performed while the epitaxial process is performed. Illustratively, the pre-formed channel layer 106 may be a P-well region formed by means such as ion implantation.

Referring to fig. 4, fig. 4 shows a schematic structure of the semiconductor structure after forming a first source contact region. The semiconductor structure shown in fig. 4 may be a prefabricated stack structure 100. Illustratively, the step of forming the prefabricated semiconductor structure includes: the prefabricated channel layer 106 is doped, forming a first source contact region 108 and resulting in a channel layer 107. The portion of the pre-formed channel layer 106 that is located below the first source contact region 108 may be considered as the channel layer 107. The first source contact region 108 may have a first doping type, which may be, for example, N-type heavy doping. The channel layer 107 may be a P-well region.

Referring to fig. 5, fig. 5 shows a schematic structural diagram of the semiconductor structure after forming the second source contact region. The semiconductor structure shown in fig. 5 may be a prefabricated semiconductor structure 200. Illustratively, the step of forming the prefabricated semiconductor structure 200 includes: the second source contact region 109 is formed by doping. The positions of the second source contact region 109 and the first source contact region 108 may be aligned by alignment according to the design position, and the second source contact region 109 and the first source contact region 108 may be formed by ion implantation. The semiconductor structure may have a first half-region a and a second half-region B, each of which may be configured to perform a conductive function. Illustratively, the semiconductor structure may have a substantially mirror-symmetrical shape, and thus may be of interest for its half-structure. The second source contact region 109 may have a second doping type, which may be, for example, P-type heavy doping. The second source contact region 109 may be electrically connected to the channel layer 107 through the first source contact region 108. As shown in fig. 5, the second source contact region 109 may penetrate the first source contact region 108 and the channel layer 107 from the upper side of the stacked structure.

Referring to fig. 6, fig. 6 shows a schematic structural view of the semiconductor structure after forming the first trench, which may also be substantially mirror symmetrical. The method for manufacturing the trench type insulated gate field effect transistor integrated with the low barrier diode provided by the embodiment of the disclosure comprises the step of forming the first trench 110, for example, forming the first trench 110 by etching. The first trench 110 and the second source contact region 109 may be separated by the first source contact region 108. The first trench 110 extends through the first source contact region 108 and the channel layer 107 and into the first diffusion region 105.

Referring to fig. 7, fig. 7 shows a schematic structure of the semiconductor structure after forming the second diffusion region. The method for manufacturing the trench type insulated gate field effect transistor integrated with the low barrier diode includes a step of forming the second diffusion region 111. The second diffusion region 111 may be formed by ion implantation, for example. The second diffusion region 111 may extend from the bottom surface of the first trench 110 into the epitaxial layer 103 of the composite substrate 101, and may also extend laterally at the bottom of the side surfaces of the first trench 110 to wrap around the bottom of the first trench 110. The second diffusion region 111 has a first doping type, for example, N-type doping.

Referring to fig. 8, fig. 8 shows a schematic structural view of the semiconductor structure after forming the second trench. The method for manufacturing the trench type insulated gate field effect transistor integrated with the low barrier diode includes a step of forming the second trench 112, for example, by etching the second trench 112. This step may etch the front second source contact region of the front semiconductor structure. The second source contact region 109 is shown in fig. 8 after the second trench 112 is formed. The second trenches 112 are located on the side of the corresponding second source contact region 109 facing away from the first trenches 110. For the entire semiconductor structure, the second trenches 112 may be formed on both sides of the first trench 110, i.e., on both sides of the two second source contact regions 109, respectively. As shown in fig. 8, the second trench 112 extends through the first source contact region 108 and the channel layer 107 in the stacking direction, and exposes the first diffusion region 105. Illustratively, the bottom surface of the second trench 112 exposes the first diffusion region 105.

Referring to fig. 9, fig. 9 shows a schematic structural diagram of the semiconductor structure after forming an insulating layer. In the disclosed embodiment, the step of forming the gate oxide structure 115 (fig. 10) includes a sub-step of forming the insulating layer 113. As shown in fig. 9, the insulating layer 113 is located at an inner wall of the first trench 110, and a bottom surface of the inner wall of the insulating layer 113 may be lower than the channel layer 107. The insulating layer 113 may be formed by deposition, and a material of the insulating layer 113 may include an oxide. Illustratively, the portion of the front-end semiconductor structure exposed to the first trench 110 may be oxidized into the insulating layer 113 by oxidation.

Referring to fig. 10, fig. 10 shows a schematic structural diagram of the semiconductor structure after forming a gate. In the disclosed embodiment, the step of forming the gate oxide structure 115 (fig. 10) includes a sub-step of forming the gate 114. The gate 114 may be deposited or filled in the first trench 110 and isolated from the stacked structure by the insulating layer 113. The gate 114 may extend beyond the channel layer 107 to a depth that is useful for forming a field effect transistor with the stacked structure. The material of the gate 114 may include polysilicon, or other conductive material.

Referring to fig. 11, fig. 11 shows a schematic structure of a trench type insulated gate field effect transistor integrated with a low barrier diode after forming a source. The method provided by the embodiments of the present disclosure includes the step of forming the source structure 116. Illustratively, the source structure 116 includes a source extension 117 and a source cap 118 of unitary structure. The step of forming the source structure 116 may be considered to include a sub-step of forming the source extension 117 and a sub-step of forming the source cap 118. The material of the source structure 116 includes a metal.

The source extension 117 is located in the second trench 112 and electrically contacts the first diffusion region 105. Illustratively, along the Y-axis direction, a bottom surface of the source extension 117 makes electrical contact with a top surface of the first diffusion region 105. Illustratively, the source extension 117 makes ohmic contact with the first diffusion region 105. The source cover 118 may cover and be electrically connected to the source extension 117, the second source contact region 109 and the first source contact region 108. The source cover 118 is spaced from the gate 114.

In an exemplary embodiment, in the step of forming the second trenches 112, the second trenches 112 extend through the first diffusion region 105. Then, the source extension 117 formed in the second trench 112 may also extend into at least the first diffusion region 105, as shown in fig. 12, and fig. 12 shows a schematic structure of the trench type insulated gate field effect transistor integrated with the low barrier diode after forming the source. In other embodiments, referring to fig. 13, fig. 13 shows a schematic structure of another trench-type insulated gate field effect transistor integrated with a low barrier diode after forming a source. The method provided by the embodiment of the present disclosure can control the shape of the contact surface of the formed source extension 117 and the first diffusion region 105 and the position and posture of the contact surface with respect to the stacking direction by setting the depth of the second trench 112, and can control the barrier height of the pinch-off barrier diode formed by the channel layer 107 and the protection layer 104, so as to provide various circuit characteristics.

Referring to fig. 14, fig. 14 shows a schematic structure of another trench-type insulated gate field effect transistor integrated with a low barrier diode after forming a source. In an exemplary embodiment, the substeps of forming the source extension 117 include: a first metal layer 119 is formed and a second metal layer 120 is formed. The first metal layer 119 and the second metal layer 120 may be formed, for example, by sputtering. Illustratively, the second metal layer 120 and the source cap 118 are a unitary structure that is continuously formed in the same substep. The first metal layer 119 makes schottky contact with the first diffusion region 105. The second metal layer 120 is electrically connected to the first metal layer 119. Illustratively, the material of the first metal layer 119 may be different from the material of the second metal layer 120. The material of the first metal layer 119 may include at least one of titanium, molybdenum, nickel, aluminum, and tungsten.

The method provided by the embodiment of the present disclosure can manufacture a trench type insulated gate field effect transistor integrated with a low barrier diode as shown in fig. 11. Illustratively, as shown in fig. 11, the embodiment of the present disclosure provides a trench type insulated gate field effect transistor 300, in which a low barrier diode is integrated in the trench type insulated gate field effect transistor 300, which is a novel metal-oxide-semiconductor field effect transistor, and may also be referred to as a trench type insulated gate field effect transistor integrated with a low barrier diode. The trench-type insulated gate field effect transistor 300 includes a stacked structure, a second source contact region 109, a second diffusion region 111, a gate oxide structure 115, and a source extension 117.

The stacked structure may include a composite substrate 101, a protective layer 104, a first diffusion region 105, a channel layer 107, and a first source contact region 108 stacked in this order. The stacking direction may be along the Y-axis direction. The composite substrate 101, the first diffusion region 105 and the first source contact region 108 have a first doping type, e.g., N-type, and the channel layer 107 and the protection layer 104 have a second doping type, e.g., P-type.

The second source contact region 109 may penetrate the first source contact region 108 and be electrically connected to the channel layer 107. The second source contact region 109 may extend through the channel layer 107. The second source contact region 109 may have a second doping type.

The second diffusion region 111 has a first doping type. The second diffusion region 111 penetrates the protective layer in the stacking direction. The second diffusion region 111 may extend into the composite substrate 101, and the second diffusion region 111 may also extend into the first diffusion region 105.

The gate oxide structure 115 penetrates the first source contact region 108 and the channel layer 107, and the gate oxide structure 115 extends into the second diffusion region 111. The gate oxide structure 115 may extend through the first diffusion region 105 or may extend into only the first diffusion region 105 along the Y-axis direction, depending on the positional relationship between the first diffusion region 105 and the second diffusion region 111. The gate oxide structure 115 is separated from the second source contact region 109 by the first source contact region 108 adjacent to the second source contact region 109.

The source extension 117 is located on a side of the second source contact region 109 facing away from the gate oxide structure 115. The source extension 117 extends through the first source contact region 108 and the channel layer 107. The source extension 117 makes electrical contact with the first diffusion region 105. Illustratively, the trench-type insulated gate field effect transistor 300 includes a source cover 118, and the source extension 117 and the source cover 118 may be in a unitary structure. The source cap 118 is located on a side of the first source contact region 108 facing away from the channel layer 107.

The trench insulated gate field effect transistor 300 provided in the embodiments of the present disclosure is a novel trench MOSFET device integrated with a low barrier diode. By providing the source extension 117 in electrical contact with the first diffusion region 105, for example, metal-semiconductor contact is achieved, such that the trench-type insulated gate field effect transistor 300 forms a current path in the lateral direction (X-axis direction). The formation of the current path can enable the trench insulated gate field effect transistor 300 to be used reliably, and the degradation failure risk is low.

In some embodiments, the source extension 117 makes ohmic contact with the first diffusion region 105. The channel layer 107 and the protective layer 104 below it can be used to form a pinch-off barrier diode, the barrier height of which is controlled by the thickness of the first diffusion region 105 in the Y-axis direction and can be arbitrarily valued in successive numerical intervals as required. Illustratively, the thickness of the first diffusion region 105 is in the range of 0.2 μm to 1 μm, for example 0.5 μm. As shown in fig. 11, in the Y-axis direction, the bottom surface of the source extension 117 makes ohmic contact with the top surface of the first diffusion region 105.

In other embodiments, as shown in fig. 12, the source extension 117 may extend through the first diffusion region 105. It is understood that the two source extensions 117 may have a generally symmetrical structure, but may also be asymmetrical, e.g., the left source extension 117 extends through the first diffusion region 105, while the right source extension 117 does not extend through the first diffusion region 105. Along the X-axis direction, the source extension 117 is in electrical contact with the first diffusion region 105, for example, an ohmic contact. The first diffusion region 105 may not extend beyond the sides of the second source contact region 109, illustratively, the portion of the second trench 112 that exposes the first diffusion region 105 is etched.

Fig. 13 illustrates a trench insulated gate field effect transistor integrated with a low barrier diode provided by embodiments of the present disclosure. In the trench type insulated gate field effect transistor 300, the source extension 117 penetrates the first diffusion region 105 along the Y-axis direction. The first diffusion region 105 protrudes from the second source contact region 109 along the X-axis direction. The first diffusion region 105 is stepped and the source extension 117 may be in ohmic contact with both the top and side surfaces of the first diffusion region 105.

Illustratively, fig. 14 shows a trench insulated gate field effect transistor integrated with a low barrier diode provided by embodiments of the present disclosure. In the trench type insulated gate field effect transistor 300, the source extension 117 is electrically contacted with the first diffusion region 105 along the stacking direction. Illustratively, the source extension 117 includes a first metal layer 119 and a second metal layer 120. The first metal layer 119 may make schottky contact with the first diffusion region 105. The second metal layer 120 is located on a side of the first metal layer 119 facing away from the first diffusion region 105 and is electrically connected to the first metal layer 119. By providing the first metal layer 119 in schottky contact with the first diffusion region 105, the first diffusion region 105 of the trench isolation gate fet 300 has a schottky diode that is substantially transverse to the stacking direction, and the channel layer 107 and the protective layer 104 on both sides of the first diffusion region 105 form pinch-offs along the stacking direction. In the high-voltage state, the barrier of the schottky diode is not directly exposed to the electric field in the stacking direction, which can suppress the reduction in the surface barrier height. Meanwhile, by utilizing the advantages, the trench type insulated gate field effect transistor 300 can avoid the advanced failure of the Schottky junction position caused by the reduction of the barrier height in the short circuit process.

Referring to fig. 15, fig. 15 illustrates a trench insulated gate field effect transistor integrated with a low barrier diode provided for an embodiment of the present disclosure. In the trench-type insulated gate field effect transistor 300, the source extension 117 penetrates through the first diffusion region 105, and the source extension 117 includes the first metal layer 119 and the second metal layer 120. The first diffusion region 105 may not protrude from the second source contact region 109 in the X-axis direction. The first metal layer 119 may make schottky contact with the sides of the first diffusion region 105. The second metal layer 120 may cover the protective layer 104 and the first metal layer 119. The second metal layer 120 may be in a unitary structure with the source cap 118.

Referring to fig. 16, fig. 16 shows a schematic structural diagram of a metal oxide semiconductor structure after forming a first metal layer in an embodiment of the present disclosure. For example, during the formation of the metal oxide semiconductor structure, the patterning of the second source contact region 109 and the patterning of the second trench may be achieved using a mask. The metal oxide semiconductor structure shown in fig. 16 is a structure after the first metal layer 119 has been formed in the second trench in the previous step. The MOS structure may include a first cell, a fourth cell, a second cell and a third cell disposed along the Z-axis, the first cell having a cross-sectional configuration shown in FIG. 17, the second cell having a cross-sectional configuration shown in FIG. 18, and the third cell having a cross-sectional configuration shown in FIG. 19. The four cell divisions may be based on the pattern of the second source contact 109 along the Z-axis direction.

Referring to fig. 16 and 17, in an exemplary method of fabricating a trench type insulated gate field effect transistor integrated with a low barrier diode, a second trench may be formed to penetrate the first source contact region 108, the channel layer 107, and the first diffusion region 105 at A-A cross-sectional location. The first diffusion region 105 may protrude from the second source contact region 109 in a direction away from the gate oxide structure 115. The first metal layer 119 makes schottky contact with the first diffusion region 105. The thin size of the first metal layer 119 may allow structures, such as the protective layer 104, under the first diffusion region 105 to remain exposed.

Referring to fig. 16 and 18, the second source contact region 109 is separated from the gate oxide structure by the first source contact region 108 and also by the channel layer 107.

Referring to fig. 16 and 19, the second source contact region 109 penetrates the first source contact region 108 and the channel layer 107 and may be blocked by the first diffusion region 105. The second source contact region 109 is spaced apart from the gate oxide structure 115.

Referring to fig. 20, fig. 20 shows a schematic structural diagram of a trench type insulated gate field effect transistor integrated with a low barrier diode. The trench isolation gate field effect transistor 300 includes a source structure 116. Fig. 21 is a schematic cross-sectional view at D-D in fig. 20. As shown in fig. 21, the source structure 116 may include a source extension 117 and a source cap 118. The source extension 117 includes a first metal layer 119 and a second metal layer 120. The second metal layer 120 may be electrically connected to the first metal layer 119 and may extend to the protection layer 104. The source cover 118 may be located at a side of the first source contact region 108 facing away from the channel layer 107, and may cover the second source contact region 109 and a portion of the first source contact region 108. The source cover 118 may be electrically connected to the second metal layer 120, and the source cover 118 is spaced apart from the gate 114 of the gate oxide structure 115. The schottky diode of the trench insulated gate field effect transistor 300 has better performance and higher reliability.

In other embodiments, the method for manufacturing the trench type insulated gate field effect transistor integrated with the low barrier diode provided in the embodiments of the present disclosure, fig. 22 shows a schematic cross-sectional view of the semiconductor structure at the second cell position after the second trench is formed. The portion of the second source contact region 109 at the B-B position penetrates the first source contact region 108, the channel layer 107 and the first diffusion region 105. Illustratively, portions of the second source contact region 109 at other cell locations remain unperforated from the first diffusion region 105, which second source contact region 109 may be formed by controlling the depth of ion implantation.

When the second trench 112 is etched, the portion of the second source contact region 109 at B-B is also etched, forming a step shape. The depth of the trench shape of the second trench 112 at B-B may exceed the first source contact region 108 and extend at least into the channel layer 107. Illustratively, the trench depth at B-B may be different from the trench depths at other locations, and may be achieved by step etching, for example, where the second trenches 112 at the first cells still extend through the first diffusion region 105. Then, in the step of forming the source structure 116, the source extension 117 to be formed fills the second trench 112 also at B-B or the source extension 117 to be formed may fill the gap of the second source contact region 109. Illustratively, the source structure 116 to be formed may be in ohmic contact with the second source contact region 109 and the source structure 116 may be in ohmic contact with the first source contact region 108. By forming a step in the second source contact region 109, the performance of ohmic contact can be enhanced, the contact effect to the protective layer 104 can be improved, and charge accumulation in the protective layer 104 during dynamic processes can be suppressed.

Referring to fig. 11 to 15 and 21, in the trench type insulated gate field effect transistor 300 provided in the embodiment of the present disclosure, the profile of the gate oxide structure 115 in the XY plane is substantially rectangular, and illustratively, both corners of the bottom of the first trench 110 may be right-angled. Then, the overall shape of the second diffusion region 111 in the XY plane is substantially rectangular.

Referring to fig. 23, fig. 23 shows a trench insulated gate field effect transistor integrated with a low barrier diode. The source structure 116 of the trench isolation gate fet 300 includes a source extension 117 and a source cap 118. The source extension 117 includes a first metal layer 119 and a second metal layer 120. The source extension 117 extends through the first source contact region 108 and the channel layer 107. The first metal layer 119 makes schottky contact with the first diffusion region 105 along the Y-axis direction and the X-axis direction, and the second metal layer 120 is electrically connected to the first metal layer 119 and may extend to the protection layer 104. The profile of the gate oxide structure 115 of the trench isolation gate fet 300 in the XY plane may be polygonal, for example, the bottom of the gate oxide structure 115 may be trapezoidal. The overall outer contour of the second diffusion region 111 may have a trapezoid shape, and in summary, the cross section of the second diffusion region 111 in the XY plane may have a polygonal shape.

Referring to fig. 24, fig. 24 shows a trench insulated gate field effect transistor integrated with a low barrier diode. The source structure 116 of the trench isolation gate fet 300 includes a source extension 117 and a source cap 118. The source extension 117 includes a first metal layer 119 and a second metal layer 120. The source extension 117 extends through the first source contact region 108, the channel layer 107, and the first diffusion region 105. The first metal layer 119 makes schottky contact with the first diffusion region 105 in the X-axis direction. The second metal layer 120 is electrically connected to the first metal layer 119 and may extend to the passivation layer 104. The profile of the gate oxide structure 115 of the trench isolation gate fet 300 in the XY plane may be polygonal, for example, the bottom of the gate oxide structure 115 may be trapezoidal. The overall outer contour of the second diffusion region 111 may have a trapezoid shape, and in summary, the cross section of the second diffusion region 111 in the XY plane may have a polygonal shape.

Referring to fig. 25, fig. 25 shows a trench insulated gate field effect transistor integrated with a low barrier diode. The source structure 116 of the trench isolation gate fet 300 includes a source extension 117 and a source cap 118. The source extension 117 includes a first metal layer 119 and a second metal layer 120. The source extension 117 extends through the first source contact region 108 and the channel layer 107. The first metal layer 119 makes schottky contact with the first diffusion region 105 in the Y-axis direction. The second metal layer 120 is electrically connected to the first metal layer 119. The profile of the gate oxide structure 115 of the trench isolation gate fet 300 in the XY plane may be polygonal, for example, the bottom of the gate oxide structure 115 may be trapezoidal. The overall outer contour of the second diffusion region 111 may have a trapezoid shape, and in summary, the cross section of the second diffusion region 111 in the XY plane may have a polygonal shape.

Referring to fig. 26, fig. 26 shows a trench insulated gate field effect transistor integrated with a low barrier diode. The source structure 116 of the trench isolation gate fet 300 includes a source extension 117 and a source cap 118. The source extension 117 includes a first metal layer 119 and a second metal layer 120. The source extension 117 extends through the first source contact region 108 and the channel layer 107. The first metal layer 119 makes schottky contact with the first diffusion region 105 along the Y-axis direction and the X-axis direction, and the second metal layer 120 is electrically connected to the first metal layer 119 and may extend to the protection layer 104. The profile of the gate oxide structure 115 of the trench isolation gate fet 300 in the XY plane may be rounded rectangular, e.g., the bottom of the gate oxide structure 115 may include rounded corners. The overall outer contour of the second diffusion region 111 may be rounded rectangular, and in summary, the cross section of the second diffusion region 111 in the XY plane may be boat-shaped.

Referring to fig. 27, fig. 27 shows a trench insulated gate field effect transistor integrated with a low barrier diode. The source structure 116 of the trench isolation gate fet 300 includes a source extension 117 and a source cap 118. The source extension 117 includes a first metal layer 119 and a second metal layer 120. The source extension 117 extends through the first source contact region 108, the channel layer 107, and the first diffusion region 105. The first metal layer 119 makes schottky contact with the first diffusion region 105 in the X-axis direction. The second metal layer 120 is electrically connected to the first metal layer 119 and may extend to the passivation layer 104. The profile of the gate oxide structure 115 of the trench isolation gate fet 300 in the XY plane may be rounded rectangular, e.g., the bottom of the gate oxide structure 115 may include rounded corners. The overall outer contour of the second diffusion region 111 may be rounded rectangular, and in summary, the cross section of the second diffusion region 111 in the XY plane may be boat-shaped.

Referring to fig. 28, fig. 28 shows a trench insulated gate field effect transistor integrated with a low barrier diode. The source structure 116 of the trench isolation gate fet 300 includes a source extension 117 and a source cap 118. The source extension 117 includes a first metal layer 119 and a second metal layer 120. The source extension 117 extends through the first source contact region 108 and the channel layer 107. The first metal layer 119 makes schottky contact with the first diffusion region 105 in the Y-axis direction. The second metal layer 120 is electrically connected to the first metal layer 119. The profile of the gate oxide structure 115 of the trench isolation gate fet 300 in the XY plane may be rounded rectangular, e.g., the bottom of the gate oxide structure 115 may include rounded corners. The overall outer contour of the second diffusion region 111 may be rounded rectangular, and in summary, the cross section of the second diffusion region 111 in the XY plane may be boat-shaped.

Referring to fig. 29, fig. 29 shows a trench insulated gate field effect transistor integrated with a low barrier diode. The source structure 116 of the trench isolation gate fet 300 includes a source extension 117 and a source cap 118. The source extension 117 includes a first metal layer 119 and a second metal layer 120. The source extension 117 extends through the first source contact region 108 and the channel layer 107. The first metal layer 119 makes schottky contact with the first diffusion region 105 along the Y-axis direction and the X-axis direction, and the second metal layer 120 is electrically connected to the first metal layer 119 and may extend to the protection layer 104. The profile of the gate oxide structure 115 of the trench isolation gate fet 300 in the XY plane may be arch-shaped, for example, the bottom of the gate oxide structure 115 may have an arc shape. The overall outer contour of the second diffusion region 111 may be arcuate, and in summary, the cross-section of the second diffusion region 111 in the XY plane may approximate a meniscus shape.

Referring to fig. 30, fig. 30 shows a trench insulated gate field effect transistor integrated with a low barrier diode. The source structure 116 of the trench isolation gate fet 300 includes a source extension 117 and a source cap 118. The source extension 117 includes a first metal layer 119 and a second metal layer 120. The source extension 117 extends through the first source contact region 108, the channel layer 107, and the first diffusion region 105. The first metal layer 119 makes schottky contact with the first diffusion region 105 in the X-axis direction. The second metal layer 120 is electrically connected to the first metal layer 119 and may extend to the passivation layer 104. The profile of the gate oxide structure 115 of the trench isolation gate fet 300 in the XY plane may be arch-shaped, for example, the bottom of the gate oxide structure 115 may have an arc shape. The overall outer contour of the second diffusion region 111 may be arcuate, and in summary, the cross-section of the second diffusion region 111 in the XY plane may approximate a meniscus shape.

Referring to fig. 31, fig. 31 shows a trench insulated gate field effect transistor integrated with a low barrier diode. The source structure 116 of the trench isolation gate fet 300 includes a source extension 117 and a source cap 118. The source extension 117 includes a first metal layer 119 and a second metal layer 120. The source extension 117 extends through the first source contact region 108 and the channel layer 107. The first metal layer 119 makes schottky contact with the first diffusion region 105 in the Y-axis direction. The second metal layer 120 is electrically connected to the first metal layer 119. The profile of the gate oxide structure 115 of the trench isolation gate fet 300 in the XY plane may be arch-shaped, for example, the bottom of the gate oxide structure 115 may have an arc shape. The overall outer contour of the second diffusion region 111 may be arcuate, and in summary, the cross-section of the second diffusion region 111 in the XY plane may approximate a meniscus shape.

In other embodiments, the gate extension of the trench isolation gate field effect transistor integrated with the low barrier diode is in ohmic contact with the first diffusion region, and the gate oxide structure and the second diffusion region may be configured in various shapes such as multi-deformation, arched, rounded rectangle, and the like.

The trench type insulated gate field effect transistor integrated with the low barrier diode can realize different electrical properties and can be matched with different source electrode structures by arranging the gate oxide structures and the second diffusion regions in different shapes. The bottom of the first trench 110 may be provided in a different shape during fabrication to facilitate formation of the second diffusion region.

It should be understood that the trench type insulated gate field effect transistor integrated with the low barrier diode provided in the embodiments of the present disclosure may further include other structures, for example, an electrode structure may be disposed on a side of the composite substrate facing away from the gate oxide structure, and so on.

Referring to fig. 32, fig. 32 shows a block diagram of the structure of the electronic component. The disclosed embodiments provide in another aspect an electronic component 20, the electronic component 20 comprising a trench insulated gate field effect transistor 300 and a circuit 400. The electronic component 20 may be used in a high pressure environment.

The trench isolation gate fet 300 may be of the various embodiments described above. Which contributes to higher integration, higher power density and higher reliability of the electronic component 20.

The circuit 400 is electrically connected to the trench isolation gate fet 300. Illustratively, the circuit 400 may be electrically connected to the gate 114, the source structure 116, and the composite substrate 101, respectively. Illustratively, the circuit 400 may include metal interconnects or power contacts.

The technical features of the above-described embodiments may be arbitrarily combined, and all possible combinations of the technical features in the above-described embodiments are not described for brevity of description, however, as long as there is no contradiction between the combinations of the technical features, they should be considered as the scope of the description.

In the above-described embodiments, the order of execution of the steps is not limited unless explicitly stated and defined otherwise, and may be performed in parallel, for example, or may be performed sequentially in a different order. The sub-steps of the steps may also be performed in an interleaved manner. Various forms of procedures described above may be used, and steps may be reordered, added, or deleted as long as the desired results of the technical solutions provided by the embodiments of the present disclosure are achieved, which are not limited herein.

The above examples only represent a few embodiments of the invention, which are described in more detail and are not to be construed as limiting the scope of the invention. It should be noted that modifications and improvements can be made by those skilled in the art without departing from the inventive concept, which falls within the scope of the invention as claimed. The scope of the invention should, therefore, be determined with reference to the appended claims.

Claims

1. A method for fabricating a trench insulated gate field effect transistor integrated with a low barrier diode, comprising:

forming a first groove in a prefabricated semiconductor structure, wherein the prefabricated semiconductor structure comprises a laminated structure and a second source contact region, the laminated structure comprises a composite substrate, a protective layer, a first diffusion region, a channel layer and a first source contact region which are sequentially stacked, the composite substrate, the first diffusion region and the first source contact region have a first doping type, the channel layer, the second source contact region and the protective layer have a second doping type, the second source contact region is electrically connected with the channel layer, the first groove and the second source contact region are separated by the first source contact region, and the first groove penetrates through the first source contact region and the channel layer and extends into the first diffusion region;

forming a second diffusion region with the first doping type, wherein the second diffusion region penetrates through the protection layer from the bottom surface of the first groove along the stacking direction and extends into the composite substrate, and the second diffusion region is electrically connected with the first diffusion region;

it is characterized in that the method comprises the steps of,

Forming a second groove in the prefabricated semiconductor structure, wherein the second groove is positioned at one side of the second source contact region, which is away from the first groove, and penetrates through the first source contact region and the channel layer, and the second groove exposes the first diffusion region;

forming a gate oxide structure in the first groove; and

a source extension is formed within the second trench, wherein the source extension is in electrical contact with the first diffusion region.

2. The method for fabricating a trench insulated gate field effect transistor integrated with a low barrier diode of claim 1, wherein the source extension makes ohmic contact with the first diffusion region.

3. The method for fabricating a trench insulated gate field effect transistor integrated with a low barrier diode of claim 1, wherein the step of forming a source extension comprises:

forming a first metal layer, wherein the first metal layer and the first diffusion region realize Schottky contact; a kind of electronic device with high-pressure air-conditioning system

And forming a second metal layer, wherein the second metal layer is electrically connected with the first metal layer.

4. The method for fabricating a trench insulated gate field effect transistor integrated with a low barrier diode of claim 1, wherein the second trench extends through the first diffusion region in a stacking direction.

5. A trench insulated gate field effect transistor integrated with a low barrier diode, comprising:

the laminated structure comprises a composite substrate, a protective layer, a first diffusion region, a channel layer and a first source contact region which are sequentially stacked, wherein the composite substrate, the first diffusion region and the first source contact region are provided with a first doping type, and the channel layer and the protective layer are provided with a second doping type;

a second source contact region having the second doping type, the second source contact region being electrically connected to the channel layer;

the second diffusion region is provided with the first doping type, penetrates through the protective layer along the stacking direction and extends into the composite substrate, and is electrically connected with the first diffusion region;

it is characterized in that the method comprises the steps of,

a gate oxide structure extending through the first source contact region and the channel layer and into the second diffusion region, the gate oxide structure being separated from the second source contact region by the first source contact region; and

the source electrode extension part is positioned on one side, away from the gate oxide structure, of the second source contact region, penetrates through the first source contact region and the channel layer, and is in electrical contact with the first diffusion region.

6. The diode integrated low barrier trench isolation gate field effect transistor of claim 5, wherein the source extension makes ohmic contact with the first diffusion region.

7. The integrated low barrier diode trench isolation gate field effect transistor of claim 5, wherein the source extension comprises a first metal layer and a second metal layer, the first metal layer making schottky contact with the first diffusion region, the second metal layer being electrically connected with the first metal layer.

8. The diode integrated low barrier trench isolation gate field effect transistor of claim 5, wherein the source extension extends through the first diffusion region in the stacking direction.

9. The diode integrated trench isolation gate field effect transistor of claim 5, wherein the diode integrated trench isolation gate field effect transistor has a first cell location and a second cell location, the first cell location and the second cell location being opposite in direction perpendicular to the stacking direction and perpendicular to the second source contact region and the gate oxide structure opposite direction;

a portion of the second source contact region located at the first cell position penetrates through the channel layer along the stacking direction; the part of the second source contact region located at the second cell position penetrates through the channel layer and the first diffusion region along the stacking direction, and the part of the source extension part located at the second cell position extends into the second source contact region and is electrically contacted with the second source contact region.

10. An electronic component comprising:

a circuit; a kind of electronic device with high-pressure air-conditioning system

A trench isolation gate field effect transistor integrated with a low barrier diode as claimed in any one of claims 5 to 9 electrically connected to the circuit.